CN101009968A - Electronic carrier board - Google Patents
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- CN101009968A CN101009968A CNA2006100027264A CN200610002726A CN101009968A CN 101009968 A CN101009968 A CN 101009968A CN A2006100027264 A CNA2006100027264 A CN A2006100027264A CN 200610002726 A CN200610002726 A CN 200610002726A CN 101009968 A CN101009968 A CN 101009968A
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Abstract
The disclosed electric carrier plate comprises: a main body, at least two welding mats set on body surface in pairs, a protective layer covering body surface and forming an opening opposite to the mat position, wherein there are at least two same side walls on the opening to expose the mats, the first one is set vertically to the mat arrangement direction, while the second one is parallel. This invention can avoid different area of exposed mats, prevents electric element standing on the plate, fills insulation material between element and plate efficiently, and overcomes problem that it cannot form flow-in groove for package resin on small-size passive element bottom.
Description
Technical field
The invention relates to a kind of electronic carrier board, particularly about a kind of surface mounting technology (Surface Mounted Technology, electronic carrier board SMT) of being applied in.
Background technology
Along with the production of integrated circuits development of technology, the design and fabrication of electronic component continues the trend development towards granular, and because it possesses electronic circuit more extensive, high integration, so its product function is also more complete.
In this case, tradition is utilized plug-in type packaging technology (Through HoleTechnology; THT) connect the electronic component of putting,, thereby take for example printed circuit board (PCB) (Printed Circuit Board owing to size can't further be dwindled; PCB), circuit board (circuitboard) or the substrate big quantity spaces of electronic carrier board such as (substrate), adding the plug-in type packaging technology needs every placement of foot of corresponding each electronic component to hole on electronic carrier board, so the actual space that takies the electronic carrier board two sides of this type electronic component pin, and this electronic component and electronic carrier board junction solder joint are also bigger.Therefore in the program of electronic component assembling now, adopt surface mounting technology (Surface Mounted Technology in a large number; SMT), effectively electronic component is assembled on the electronic carrier board.
Use the electronic component of surface mounting technology, since its electricity connection end (pin) be welded on this electronic component with the one side electronic carrier board on, therefore, do not need boring in a large number in electronic carrier board as the plug-in type packaging technology, the pin of electronic component wears.Just use surface mounting technology can all assemble electronic component simultaneously on the electronic carrier board two sides, significantly promoted the space availability ratio of electronic carrier board, in addition, because the electronic component volume of surface mounting technology is less, electronic component compared to traditional plug-in type packaging technology, the quantity that the electronic component of use surface mounting technology is arranged on the electronic carrier board is comparatively intensive, therefore the electronic component cost that adds surface mounting technology is also more cheap, has risen to the main flow into assembling electronic component on the electronic carrier board now.
Moreover, based on electrically and the demand on the performance, on electronic carrier board, settle to have become and keep the indispensable step of the electrical steady quality of electronic product as electric capacity (Capacitor), resistance (Resistor) or inductance passive devices (PassiveComponents) such as (Inductor).
See also Figure 1A, it is to connect the floor map of putting the surface-adhered type passive device on substrate, cooperates simultaneously to consult Figure 1B and Fig. 1 C, and it is the generalized section that the hatching 1B-1B in should Figure 1A and hatching 1C-1C are formed.It mainly is to be formed with a pair of isolated weld pad 12 on the predeterminated position on the substrate 11, and these two weld pads 12 expose outside the opening 130 of the welding resisting layer (Solder Mask) 13 that is used to cover on this substrate 11 respectively; Behind an amount of tin cream (Solder Paste) 15 of coating on the weld pad 12, can connect respectively for the both ends of a passive device 14 and stick on the tin cream 15, give reflow welding (Reflow Soldering) again and handle, this passive device 14 just can suitably electrically connect by tin cream 15 and weld pad 12.Wherein, passive device 14 is corresponding then when weld pad, for avoiding because of the both sides cream tin 15 uneven phenomenons (Tombstone) of setting up a monument, therefore in design for wetting zones (wetting area) size that makes tin cream 15 is consistent, it is all symmetrical and big or small identical that institute forms the opening size that exposes outside these relative two weld pad 12 welding resisting layers 13.
When being applied in semiconductor package part, because the coating weight and tin cream 15 fusions when reflow is handled of tin cream 15, make passive device 14 highly be difficult to accurate control, add welding resisting layer 13 surface and out-of-flatnesses, in time, have depression to produce passive device 14 and 13 of this welding resisting layers cause welding often to form a gap (Clearance) 17, generally only there is 10 to 30 microns height in this type of gap 17, the particle size that is used to form its filler particles of resin material (Filler) of the packing colloid that coats passive device 14 is about 50 microns, greater than this clearance height.Therefore, when molding operation carried out filling with resin, the gap 17 of passive device 14 bottoms can't be filled up by resin, was formed with gas hole (void), cause gas explosion phenomenon (popcorn effect) takes place in the follow-up high-temperature operation environment, whole assembling structure is suffered damage; Also or make fusion tin cream 15 bore gap 17 (being capillarity) to form bridge joint, cause passive device 14 short circuits (shown in Figure 1B), thereby influence the acceptance rate of manufactured goods.
Simultaneously owing to be subjected to adjacent passive device 14 configuration affects, different passive devices 14 electrically conduct to the fusion tin cream 15 of weld pad 12, also might the flow through gap of 13 of weld pad 12 surface and welding resisting layers, again along gap counterdiffusion mutually, the contact of 13 of this substrate 11 and welding resisting layers, thereby generation scolding tin projection (solder extrusion) phenomenon, cause adjacent passive device 14 problem that is short-circuited, the label SE shown in Fig. 1 C.
Other sees also Fig. 2 A, United States Patent (USP) the 6th, 521, and No. 997 is between welding resisting layer 23 openings that form 22 of opposite soldering pads, sets up a groove (Groove) 230, provides resin to pass through by offering groove 230 expansion gaps.
Yet, this groove 330 offer the lower restriction of resolution (Resolution) that is subject to photosensitive type welding resisting layer 33, its width dimensions minimum only can be offered into 150 microns (μ m), and restriction because of the light shield aligning accuracy of welding pad opening, its weld pad welding resisting layer width M minimum needs 75 microns wide, therefore, along with component size dwindles gradually, between limited weld pad spacing, offer groove difficulty more.
This is to represent the length of this passive device and wide because be respectively by two groups of numerals the passive device dimensions (as 0603 type or 0402 type) that the semiconductor industry is used at present, this length and width unit is a unit with made in Great Britain (generally with the English inch) all, and with bigger array preceding.With 0402 cake core passive device is example, the 0402nd, the passive device of specific standard, the size of element is 0.040 English inch (length) * 0.020 English inch (wide), as be converted into metric unit and then be equivalent to length 0.040 * 25.4=1.016 millimetre (being about 1000 microns), width 0.020 * 25.4=0.508 millimetre (being about 500 microns) highly is generally 500 microns chip-shaped electric capacity, resistance or inductance.
Shown in Fig. 2 B, along with semiconductor product develops to light, thin, short, little direction gradually, present thin spherical grid array semiconductor package part (Thin﹠amp; Fine Ball Grid Array, TFBGA) packing colloid (Encapsulant) thickness has been developed to 530 microns, therefore, following slim packaging part certainly will can't hold 0402 cake core passive device of 500 microns of thickness, must change into adopting 0201 littler cake core passive device of size to reduce the packaging part integral thickness.The length of relevant 0201 cake core passive device is half of 0402 cake core passive device, micron (wide) * 250,500 microns (length) * 250 micron (height) just, be length (500 microns) restriction cooperate 0201 type small size passive device, spacing distance (Spacing) A1 on the substrate between two paired weld pads also is contracted to 275 microns from 400 microns.
Yet, welding resisting layer is a kind of photosensitive type (Photoimage) material, because the restriction of the light shield aligning accuracy of opening between low sensitization resolution and weld pad, the welding resisting layer minimum of this weld pad need have 75 microns width, at this moment, if according to above-mentioned United States Patent (USP) 6,521, No. 997 technology are offered the groove of 150 microns of width on the welding resisting layer between the weld pad, then shown in Fig. 2 B, the welding resisting layer width A2 that respectively exposes this groove of welding resisting layer extended distance of weld pad only is (275-150)/2=62.5 micron, therefore, width when between welding resisting layer opening that exposes weld pad and groove is reduced to 62.5 microns, has exceeded the minimum 75 microns manufacturing capacity of present substrate and can't make with existing processing procedure.
Also see also Fig. 3 A, No. 2005/0253231 technology of United States Patent (USP) is to form two welding resisting layer openings 330 that expose outside these two weld pad 32 opposing sidewalls respectively on two weld pads 32 that are provided with in pairs, and be provided with obstruct bar 331 330 of this openings, so as to forming runner 3300, block the edge resin and insert.
This technology still is subject to the lower restriction of resolution of photosensitive type welding resisting layer,, promptly can't form and intercept bar 331, thereby can't apply to 0201 type passive device during less than 275 microns in limited weld pad spacing.
This technology is when skew takes place in welding resisting layer in addition, can cause the wetting zones of two weld pads that unequal situation takes place, shown in Fig. 3 B, former pad area (exposing outside the welding resisting layer aperture area) for welding is A*B, welding resisting layer is if be offset X micron (conventional substrate processing procedure side-play amount ability is 75 microns) left, then the area of left weld pad will be B* (A+X), backhand welding pad area is B* (A-X), two pad area will have the difference of B* (A+X)-B* (A-X)=2BX, this wetting areas inequality, the passive device that can cause being welded on this weld pad phenomenon (Tombstone) of setting up a monument.
Moreover, above-mentioned United States Patent (USP) the 6th, 521, in the technology that No. 997 and No. 2005/0253231 are disclosed, in the face of adjacent passive device configuration affects, all can't provide the tin cream between the adjacent passive device of effective solution may be via the gap between this substrate surface and welding resisting layer and problem such as counterdiffusion, contact mutually, the scolding tin projection phenomenon that causes be even the problem that causes adjacent passive device to be short-circuited.
In sum, how a kind of electronic carrier board is provided, connect when putting on it at electronic component, can avoid producing and electrical bridge joint and scolding tin projection problem because of retaining the gapped gas hole that causes in electronic component and the electronic carrier board, avoid simultaneously forming the opening that exposes weld pad and producing off normal because of processing procedure precision and error problem make, cause the different and problems such as the phenomenon of setting up a monument of the dimensioned area that exposes outside this weld pad, reality is needed problem to be separated badly for industry.
Summary of the invention
For overcoming above-mentioned prior art problems, main purpose of the present invention is that a kind of electronic carrier board is being provided, and can avoid because of processing procedure precision and error problem make the off normal that forms the opening that exposes two paired weld pads, causes the equal problem of weld pad dimensioned area that exposes.
A further object of the present invention is that a kind of electronic carrier board is being provided, and avoids electronic component to connect and put the phenomenon (Tombstone) of setting up a monument on this electronic carrier board.
Another object of the present invention is that a kind of electronic carrier board is being provided, and the insulation material is filled between electronic component and electronic carrier board, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Another purpose of the present invention is that a kind of electronic carrier board is being provided, and can prevent to be electrically conducted and short circuit between adjacent electronic elements.
An also purpose of the present invention is that a kind of electronic carrier board is being provided, and (Surface Mounted Technology, SMT) problem that flows into groove for potting resin can't be formed on the passive device bottom to solve small-sized surface-adhered type.
For taking off on reaching and other purpose, the invention provides a kind of electronic carrier board, this electronic carrier board comprises: a main body; At least two weld pads of being located at this body surfaces in pairs; An and protective layer that is used to cover this body surfaces; this protective layer is formed with opening corresponding to this bond pad locations; this opening is each other in the same way and expose outside at least two first and second identical sidewalls of this two weld pads; this weld pad the first side wall is the direction that vertical this paired weld pad is laid; second sidewall is the direction that parallel this paired weld pad is laid, and the first side wall of at least one weld pad at interval the distance of this opening at least greater than 50 microns of the distances of its this opening of second sidewall spacers.In addition corresponding in these two paired weld pads that expose outside this protective layer opening; the first side wall that also can make these two weld pads simultaneously at interval distance of this opening all is greater than at least 50 microns of the distances of second this opening of sidewall spacers; and at least for the position at the protective layer opening that connects below the electronic component that places on this paired weld pad, at a distance of the distance of this weld pad the first side wall greater than apart from about 50 microns of the distance of second sidewall.
The invention still further relates to a kind of electronic carrier board, this electronic carrier board comprises: a main body; At least two weld pads of being located at this body surfaces in pairs; An and protective layer that is used to cover this body surfaces; this protective layer is formed with opening corresponding to this bond pad locations; this opening is to manifest the first, second, third and the 4th identical sidewall of these two weld pads each other in the same way and fully; wherein this first, the 4th sidewall is the direction that vertical this paired weld pad is laid; second, third sidewall is the direction that parallel this paired weld pad is laid, and the first side wall of at least one this weld pad at interval the distance of this opening at least greater than 50 microns of the distances of its second, third this opening of sidewall spacers.
The invention still further relates to a kind of electronic carrier board, this electronic carrier board comprises: a main body; At least two weld pads of being located at this body surfaces in pairs; And a protective layer that is used to cover this body surfaces, this protective layer is formed with opening corresponding to this bond pad locations, this opening is each other in the same way and expose outside this two the first side walls that weld pad is identical, this first side wall be vertically should paired weld pad laying direction.
The invention still further relates to a kind of electronic carrier board, this electronic carrier board comprises: a main body; At least two weld pads that are located at this body surfaces in pairs; An and protective layer that is used to cover this body surfaces; this protective layer is formed with opening corresponding to this bond pad locations; this opening is to manifest the first and the 4th identical sidewall of these two weld pads each other in the same way and fully; wherein this first and the 4th sidewall is the direction of that it(?) vertically should paired weld pad lay, and the distance of this opening of the first side wall of at least one this weld pad interval is at least greater than 50 microns of the distances of its this opening of the 4th sidewall spacers.
Therefore, the assembling structure of electronic carrier board formation of the present invention comprises: as above-mentioned electronic carrier board; Electronic component connects the weld pad of putting and be electrically connected to this electronic carrier board; Insulating resin coats this electronic component, and can be distributed in fully in this electronic component below and this electronic carrier board opening.Wherein this electronic carrier board is substrate, circuit board or printed circuit board (PCB) etc., and this protective layer is a welding resisting layer, and this electronic component is a passive device.
Therefore; in the electronic carrier board of the present invention; make the protective layer that is covered in the electronic carrier board surface; be formed with opening in the same way at least two weld pad places that dispose in pairs; so as to exposing outside these two weld pads sidewall in the same way; so forming protective layer (welding resisting layer) when opening is provided with; because of processing procedure precision and error; because this opening is to be located at this paired weld pad place in the same way; even if therefore off normal takes place; can avoid exposing outside the pad area difference of opening, make follow-up on this weld pad then during electronic component, the phenomenon of setting up a monument of avoiding the imbalance because of wetted area (wetting area) to cause.
Simultaneously; this protective layer opening can expose outside at least two first and second identical sidewalls of these two weld pads; also or expose outside at least three first, second, third identical sidewalls of these two weld pads; this weld pad the first side wall is the direction that vertical this paired weld pad is laid; second (the 3rd) sidewall is the direction that parallel this paired weld pad is laid, and this first side wall at interval the distance of this opening at least greater than 50 microns of the distances of this this opening of second (the 3rd) sidewall spacers.So, even if opening generation off normal, not only still can keep identical weld pad exposed area, the insulating resin (50 microns of average grain diameters) of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause, also can make insulating resin coat at least one side of this weld pad at least simultaneously, avoid taking place scolding tin projection (solder extrusion) phenomenon, avoid causing the adjacent electronic elements problem of short-circuit.
In addition; this protective layer opening also can manifest the first, second, third and the 4th identical sidewall of these two weld pads each other in the same way and fully; wherein this first, the 4th sidewall is the direction that vertical this paired weld pad is laid; second, third sidewall is the direction that parallel this paired weld pad is laid, and this first side wall at interval the distance of this opening at least greater than 50 microns of the distances of this second, third this opening of sidewall spacers.So, even if this opening generation off normal, still can keep the existing exposed area of this weld pad, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause still can make insulating resin coat this weld pad side fully, avoid taking place scolding tin projection phenomenon.
In addition; this protective layer opening is the first side wall that can only expose outside weld pad among the present invention; this the first side wall is the direction that vertical this paired weld pad is laid, so, and when forming the protective layer opening; because of processing procedure precision and error; because this opening is to be located at this two paired weld pad place in the same way,, still can avoid paired weld pad to expose outside the area difference of opening even if therefore off normal takes place for it; make follow-up on this weld pad then during electronic component, because of the imbalance of wetted area causes the phenomenon of setting up a monument.
Moreover; this protective layer opening can expose outside the first and the 4th sidewall of weld pad among the present invention; this the first and the 4th sidewall is the direction that vertical this paired weld pad is laid, and the distance of this this opening of the first side wall interval is at least greater than about 50 microns of the distance of the 4th this opening of sidewall spacers.So, even if this opening generation off normal, still can keep the existing exposed area size of this weld pad, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Simultaneously; one among the present invention in this protective layer opening is to expose outside wherein the first, second, third and the 4th sidewall of a weld pad comprehensively; relatively another opening is the first and the 4th sidewall that exposes outside another weld pad, and this first side wall at interval the distance of this opening at least greater than this second, third and about 50 microns of the distance of the 4th this opening of sidewall spacers.So, even if this opening generation off normal, still can keep the existing exposed area size of this weld pad, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Description of drawings
Figure 1A is that prior art connects the floor map of putting the surface mount passive device on substrate;
Figure 1B and Fig. 1 C are the generalized sections that the hatching 1B-1B in should Figure 1A and hatching 1C-1C are formed;
Fig. 2 A and Fig. 2 B are United States Patent (USP)s the 6th, 521, the passive device assembling schematic diagram of No. 997 announcements;
Fig. 3 A and Fig. 3 B are the passive device assembling schematic diagrames that United States Patent (USP) discloses for No. 2005/0253231;
Fig. 4 A and Fig. 4 B are the floor map of electronic carrier board embodiment 1 of the present invention;
Fig. 4 C is the floor map that the protective layer opening is offset left in the electronic carrier board of the embodiment of the invention 1;
Fig. 4 D is the different floor map of protective layer opening size in the electronic carrier board of the embodiment of the invention 1;
Fig. 5 is the floor map of electronic carrier board embodiment 2 of the present invention;
Fig. 6 A is the floor map of electronic carrier board embodiment 3 of the present invention;
Fig. 6 B is the floor map that the protective layer opening is offset to the right in the electronic carrier board of the embodiment of the invention 3;
Fig. 7 A to Fig. 7 C is the floor map of electronic carrier board embodiment 4 of the present invention;
Fig. 8 A and Fig. 8 B use assembling structure plane and the generalized section that electronic carrier board of the present invention forms;
Fig. 9 is the floor map of electronic carrier board embodiment 5 of the present invention;
Figure 10 is the floor map of electronic carrier board embodiment 6 of the present invention; And
Figure 11 is the floor map of electronic carrier board embodiment 7 of the present invention.
Embodiment
Embodiment 1
See also Fig. 4 A and Fig. 4 B, it is electronic carrier board embodiment 1 floor map of the present invention.
Electronic carrier board of the present invention comprises: a main body 411; At least two weld pads 42 that are located at these main body 411 surfaces in pairs; An and protective layer 43 that is used to cover this body surfaces; this protective layer 43 is being formed with opening 430 and 431 corresponding to these two weld pad 42 positions; this opening 430 and 431 is each other in the same way and expose outside the identical and width of two of this two weld pad 42 and be respectively the first side wall 421 of B and second sidewall 422 (or the 3rd sidewall 423) that width is A; forming a weld pad exposed area is two weld pads that are provided with in pairs of A*B; this weld pad the first side wall 421 is directions that vertical this paired weld pad 42 is laid; second sidewall 422 (or the 3rd sidewall 423) is the direction that parallel this paired weld pad 42 is laid; and this first side wall 421 is this opening 430 at interval; 431 distance D is at least greater than this opening 430 of this second sidewall 422 (or the 3rd sidewall 423) interval; 431 apart from about 50 microns of d (μ m).
In the present embodiment, protective layer (welding resisting layer) bit errors that adopts industry fully to use is that 75 microns processing procedure is illustrated, but non-as limit.When being 75 microns, should be can be more than or equal to 75 microns apart from d according to the ability of bit errors wherein, and distance D then is more than or equal to being 125 microns; In addition, when being 50 microns, should be can be then apart from d more than or equal to 50 microns as the bit errors ability, this distance D then is more than or equal to 100 microns.
So, even if opening 430,431 off normals (as 75 microns of off normals left) take place, two pad area that are provided with in pairs are all (A+75) * B shown in Fig. 4 C, not only can provide the identical weld pad of electronic component to connect and put area (wetting areas), and the insulating resin (50 microns of average grain diameters) that can make coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause, also can make insulating resin coat at least one side of this weld pad at least simultaneously, avoid taking place scolding tin projection (solder extrusion) phenomenon, avoid causing the adjacent electronic elements problem of short-circuit.
This electronic carrier board 41 can be base plate for packaging, circuit board or the printed circuit board (PCB) etc. that Chip Packaging is used, and mainly is that example describes with the base plate for packaging in the present embodiment.The body 411 of this electronic carrier board 41 can be the insulating barrier that insulating barrier or its middle storehouse have line layer, and is laid with a plurality of conducting wires (not marking) and weld pad 42 on its surface, and wherein part of solder pads is to be provided with in pairs.This insulating barrier is that for example materials such as glass fibre, epoxy resin (Epoxy), pi (polyimide) film, FR4 resin and BT (Bismaleimide Triazine) resin are made, and this line layer for example is the copper layer.Be coated with a protective layer 43 on this electronic carrier board body 411, this protective layer 43 for example is welding resisting layer (solder mask), and the material of this welding resisting layer is selected the high molecular polymer (Polymer) with high fluidity for use, as epoxy resin (Epoxy Resin) etc.This protective layer 43 forms opening 430 and 431 corresponding to 42 of at least two weld pads that are provided with in pairs, and wherein this opening 430 and 431 is each other in the same way and expose outside 42 2 the identical the first side walls 421 of these two weld pads and second sidewall 422.
Also see also Fig. 4 D; on this paired weld pad, connect when putting electronic component when follow-up; this is not located at the protective layer opening 431 of electronic component below; just be not positioned at the distance of the protective layer opening 431 of 42 of two paired weld pads apart from its weld pad the first side wall 421; be under 75 microns the condition in bit errors; still can be more than or equal to 75 microns (being can be under 50 microns the condition in addition) more than or equal to 50 microns in bit errors; so; even if opening 430; 431 off normals (as 75 microns of off normals left) take place; can make electronic component have identical weld pad equally connects and puts area (wetting areas); and the insulating resin (50 microns of average grain diameters) that can make coated electric components is fully distributed in electronic component below and this opening; gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause; also can make insulating resin coat at least one side of this weld pad at least simultaneously; avoid taking place scolding tin projection (solder extrusion) phenomenon, avoid causing the adjacent electronic elements problem of short-circuit.
Embodiment 2
See also Fig. 5, it is electronic carrier board embodiment 2 floor map of the present invention.
The electronic carrier board of the embodiment of the invention 2 and the foregoing description 1 are roughly the same; main difference is that the protective layer 43 on this electronic carrier board 41 is formed with opening 430 and 431 corresponding at least two 42 of weld pads that are provided with in pairs; this opening 430 and 431 is each other in the same way and expose outside 42 3 identical the first side walls 421 of these two weld pads; second sidewall 422 and the 3rd sidewall 423; this weld pad the first side wall 421 is directions that vertical this paired weld pad 42 is laid; second sidewall 422; the 3rd sidewall 423 is directions that parallel this paired weld pad 42 is laid, and the distance D of these the first side wall 421 these openings 430 of interval and 431 is at least greater than this second sidewall 422; the 3rd sidewall 423 is these openings 430 and 431 apart from d about 50 microns at interval.Should be more than or equal to 75 microns apart from d wherein, distance D be more than or equal to 125 microns; In addition, when being 50 microns as the bit errors ability, then being somebody's turn to do can be more than or equal to 50 micron apart from d, and this distance D then is more than or equal to 100 microns.
So, even if off normals (as 75 microns of off normals left) take place in opening 430 and 431, promptly described in above-mentioned embodiment 1, still can make electronic component have identical weld pad connects and puts area (wetting areas), and the insulating resin (50 microns of average grain diameters) that can make coated electric components is fully distributed in electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause, also can make insulating resin coat two sides of this weld pad at least simultaneously, avoid taking place scolding tin projection (solder extrusion) phenomenon, avoid causing the adjacent electronic elements problem of short-circuit.
Simultaneously; on this paired weld pad, connect when putting electronic component when follow-up; this is not located at the protective layer opening 431 of electronic component below; just not to be positioned at the distance of the protective layer opening 431 of 42 of two paired weld pads apart from its weld pad the first side wall 421; be under 75 microns the condition in bit errors; also can be more than or equal to 75 microns (being can be under 50 microns the condition in addition) more than or equal to 50 microns in bit errors; so; even if opening 430; 431 off normal takes place; still can make electronic component have identical weld pad connects and puts area (wetting areas); and the insulating resin (50 microns of average grain diameters) that can make coated electric components is fully distributed in this electronic component below and this opening; gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause; also can make insulating resin coat two sides of this weld pad at least simultaneously; avoid taking place scolding tin projection (solder extrusion) phenomenon, avoid causing the adjacent electronic elements problem of short-circuit.
Embodiment 3
See also Fig. 6 A, it is electronic carrier board embodiment 3 floor map of the present invention.
The electronic carrier board of the embodiment of the invention 3 and the foregoing description 1 are roughly the same; main difference is that the protective layer 43 on this electronic carrier board 41 is formed with opening 430 and 431 corresponding at least two 42 of weld pads that are provided with in pairs; this opening 430 and 431 is to manifest the identical the first side wall 421 of this two weld pads 42 each other in the same way and fully; second sidewall 422; the 3rd sidewall 423 and the 4th sidewall 424; wherein this first; the 4th sidewall 421; the 424th, the direction that vertical this paired weld pad 42 is laid; second; the 3rd sidewall 422; the 423rd, the direction that parallel this paired weld pad 42 is laid; and this first side wall 421 at interval these openings 430 and 431 distance D at least greater than this second; the 3rd sidewall 422,423 is these openings 430 and 431 apart from d about 50 microns at interval.Wherein should be apart from d be more than or equal to 75 microns, distance D is more than or equal to 125 microns, these openings 430 and 431 distance are more than or equal to 75 microns to the 4th sidewall 424 at interval in addition; In addition, when being 50 microns, should be can be then apart from d more than or equal to 50 microns as the bit errors ability, this distance D then is more than or equal to 100 microns.
So, even if off normal takes place in this opening 430 and 431,75 microns of skews to the right shown in Fig. 6 B, still can keep this weld pad 42 existing exposed area sizes, provide electronic component the wetting areas identical, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause with former design, also make insulating resin coat this weld pad side fully, avoid taking place scolding tin projection phenomenon.
Simultaneously; on this paired weld pad, connect when putting electronic component when follow-up; this is not located at the protective layer opening 431 of electronic component below; just not to be positioned at the distance of the protective layer opening 431 of 42 of two paired weld pads apart from its weld pad the first side wall 421; be under 75 microns the condition in bit errors; still can be more than or equal to 75 microns (being can be under 50 microns the condition in addition) more than or equal to 50 microns in bit errors; so; even if opening 430; 431 off normal takes place; still can keep this weld pad 42 existing exposed area sizes; provide electronic component the wetting areas identical with former design; the insulating resin of coated electric components is fully distributed in this electronic component below and this opening; gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause; also can make insulating resin coat this weld pad side fully, avoid taking place scolding tin projection phenomenon.
Embodiment 4
See also Fig. 7 A to Fig. 7 C, it is electronic carrier board embodiment 4 floor map of the present invention.
The electronic carrier board of the embodiment of the invention 4 and the foregoing description 3 are roughly the same; the conducting wire 420 that main difference is to be used for being connected with this weld pad 42 is except can being laid in these weld pad 42 left and right sides sides; also can place this weld pad 42 top, below, on/below or corner etc. locate; can cooperate the actual track arrangement but not exceed with this diagram; and non-ly expose outside weld pad four sidewalls with the protective layer opening and exceed, also can correspondence be applied among each embodiment.
Other sees also Fig. 8 A and Fig. 8 B, it is plane and a generalized section of using the assembling structure of electronic carrier board formation of the present invention, it comprises: an electronic carrier board 41, this electronic carrier board 41 can be the electronic carrier board in the various embodiments described above, this accompanying drawing is that the electronic carrier board that discloses with Fig. 6 is that example explains, but non-as limit; Electronic component 44 connects and puts and be electrically connected to this weld pad 42; Insulating resin 46 coats this electronic component 44, and can be fully distributed in these electronic component 44 belows and this opening 430 and 431, even can coat this weld pad 42 side surfaces.Wherein this electronic carrier board 41 is substrate, circuit board or printed circuit board (PCB) etc., and this protective layer 43 is welding resisting layers, and this electronic component 44 is passive devices.
This electronic component 44 be can saturating one for example the electric conducting material 45 of tin cream connect and put on the weld pad 42 that exposes outside this protective layer opening 430 and 431, carry out the reflow operation then, make this electronic component 44 be soldered on this weld pad 42 and form electrical connection by tin cream.
So, even if processing procedure precision and the skew of error effect generation protective layer aperture position when making this protective layer opening 430 and 431 upper and lower, left and right be offset 75 microns, still can not cause and expose the change thereupon simultaneously of weld pad 42 sizes.In addition; in the present embodiment since this protective layer opening be four sidewalls that expose outside this weld pad simultaneously; can in subsequent job, make insulating resin 46 envelope this weld pad 42 sides fully; avoiding existing connects passive device when putting on substrate by tin cream; the fusion tin cream gap between this weld pad surface and welding resisting layer of may flowing through; again along gap counterdiffusion mutually, contact between substrate and welding resisting layer; thereby scolding tin projection (solder extrusion) phenomenon takes place, avoid causing problems such as adjacent passive device is short-circuited.
Embodiment 5
See also Fig. 9, it is electronic carrier board embodiment 5 floor map of the present invention.
As shown in the figure, electronic carrier board 41 of the present invention comprises: a main body 411; At least two weld pads 42 that are located at these main body 411 surfaces in pairs, and these weld pad 42 sizes are identical; An and protective layer 43 that is used to cover these main body 411 surfaces; this protective layer 43 is formed with opening 430 and 431 corresponding to these weld pad 42 positions; this opening 430 and 431 is each other in the same way and expose outside the identical the first side wall 421 of this two weld pads 42, this first side wall 421 be vertically should paired weld pad 42 layings direction.
This weld pad the first side wall 421 can be more than or equal to 125 microns apart from the distance D of this opening 430 and 431; When being 50 microns as the bit errors ability, then this distance D then is more than or equal to 100 microns.
So; forming protective layer (welding resisting layer) opening 430 and at 431 o'clock; because of considering processing procedure precision and error; because this opening 430 and 431 is to be located at these two paired weld pad 42 places in the same way; even if therefore off normal takes place in it; still can avoid paired weld pad 42 to expose outside the area difference of opening 430 and 431, avoid follow-up on this weld pad 42 then during electronic component, because of the imbalance of wetted area causes the phenomenon of setting up a monument.
In addition, as this opening left during 75 microns of off normals, make this weld pad the first side wall 421 change to 50 microns (or more than) apart from the distance D of this opening 430, the insulating resin (50 microns of average grain diameters) of coated electric components is fully distributed in this electronic component below and this opening 430, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Simultaneously; on this paired weld pad, connect when putting electronic component when follow-up; this is not located at the protective layer opening 431 of electronic component below; just not to be positioned at the distance of the protective layer opening 431 of 42 of two paired weld pads apart from its weld pad the first side wall 421; be under 75 microns the condition in bit errors; still can be more than or equal to 75 microns (being can be under 50 microns the condition in addition) more than or equal to 50 microns in bit errors; so; even if opening 430; 431 off normal takes place; still can avoid paired weld pad 42 to expose outside opening 430; 431 area difference; make follow-up on this weld pad 42 then during electronic component, because of the imbalance of wetted area causes the phenomenon of setting up a monument.
Embodiment 6
See also Figure 10, it is to be electronic carrier board embodiment 6 floor map of the present invention.
The electronic carrier board of the embodiment of the invention 6 and the foregoing description 1 are roughly the same; make protective layer opening 430 and 431 each other in the same way; and expose outside two identical sidewalls of weld pad 42; main difference is that this protective layer opening 430 and 431 is the first side wall 421 and the 4th sidewalls 424 that expose outside weld pad 42; this the first side wall 421 and the 4th sidewall 424 are directions that vertical this paired weld pad 42 is laid; and this first side wall 421 is these openings 430 and 431 distance D at interval, at least greater than the 4th sidewall 424 these openings 430 and 431 apart from d about 50 microns at interval.Should be more than or equal to 75 microns apart from d wherein, distance D be more than or equal to 125 microns; In addition, when being 50 microns as the bit errors ability, then being somebody's turn to do can be more than or equal to 50 micron apart from d, and this distance D then is more than or equal to 100 microns.
So, even if off normals (no matter left, to the right or upwards, off normal) downwards take place in this opening 430 and 431, still can keep this weld pad 42 existing exposed area sizes, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Simultaneously; on this paired weld pad, connect when putting electronic component when follow-up; this is not located at the protective layer opening 431 of electronic component below; just not to be positioned at the distance of the protective layer opening 431 of 42 of two paired weld pads apart from its weld pad the first side wall 421; be under 75 microns the condition in bit errors; still can be more than or equal to 75 microns (being can be under 50 microns the condition in addition) more than or equal to 50 microns in bit errors; so; even if opening 430; 431 off normal takes place; still can keep this weld pad 42 existing exposed area sizes; make electronic component have identical wetting areas with former design; the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Embodiment 7
See also Figure 11, it is electronic carrier board embodiment 7 floor map of the present invention.
Can be simultaneously in the embodiment of the invention 7 in conjunction with the arrangement design of protective layer opening opposite soldering pads among the foregoing description 3 and the embodiment 6.
As shown in the figure; the planar dimension of two paired weld pads 42 can differ from one another on this electronic carrier board 41; and this protective layer opening 430 and 431 is each other in the same way; wherein this opening 430 is the first side wall 421, second sidewall 422, the 3rd sidewall 423 and the 4th sidewalls 424 that comprehensively expose outside weld pad 42, and this opening 431 is the first side wall and the 4th sidewalls that expose outside weld pad 42 relatively.Wherein this first side wall 421 at interval these openings 430 and 431 distance D at least greater than this second sidewall 422, the 3rd sidewall 423 and the 4th sidewall 424 these openings 430 and 431 about 50 microns at interval apart from d.Should be more than or equal to 75 microns apart from d wherein, distance D be more than or equal to 125 microns; In addition, when being 50 microns as the bit errors ability, then being somebody's turn to do can be more than or equal to 50 micron apart from d, and this distance D then is more than or equal to 100 microns.
So, even if off normals (no matter left, to the right or upwards, off normal) downwards take place in this opening 430 and 431, still can keep this weld pad 42 existing exposed area sizes, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Simultaneously; on this paired weld pad, connect when putting electronic component when follow-up; this is not located at the protective layer opening 431 of electronic component below; just not to be positioned at the distance of the protective layer opening 431 of 42 of two paired weld pads apart from its weld pad the first side wall 421; be under 75 microns the condition in bit errors; still can be more than or equal to 75 microns (being can be under 50 microns the condition in addition) more than or equal to 50 microns in bit errors; so; even if opening 430; 431 off normal takes place; still can keep this weld pad 42 existing exposed area sizes; make electronic component have identical wetting areas with former design; the insulating resin branch of coated electric components is distributed in this electronic component below and this opening with filling, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Therefore; make the protective layer that covers the electronic carrier board surface in the electronic carrier board of the present invention; at at least two weld pad places formation openings in the same way that dispose in pairs; expose outside these two weld pads sidewall in the same way; so forming protective layer (welding resisting layer) when opening is provided with; consider processing procedure precision and error; because this opening is to be located at this paired weld pad place in the same way; even if therefore off normal takes place; can avoid exposing outside the pad area difference of opening; make follow-up on this weld pad then during electronic component, the phenomenon of setting up a monument that can avoid the imbalance of wetted area (wetting area) to cause.
Simultaneously, this protective layer opening can expose outside the first side wall of vertical this paired weld pad cloth set direction, and the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.This protective layer opening can expose outside at least two first and second identical sidewalls of these two weld pads in addition; also or expose outside at least three first, second, third identical sidewalls of these two weld pads; this weld pad the first side wall is the direction that vertical this paired weld pad is laid; second (the 3rd) sidewall is the direction that parallel this paired weld pad is laid, and this first side wall at interval the distance of this opening at least greater than 50 microns of the distances of this this opening of second (the 3rd) sidewall spacers.So, even if opening generation off normal, not only still can keep identical weld pad exposed area, the insulating resin (50 microns of average grain diameters) of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause, also can make insulating resin coat at least one side of this weld pad at least simultaneously, avoid taking place scolding tin projection (solder extrusion) phenomenon, also can avoid causing the adjacent electronic elements problem of short-circuit.
In addition; this protective layer opening also can manifest the first, second, third and the 4th identical sidewall of these two weld pads each other in the same way and fully; the direction that this first, the 4th sidewall vertically should paired weld pad laying wherein; the direction that this paired weld pad of second, third parallel sidewalls is laid, and this first side wall at interval the distance of this opening at least greater than 50 microns of the distances of this second, third this opening of sidewall spacers.So, even if this opening generation off normal, still can keep the existing exposed area of this weld pad, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause still can make insulating resin coat this weld pad side fully, avoid taking place scolding tin projection phenomenon.
In addition; this protective layer opening can only expose outside the first side wall of weld pad among the present invention; the direction that vertical this paired weld pad of this first side wall is laid; so, when forming the protective layer opening, consider processing procedure precision and error; because this opening is to be located at this two paired weld pad places in the same way; therefore even if off normal takes place, still can avoid paired weld pad to expose outside the area difference of opening, avoid follow-up on this weld pad then during electronic component the imbalance because of wetted area cause the phenomenon of setting up a monument.
Moreover; this protective layer opening can expose outside the first and the 4th sidewall of weld pad among the present invention; this the first and the 4th sidewall is the direction that vertical this paired weld pad is laid, and the distance of this this opening of the first side wall interval is at least greater than about 50 microns of the distance of the 4th this opening of sidewall spacers.So, even if this opening generation off normal, still can keep the existing exposed area size of this weld pad, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is fully distributed in this electronic component below and this opening, gas explosion and the electrical bridge joint problem of avoiding the generation of gas hole to cause.
Simultaneously; one among the present invention in this protective layer opening exposes outside wherein the first, second, third and the 4th sidewall of a weld pad comprehensively; relatively another opening is the first and the 4th sidewall that exposes outside another weld pad, and this first side wall at interval the distance of this opening at least greater than this second, third and about 50 microns of the distance of the 4th this opening of sidewall spacers.So, even if this opening generation off normal, still can keep the existing exposed area size of this weld pad, make electronic component have identical wetting areas with former design, the insulating resin of coated electric components is distributed in this electronic component below and this opening fully, gas explosion of avoiding the gas hole to produce causing and electrical bridge joint problem.
Claims (44)
1. an electronic carrier board is characterized in that, this electronic carrier board comprises:
One main body;
At least two weld pads of being located at this body surfaces in pairs; And
One is used to cover the protective layer of this body surfaces; this protective layer is formed with opening corresponding to this bond pad locations; this opening is each other in the same way and expose outside at least two first and second identical sidewalls of this two weld pads; this weld pad the first side wall is the direction that vertical this paired weld pad is laid; second sidewall is the direction that parallel this paired weld pad is laid, and the first side wall of at least one weld pad at interval the distance of this opening at least greater than 50 microns of the distances of its this opening of second sidewall spacers.
2. electronic carrier board as claimed in claim 1 is characterized in that, this electronic carrier board is in the Chip Packaging base plate for packaging, circuit board or the printed circuit board (PCB) that use.
3. electronic carrier board as claimed in claim 1 is characterized in that, the main body of this electronic carrier board is the insulating barrier that insulating barrier or intermediate depot have line layer.
4. electronic carrier board as claimed in claim 1; it is characterized in that; can be coated with tin cream on this weld pad, electronic component can be electrically connected to this weld pad by this tin cream, and the first side wall distance of the protective layer extended distance weld pad of this electronic component below is at least greater than 50 microns of second sidewall distances.
5. electronic carrier board as claimed in claim 4 is characterized in that this electronic component is a passive device, makes insulating resin coat this passive device, and can be fully distributed in this passive device below and this opening.
6. electronic carrier board as claimed in claim 1 is characterized in that, the first side wall of this weld pad is more than or equal to 125 microns apart from this opening, and this second sidewall is more than or equal to 75 microns apart from this opening.
7. electronic carrier board as claimed in claim 6 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 75 microns apart from this weld pad the first side wall distance.
8. electronic carrier board as claimed in claim 1 is characterized in that, the first side wall of this weld pad is more than or equal to 100 microns apart from this opening, and this second sidewall is more than or equal to 50 microns apart from this opening.
9. electronic carrier board as claimed in claim 8 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 50 microns apart from this weld pad the first side wall distance.
10. electronic carrier board as claimed in claim 1, it is characterized in that, this opening also can expose outside three first, second and third identical sidewalls of these two weld pads, this weld pad the first side wall is the direction that vertical this paired weld pad is laid, second and third sidewall is the direction that parallel this paired weld pad is laid, and this first side wall at interval the distance of this opening at least greater than 50 microns of the distances of this second and third this opening of sidewall spacers.
11. an electronic carrier board is characterized in that, this electronic carrier board comprises:
One main body;
At least two weld pads of being located at this body surfaces in pairs; And
One is used to cover the protective layer of this body surfaces; this protective layer is formed with opening corresponding to this bond pad locations; this opening is to manifest the first, second, third and the 4th identical sidewall of these two weld pads each other in the same way and fully; wherein this first, the 4th sidewall is the direction that vertical this paired weld pad is laid; second, third sidewall is the direction that parallel this paired weld pad is laid, and the first side wall of at least one this weld pad at interval the distance of this opening at least greater than 50 microns of the distances of its second, third this opening of sidewall spacers.
12. electronic carrier board as claimed in claim 11 is characterized in that, this electronic carrier board is in the Chip Packaging base plate for packaging, circuit board or the printed circuit board (PCB) that use.
13. electronic carrier board as claimed in claim 11 is characterized in that, the main body of this electronic carrier board is the insulating barrier that insulating barrier or intermediate depot have line layer.
14. electronic carrier board as claimed in claim 11; it is characterized in that; can be coated with tin cream on this weld pad, electronic component borrows this tin cream to be electrically connected to this weld pad, and the first side wall distance of the protective layer extended distance weld pad of this electronic component below is at least greater than 50 microns of second sidewall distances.
15. electronic carrier board as claimed in claim 14 is characterized in that, this electronic component is a passive device, coats this passive device for insulating resin, and may be fully distributed in this passive device below and this opening.
16. electronic carrier board as claimed in claim 11 is characterized in that, the first side wall of this weld pad is more than or equal to 125 microns apart from this opening, this second, third and the 4th sidewall be more than or equal to 75 microns apart from this opening.
17. electronic carrier board as claimed in claim 16 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 75 microns apart from this weld pad the first side wall distance.
18. electronic carrier board as claimed in claim 11 is characterized in that, the first side wall of this weld pad is more than or equal to 100 microns apart from this opening, and this second sidewall is more than or equal to 50 microns apart from this opening.
19. electronic carrier board as claimed in claim 18 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 50 microns apart from this weld pad the first side wall distance.
20. electronic carrier board as claimed in claim 11 is characterized in that, this electronic carrier board also comprises the conducting wire that is located at this body surface, wherein this conducting wire be provided in a side of this weld pad left side, right side, top, below, on/in below or the corner one.
21. an electronic carrier board is characterized in that, this electronic carrier board comprises:
One main body;
At least two weld pads of being located at this body surfaces in pairs; And
One is used to cover the protective layer of this body surfaces, and this protective layer is formed with opening corresponding to this bond pad locations, and this opening is each other in the same way and expose outside this two the first side walls that weld pad is identical, this first side wall be vertically should paired weld pad laying direction.
22. electronic carrier board as claimed in claim 21 is characterized in that, this electronic carrier board is base plate for packaging, circuit board or the printed circuit board (PCB) that Chip Packaging is used.
23. electronic carrier board as claimed in claim 21 is characterized in that, the main body of this electronic carrier board is the insulating barrier that insulating barrier or intermediate depot have line layer.
24. electronic carrier board as claimed in claim 21 is characterized in that, can be coated with tin cream on this weld pad, electronic component borrows this tin cream to be electrically connected to this weld pad.
25. electronic carrier board as claimed in claim 24 is characterized in that, this electronic component is a passive device, coats this passive device for insulating resin, and can be fully distributed in this passive device below and this opening.
26. electronic carrier board as claimed in claim 21 is characterized in that, the first side wall of this weld pad is more than or equal to 125 microns apart from this opening.
27. electronic carrier board as claimed in claim 26 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 75 microns apart from this weld pad the first side wall distance.
28. electronic carrier board as claimed in claim 21 is characterized in that, the first side wall of this weld pad is more than or equal to 100 microns apart from this opening.
29. electronic carrier board as claimed in claim 28 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 50 microns apart from this weld pad the first side wall distance.
30. an electronic carrier board is characterized in that, this electronic carrier board comprises:
One main body;
At least two weld pads that are located at this body surfaces in pairs; And
One is used to cover the protective layer of this body surfaces; this protective layer is formed with opening corresponding to this bond pad locations; this opening is to manifest the first and the 4th identical sidewall of these two weld pads each other in the same way and fully; wherein this first and the 4th sidewall is the direction of that it(?) vertically should paired weld pad lay, and the distance of this opening of the first side wall of at least one this weld pad interval is at least greater than 50 microns of the distances of its this opening of the 4th sidewall spacers.
31. electronic carrier board as claimed in claim 30 is characterized in that, this electronic carrier board is in the Chip Packaging base plate for packaging, circuit board or the printed circuit board (PCB) that use.
32. electronic carrier board as claimed in claim 30 is characterized in that, the main body of this electronic carrier board is the insulating barrier that insulating barrier or intermediate depot have line layer.
33. electronic carrier board as claimed in claim 30; it is characterized in that; can be coated with tin cream on this weld pad, electronic component borrows this tin cream to be electrically connected to this weld pad, and the first side wall distance of the protective layer extended distance weld pad of this electronic component below is at least greater than 50 microns of second sidewall distances.
34. electronic carrier board as claimed in claim 33 is characterized in that, this electronic component is a passive device, coats this passive device for insulating resin, and can be fully distributed in this passive device below and this opening.
35. electronic carrier board as claimed in claim 30 is characterized in that, the first side wall of this weld pad is more than or equal to 125 microns apart from this opening, and the 4th sidewall is more than or equal to 75 microns apart from this opening.
36. electronic carrier board as claimed in claim 35 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 75 microns apart from this weld pad the first side wall distance.
37. electronic carrier board as claimed in claim 30 is characterized in that, the first side wall of this weld pad is more than or equal to 100 microns apart from this opening, and the 4th sidewall is more than or equal to 50 microns apart from this opening.
38. electronic carrier board as claimed in claim 37 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 50 microns apart from this weld pad the first side wall distance.
39. electronic carrier board as claimed in claim 30; it is characterized in that; one of them of this paired weld pad also comprises and exposes outside its second and third sidewall in this protective layer opening; this second and third sidewall is the direction that parallel this paired weld pad is laid, and the first side wall of this weld pad at interval the distance of this opening at least greater than 50 microns of the distances of its second, third this opening of sidewall spacers.
40. electronic carrier board as claimed in claim 39 is characterized in that, the first side wall of this weld pad is more than or equal to 125 microns apart from this opening, and this second and third sidewall is more than or equal to 75 microns apart from this opening.
41. electronic carrier board as claimed in claim 40 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 75 microns apart from this weld pad the first side wall distance.
42. electronic carrier board as claimed in claim 39 is characterized in that, the first side wall of this weld pad is more than or equal to 100 microns apart from this opening, and this second, third sidewall is more than or equal to 50 microns apart from this opening.
43. electronic carrier board as claimed in claim 42 is characterized in that, can put electronic component for connecing on this paired weld pad, and the corresponding protective layer opening of not being located at this electronic component below is more than or equal to 50 microns apart from this weld pad the first side wall distance.
44. electronic carrier board as claimed in claim 39 is characterized in that, the planar dimension each other of this paired weld pad is inequality.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100027264A CN101009968A (en) | 2006-01-25 | 2006-01-25 | Electronic carrier board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006100027264A CN101009968A (en) | 2006-01-25 | 2006-01-25 | Electronic carrier board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101009968A true CN101009968A (en) | 2007-08-01 |
Family
ID=38697998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006100027264A Pending CN101009968A (en) | 2006-01-25 | 2006-01-25 | Electronic carrier board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101009968A (en) |
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| CN102208387A (en) * | 2010-03-30 | 2011-10-05 | 曹用信 | Circuit board for being connected with ball grid array packaging assembly and method for forming bonding pad structure |
| CN102480849A (en) * | 2010-11-29 | 2012-05-30 | 宏恒胜电子科技（淮安）有限公司 | Circuit board and manufacturing method thereof |
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| CN102088822B (en) * | 2009-12-08 | 2014-12-17 | 三星半导体(中国)研究开发有限公司 | PCB (printed circuit board) substrate with welding spot self-protection function and manufacturing process of pad of PCB substrate |
| CN102208387A (en) * | 2010-03-30 | 2011-10-05 | 曹用信 | Circuit board for being connected with ball grid array packaging assembly and method for forming bonding pad structure |
| CN102208387B (en) * | 2010-03-30 | 2013-05-22 | 曹用信 | Circuit board for being connected with ball grid array packaging assembly and method for forming bonding pad structure |
| CN101916753A (en) * | 2010-08-04 | 2010-12-15 | 联发软体设计(深圳)有限公司 | Printed circuit board used for multi-column quadrature flat pin-free package chip |
| CN102480849A (en) * | 2010-11-29 | 2012-05-30 | 宏恒胜电子科技（淮安）有限公司 | Circuit board and manufacturing method thereof |
| CN102480849B (en) * | 2010-11-29 | 2014-09-24 | 宏恒胜电子科技（淮安）有限公司 | Circuit board and manufacturing method thereof |
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| CN103582283B (en) * | 2012-07-27 | 2016-08-10 | 富葵精密组件(深圳)有限公司 | Flexible PCB and preparation method thereof |
| CN105376934A (en) * | 2014-09-02 | 2016-03-02 | 富葵精密组件(深圳)有限公司 | Circuit board and manufacturing method of the circuit board |
| CN105376934B (en) * | 2014-09-02 | 2018-03-09 | 鹏鼎控股(深圳)股份有限公司 | The manufacture method of circuit board and circuit board |
| CN106992205A (en) * | 2017-04-27 | 2017-07-28 | 京东方科技集团股份有限公司 | A kind of organic EL display panel and display of organic electroluminescence |
| WO2019024351A1 (en) * | 2017-07-31 | 2019-02-07 | 郑州云海信息技术有限公司 | Pcb board design method for avoiding surface element tombstoning, and packaging method and pcb board |
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