CN101009140A - Signal generator and its shift register - Google Patents

Signal generator and its shift register Download PDF

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Publication number
CN101009140A
CN101009140A CN 200610006077 CN200610006077A CN101009140A CN 101009140 A CN101009140 A CN 101009140A CN 200610006077 CN200610006077 CN 200610006077 CN 200610006077 A CN200610006077 A CN 200610006077A CN 101009140 A CN101009140 A CN 101009140A
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China
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signal
switch module
conducting
shift register
control
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CN100578673C (en
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曾名骏
郭鸿儒
黄建翔
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QIJING PHOTOELECTRIC CO Ltd
Chi Mei Optoelectronics Corp
Chi Mei EL Corp
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QIJING PHOTOELECTRIC CO Ltd
Chi Mei Optoelectronics Corp
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Abstract

This invention relates to one signal generator, which comprises multiple displacement memory device with each composed of first switch, second and third switch parts and control part, wherein, the first part comprises first input end to receive input signal and first control end to receive first clock signal and first output end; the second part comprises second input end coupled to first voltage and second control end and output end to receive first control signals; the third part comprises third input end to receive second clock signals and third control end coupled to first output end and third output end to output signals.

Description

Signal generator and shift register thereof
Technical field
The present invention relates to a kind of signal generator and shift register thereof (Shift Register), and be particularly related to the single P-type mos of a kind of use (P-type Metal OxideSemiconductor, PMOS) transistor or transistorized signal generator of N type metal oxide semiconductor (NMOS) and shift register thereof.
Background technology
Tradition application of cold temperature polysilicon (Low Temperature Poly Silicon, LTPS) to be implemented in the shift register of glass substrate be complementary shift register to technology, often comprised in its circuit N type thin film transistor (TFT) (Thin Film Transistor, TFT) and P type thin film transistor (TFT).
Figure 1A is the circuit structure diagram of existing multistage complementary shift register.Please refer to Figure 1A, first order shift register 100 has two PMOS transistor MP1 and MP2 and two nmos pass transistor MN1 and MN2.The grid of the grid of transistor MP2 and transistor MN2 couples, and receiving inputted signal input.The drain electrode of the source electrode of transistor MP2 and transistor MN2 couples, and exports the first signal S1.The first signal S1 is via first phase inverter, 102 back outputs, the first output signal out-1.The grid receive clock signal XCK of transistor MP1, and the grid of transistor MN1 receive clock signal CK then.Clock signal C K and XCK are inversion signals.In addition, the source electrode of transistor MP1 couples the drain electrode of transistor MP2, and the drain electrode of transistor MN1 couples the source electrode of transistor MN2.
Similarly, second level shift register 110 comprises PMOS transistor MP3 and MP4 and nmos pass transistor MN3 and MN4.The grid of the grid of transistor MP4 and transistor MN4 couples, and receives the first signal S1.The drain electrode of the source electrode of transistor MP4 and transistor MN4 couples, and output secondary signal S2.Secondary signal S2 is via second phase inverter, 112 back outputs, the second output signal out-2.The grid receive clock signal CK of transistor MP3, and the grid of transistor MN1 receive clock signal XCK then.In addition, the source electrode of transistor MP3 couples the drain electrode of transistor MP4, and the drain electrode of transistor MN3 couples transistor MN4 source electrode.
Figure 1B illustrates input signal input, the output signal out-1 of shift register 100 among Figure 1A and 110 and the sequential chart of out-2.Shown in Figure 1B, output signal out-2 phase place is that the phase place of output signal out-1 is to right translation half period T/2.Because it is higher that complementary shift register 100 and 110 has comprised the required photomask cost of N-TFT and P-TFT technology, do not meet the technical target that reduces cost of LTPS.And the overlapping that the output signal out-1 after the phase shift, out-2 will produce half period partly, if be applied to the drive signal of actual panel, must utilize to reach and (AND) be separated with logical circuit.Therefore more increase the cost of manufacture of shift register.
In addition, Fig. 1 C is the multi-stage shift register circuit structure diagram of one-level wherein in the existing flat-panel screens.Shift register 120 comprises PMOS transistor MP1, MP2, MP3, MP4 and MP5.The drain electrode receiving inputted signal INPUT of transistor MP1, and the grid receive clock signal XCK of transistor MP1.The source electrode of transistor MP1 then couples the grid of transistor MP5.The drain electrode of transistor MP2 couples the source electrode of transistor MP3 and the grid of transistor MP4, and the grid of transistor MP2 couples the drain electrode of transistor MP4.The grid of transistor MP3 receives the output signal OUTPUT2 of next stage shift register (not being shown among the figure).The drain electrode of transistor MP4 couples the grid of transistor MP2 and the source electrode of transistor MP5, and output signal OUTPUT.The drain electrode of transistor MP5 is receive clock signal CK then.
Among Fig. 1 C transistor MP2 and MP4 formed differential be to have a feedback mechanism to (Cross Couple), shown in Fig. 1 D.Node B is represented the drain electrode end of transistor MP2.The drain current of transistor MP2 is by the Node B grid of transistor MP4 of flowing through, and flow to the OUTPUT output terminal.The grid of transistor MP2 and the transistor MP4 drain current of OUTPUT output terminal is flowed through, and flow to Node B.Therefore, the level of signal OUTPUT can determine the action of transistor NP2, and the level of decision Node B, and the level of Node B also can influence the action of transistor MP4 and the level of signal OUTPUT.
Please refer to Fig. 1 E, it illustrates signal INPUT, XCK, CK, OUTPUT and OUTPUT2 and the node A and the B voltage level V of shift register 120 among Fig. 1 C AAnd V BSequential chart.Under normal operation, above-mentioned feedback mechanism can arrive steady state (SS) in a short period of time, and the signal OUTPUT of the normal feedback of output, shown in the OUTPUT level of period T 3 inside solids of Fig. 1 E, by level low vertical uplift to level high.Yet, under certain conditions, for example be the threshold voltage of thin film transistor (TFT) (TFT) when too big, this feedback mechanism spends the long time could arrive steady state (SS) possibly.The signal OUTPUT of meeting this moment output abnormality feedback is shown in the OUTPUT level of dotted lines in the period T 3 of Fig. 1 E.The action that this abnormal signal output can influence whole display was lost efficacy, and reduced the yield rate of display.
Please refer to Fig. 2, it illustrates a kind of signal generator structure calcspar of correlation technique of the present invention.Signal generator 200 comprises the multi-stage shift register 210 of mutual serial connection.Fig. 2 only shows N level, (N+1) level and (N+2) level shift register 210 of serial connection.N level shift register 210 comprises PMOS transistor MP1n and MP2n, capacitance component Cn and voltage replacement (Reset) assembly 212.The drain electrode of transistor MP1n is receiving inputted signal INPUT, that is the output signal OUT_N-1 of (N-1) level shift register 210 (not being shown among the figure), and the grid receive clock signal XCK of transistor MP1n.The grid of transistor MP2n couples the source electrode of transistor MP1n, and capacitance component Cn is that cross-over connection is between the source electrode and grid of transistor MP2n.The drain electrode of transistor MP2n is then in order to output signal OUT_N, and the source electrode receive clock signal CK of transistor MP2n.Clock signal C K and XCK are inversion signal.
The voltage replacement assembly 212 of N level comprises PMOS transistor MP3n, MP4n and MP5n.The drain electrode of transistor MP3n connects the drain electrode of transistor MP2n, and the grid of transistor MP3n connects the drain electrode of transistor MP4n and transistor MP5n, the source electrode connection V of transistor MP3n DDThe grid of transistor MP4n connects the drain electrode of transistor MP3n, and the source electrode of transistor MP4n connects V DDThe drain electrode of transistor MP5n connects the drain electrode of transistor MP4n, and the source electrode of transistor MP5n connects GND.In addition, the grid of transistor MP5n then receives the output signal OUT_N+1 of (N+1) level shift register 210 as a kind of reset signal.
Similarly, (N+1) level shift register 210 comprises PMOS transistor MP1 (n+1) and MP2 (n+1), capacitance component C (n+1) and voltage replacement (Reset) assembly 212.The drain electrode of transistor MP1 (n+1) receives output signal OUT_N, and the grid receive clock signal CK of transistor MP1 (n+1).The grid of transistor MP2 (n+1) couples the source electrode of transistor MP1 (n+1), and capacitance component C (n+1) be cross-over connection in the source electrode of transistor MP2 (n+1) with and grid between.The drain electrode of transistor MP2 (n+1) is then in order to output signal OUT_N+1, and the source electrode receive clock signal XCK of transistor MP2 (n+1).Two PMOS transistor gates of adjacent two-stage shift register 210 are to receive anti-phase clock signal in the signal generator 200.
In addition, the voltage replacement assembly 212 of (N+1) level comprises PMOS transistor MP3 (n+1), MP4 (n+1) and MP5 (n+1).Each transistorized annexation is identical with the voltage replacement assembly 212 of N level, does not just give unnecessary details at this.The grid of transistor MP5 (n+1) is to receive the output signal OUT_N+2 of (N+2) level shift register 210 as a kind of reset signal.
Please refer to Fig. 3, it illustrates the time sequential routine figure of N level among Fig. 2 and (N+1) level shift register 210.In the first sequential period T 1, input signal INPUT is the first incoming level (V IL), for example be the GND current potential, clock signal XCK is the first clock level (V CL), for example be the GND current potential, and clock signal C K is second clock level (V CH), for example be the VDD current potential.So transistor MP1n is a conducting state.Current potential V XBe pulled to a relative low level (V IL+ V Th), wherein, voltage V ThThreshold voltage (Threshold Voltage) for transistor MP1n.At this moment, the grid potential (V of transistor MP2n IL+ V Th) be lower than source potential V CHTherefore, also conducting of transistor MP2n, and signal OUT_N is a desirable high level V CH, and feed back to the grid of transistor MP4n in the voltage replacement assembly 212 of N level, make not conducting of transistor MP4n.
Because this moment, output signal OUT_N+1 was high level V CHSo not conducting of transistor MP5n.This moment voltage V YLevel be last cycle status, no matter but V YWhy level all can not influence the output result of signal OUT_N.That is when period 1 T1, signal OUT_N is output high level V CH
Then, in second round T2, input signal INPUT is the second incoming level (V IH).Clock signal C K is second clock level (V CH), and clock signal XCK is the first clock level (V CL).Because the grid potential V of transistor MP1n IHBe higher than source potential V CLSo, not conducting of transistor MP1n.The source potential of transistor MP2n is by V CHReduce to V CLTherefore, node V XCurrent potential can be depressurized to ((V because of the effect of decompression capacitor Cn IL+ V Th)-(V CH-V CL)) level, this level is still less than the source potential V of MP2n CLThis moment, transistor MP2n still was a conducting state, and signal OUT_N is a desirable low level V CL, and feed back to the grid of transistor MP4n, making transistor MP4n is conducting state, this moment node V YVoltage is VDD.Because the grid potential VDD of transistor MP3n equals source voltage VDD, so not conducting of transistor MP3n.
At this moment, signal OUT_N is with low level V CLThe drain electrode of transistor MP1 (n+1) in input (N+1) the level shift register 210, and clock signal C K is low level V CL, each assemblies action of level shift register 210 this moment (N+1) is as the N level shift register 210 of period 1 T1, transistor MP1 (n+1) and all conductings of MP2 (n+1), and making output signal OUT_N+1 is high level V CHSignal OUT_N+1 feeds back to the grid of transistor MP5n in the N voltage replacement assembly 212, makes not conducting of transistor MP5n.
In the 3rd sequential period T 3, input signal INPUT is continuously high level V IHClock signal C K is high level V CH, and clock signal XCK is low level V CLAt this moment, the transistor MP1n of N level shift register 210 is a conducting state, makes node V XCurrent potential is high level V IH, so not conducting of transistor MP2n.In (N+1) level shift register 210, as the N level shift register 210 of T2 second round, capacitance component C (n+1) hypotensive effect makes transistor MP2 (n+1) conducting and the low level V of signal OUT_N+1 output signal XCK CLSignal OUT_N+1 feeds back to the grid of transistor MP5n in the voltage replacement assembly 212 of N level, and making transistor MP5n is conducting state.At this moment, node V YVoltage be a relative low level (GND+Vth), make transistor MP3n conducting.Therefore, signal OUT_N exports a desirable high level (=V CH), and feed back to the grid of transistor MP4n, make that transistor MP4n is a not on-state.
As shown in Figure 3, the output signal OUT_N phase place of N level shift register 210 be with respect to input signal INPUT phase place to right translation half period T/2, and (N+1) level shift register 210 output signal OUT_N+1 phase place be with respect to output signal OUT_N phase place to right translation half period T/2.
Yet above-mentioned shift register 210 also exists shown in Fig. 1 E, because the threshold voltage of the thin film transistor (TFT) unusual OUTPUT signal that institute may cause when too big, thereby the yield rate of reduction display was lost efficacy in the action that influences whole display.
Please refer to Fig. 4, it illustrates the another kind of signal generator structure calcspar of correlation technique of the present invention.Signal generator 400 comprises the multi-stage shift register 410 of mutual serial connection.Fig. 4 only shows N level, (N+1) level and (N+2) level shift register 410 of serial connection.N level shift register 410 comprises the voltage replacement assembly 412 of PMOS transistor MP1n and transistor MP2n, capacitance component Cn and N level.The drain electrode of transistor MP1n is receiving inputted signal INPUT, and the grid receive clock signal XCK of transistor MP1n.The annexation of transistor MP1n, MP2n and capacitance component Cn is identical with the N level shift register 210 of Fig. 2, does not give unnecessary details at this.The drain electrode of transistor MP2n is output signal OUT_N, and the source electrode receive clock signal CK of transistor MP2n.
In addition, the voltage replacement assembly 412 of N level comprises PMOS transistor MP3n, MP4n and MP5n.The annexation of transistor MP3n, MP4n and the MP5n also N step voltage replacement assembly 212 with Fig. 2 is identical, this also no longer stating more.Yet the grid of transistor MP5n is that receive clock signal XCK is as a kind of reset signal among Fig. 4.
Similarly, (N+1) level shift register 410 comprises PMOS transistor MP1 (n+1) and MP2 (n+1), capacitance component C (n+1) and (N+1) step voltage replacement assembly 412.The drain electrode of transistor MP1 (n+1) receives output signal OUT_N, and the grid receive clock signal CK of transistor MP1 (n+1).The source electrode receive clock signal XCK of transistor MP2 (n+1).The annexation of transistor MP1 (n+1) and MP2 (n+1) also is same as (N+1) level shift register 210 of Fig. 2.And two PMOS transistor gates of adjacent two-stage shift register 410 are to receive anti-phase clock signal in the signal generator 400.
In addition, the voltage replacement assembly 412 of (N+1) level comprises PMOS transistor MP3 (n+1), MP4 (n+1) and MP5 (n+1).Each transistorized annexation is identical with the voltage replacement assembly 212 of N level among Fig. 2, does not just give unnecessary details at this.The grid of transistor MP5 (n+1) is that receive clock signal CK is as a kind of reset signal.
Please refer to Fig. 5, it illustrates the time sequential routine figure of N level among Fig. 4 and (N+1) level shift register 410.As a same correlation technique, in the first sequential period T 1, input signal INPUT is the first incoming level V IL, clock signal XCK is the first clock level V CL, and clock signal C K is second clock level V CHTransistor MP1n is a conducting state.V XCurrent potential is pulled to a relative low level (V IL+ Vth).At this moment, also conducting of transistor MP2n, and signal OUT_N exports a desirable high level V CH, and feed back to the grid of transistor MP4n in the voltage replacement assembly 412 of N level, make not conducting of transistor MP4n.
Because the clock signal XCK of input transistors MP5n grid is low level V CL, so transistor MP5n conducting, make V YCurrent potential is a relative low level (GND+Vth), and exports the grid of transistor MP3n to, makes transistor MP3n conducting, and signal OUT_N output high level (VDD).
Then, in second round T2, input signal INPUT is the second incoming level V IHClock signal C K is the first clock level V CL, and clock signal XCK is second clock level V CHTransistor MP1n is a not on-state.The source potential of transistor MP2n is by V CHReduce to V CLTherefore, V XCurrent potential can be because of the effect of decompression capacitor Cn by step-down (Boost) to level ((V IL+ V Th)-(V CH-V CL)), this level is still less than the source potential V of MP2n CLSo transistor MP2n still is a conducting state, and signal OUT_N is output one desirable low level V CL, and feed back to the grid of transistor MP4n, making transistor MP4n is conducting state, and node V YVoltage is VDD (high level).Because the grid potential (=V of transistor MP3n YVoltage=VDD) equals source voltage VDD so not conducting of transistor MP3n.Because transistor MP5n grid potential=XCK=V CH, so not conducting of transistor MP5n.
At this moment, the drain electrode of transistor MP1 (n+1) in low level signal OUT_N input (N+1) the level shift register 410, and clock signal C K is low level V CL, as the N level shift register 410 of period 1 T1, transistor MP1 (n+1) and all conductings of MP2 (n+1), making output signal OUT_N+1 is high level V CH
In the 3rd sequential period T 3, input signal INPUT is continuously the second incoming level V IHClock signal C K is high level V CH, and clock signal XCK is low level V CLAt this moment, transistor MP1n is a conducting state, makes V XCurrent potential is high level V IH, so not conducting of transistor MP2n.In (N+1) level shift register 410, as the N level shift register 410 of T2 second round, capacitance component C (n+1) hypotensive effect makes transistor MP2 (n+1) conducting and the low level V of signal OUT_N+1 output signal XCK CLThis moment transistor MP5n grid potential to equal XCK be a low level V CL, so transistor MP5n is conducting state, and V YCurrent potential is a relative low level (GND+Vth), and exports the grid of transistor MP3n to, makes transistor MP3n conducting.Therefore, signal OUT_N exports a desirable high level (VDD), and feeds back to the grid of transistor MP4n, makes that transistor MP4n is a not on-state.
As shown in Figure 5, the output signal OUT_N phase place of N level shift register 410 be with respect to input signal INPUT phase place to right translation half period T/2, and (N+1) level shift register 410 output signal OUT_N+1 phase place be with respect to output signal OUT_N phase place to right translation half period T/2.
Yet above-mentioned shift register 210 also exists shown in Fig. 1 E, because the threshold voltage of the thin film transistor (TFT) unusual OUTPUT signal that institute may cause when too big, thereby the yield rate of reduction display was lost efficacy in the action that influences whole display.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of signal generator and shift register thereof exactly, utilize single PMOS transistor or nmos pass transistor to make switch module, can reduce the employed number of optical mask of overall system process, effectively reduce manufacturing cost, and can improve panel output capacity (throughput) and yield rate simultaneously.
According to purpose of the present invention, a kind of shift register is proposed, also export an output signal according to this in order to receiving inputted signal.Shift register comprises first switch module, second switch assembly, the 3rd switch module and controlled switch assembly.First switch module comprises first input end, first control end and first output terminal.First input end is in order to receiving inputted signal, and first control end is in order to receive first clock signal.The second switch assembly comprises second input end, second control end and second output terminal.Second input end is to be coupled to first voltage, and second control end is in order to receive first control signal.The 3rd switch module comprises the 3rd input end, the 3rd control end and the 3rd output terminal.The 3rd input end is in order to receive the second clock signal, and wherein the second clock signal is the inversion signal of first clock signal.The 3rd control end is to be coupled to first output terminal, and the 3rd output terminal is in order to output signal output.The controlled switch assembly comprises controlled input end, the first switch control end, second switch control end and controlled output terminal.Controlled input end is to be coupled to second voltage, and the first switch control end is in order to receive second control signal.The second switch control end is coupled to second output terminal, and controlled output terminal is to be coupled to the 3rd output terminal.
In cycle, the input signal and first clock signal are to have first level in first sequential, the first switch module conducting, and export input signal to the 3rd control end; Simultaneously, the second clock signal has second level, makes the also conducting of the 3rd switch module, and the second clock signal is output as output signal.
In cycle, input signal, first clock signal and first control signal have second level in second sequential, make win switch module and the not conducting of second switch assembly; Simultaneously, second control signal is controlled the not conducting of controlled switch assembly, and the second clock signal has first level, and the 3rd switch module conducting, and the second clock signal is output as output signal.
In cycle, input signal has second level in the 3rd sequential, and first clock signal has first level, makes the switch module conducting of winning, and exports input signal to the 3rd control end; Simultaneously, first control signal has first level, makes the conducting of second switch assembly, and exports first voltage to the second switch control end; Second control signal and first voltage are the conductings of control controlled switch assembly, and second voltage is output as output signal level.
According to purpose of the present invention, a kind of signal generator is proposed, comprise multi-stage shift register, each is in order to receive an input signal and to export an output signal according to this.Shift registers at different levels comprise first switch module, second switch assembly, the 3rd switch module and controlled switch assembly.First switch module comprises first input end, first control end and first output terminal.First input end is in order to receiving inputted signal, and first control end is in order to receive first clock signal, and wherein first clock signal of this grade shift register is the inversion signal of first clock signal of next stage shift register.The second switch assembly comprises second input end, second control end and second output terminal.Second input end is to be coupled to first voltage, and second control end is in order to receive first control signal.The 3rd switch module comprises the 3rd input end, the 3rd control end and the 3rd output terminal.The 3rd input end is in order to receive the second clock signal, and wherein the second clock signal is the inversion signal of first clock signal.The 3rd control end is to be coupled to first output terminal, and the 3rd output terminal is in order to output signal output.The controlled switch assembly comprises controlled input end, the first switch control end, second switch control end and controlled output terminal.Controlled input end is coupled to second voltage, and the first switch control end is in order to receive second control signal.The second switch control end is coupled to second output terminal, and controlled output terminal is to be coupled to the 3rd output terminal.
In cycle, the input signal and first clock signal are to have first level in this grade shift register in first sequential, the first switch module conducting, and export input signal to the 3rd control end; Simultaneously, the second clock signal has second level, makes the also conducting of the 3rd switch module, and the second clock signal is output as output signal.
In cycle, input signal, first clock signal and first control signal have second level in this grade shift register in second sequential, make win switch module and the not conducting of second switch assembly; Simultaneously, second control signal is controlled the not conducting of controlled switch assembly, and the second clock signal has first level, and the 3rd switch module conducting, and the second clock signal is output as output signal.
In cycle, input signal has second level in this grade shift register in the 3rd sequential, and first clock signal has first level, makes the switch module conducting of winning, and exports input signal to the 3rd control end; Simultaneously, first control signal has first level, makes the conducting of second switch assembly, and exports first voltage to the second switch control end; Second control signal and first voltage are the conductings of control controlled switch assembly, and second voltage is output as output signal level.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, three preferred embodiments cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A is the circuit structure diagram of existing multistage complementary shift register.
Figure 1B be illustrate shift register among Figure 1A and input signal input, output signal out-1 and the sequential chart of out-2.
Fig. 1 C is the multi-stage shift register circuit structure diagram of one-level wherein in the existing flat-panel screens.
Fig. 1 D illustrates the feedback mechanism synoptic diagram that shift register had among Fig. 1 C.
Fig. 1 E, it illustrates signal INPUT, XCK, CK, OUTPUT and OUTPUT2 and the node A and the B voltage level V of shift register 120 among Fig. 1 C AAnd V BSequential chart.
Fig. 2 illustrates a kind of signal generator structure calcspar of correlation technique of the present invention.
Fig. 3 illustrates the time sequential routine figure of N level among Fig. 2 and (N+1) level shift register.
Fig. 4 illustrates the another kind of signal generator structure calcspar of correlation technique of the present invention.
Fig. 5 illustrates the time sequential routine figure of N level among Fig. 4 and (N+1) level shift register.
Fig. 6 A illustrates a kind of signal generator circuit structure diagram according to first embodiment of the invention.
Fig. 6 B illustrates the time sequential routine figure of N level shift register among Fig. 6 A.
Fig. 6 C illustrates wherein circuit structure diagram that transistor uses the output signal of next stage shift register to control of N level shift register among Fig. 6 A.
Fig. 6 D illustrates the circuit structure diagram of N level shift register use transistor switch stabilizing circuit among Fig. 6 A.
Fig. 7 A illustrates a kind of signal generator circuit structure diagram according to second embodiment of the invention.
Fig. 7 B illustrates the time sequential routine figure of N level shift register among Fig. 7 A.
Fig. 7 C illustrates wherein circuit structure diagram that transistor uses the output signal of next stage shift register to control of N level shift register among Fig. 7 A.
Fig. 7 D illustrates the circuit structure diagram of N level shift register use transistor switch stabilizing circuit among Fig. 7 A.
Fig. 8 A illustrates a kind of signal generator circuit structure diagram according to third embodiment of the invention.
Fig. 8 B illustrates the time sequential routine figure of N level shift register among Fig. 8 A.
Fig. 8 C illustrates wherein circuit structure diagram that transistor uses the output signal of next stage shift register to control of N level shift register among Fig. 8 A.
Fig. 8 D illustrates the circuit structure diagram of N level shift register use transistor switch stabilizing circuit among Fig. 8 A.
The reference numeral explanation
100,210,410,610,710,810: shift register
102,112: phase inverter
200,400,600,700,800: signal generator
212,412: voltage replacement assembly
Embodiment
Next, just illustrate with three preferred embodiments how the present invention uses the PMOS transistor of single kenel to make signal generator and shift register thereof.
First embodiment:
Please refer to Fig. 6 A, it illustrates a kind of signal generator structure calcspar according to first embodiment of the invention.Signal generator 600 for example is scanner driver or the data driver that is applied to flat-panel screens, and it comprises the multi-stage shift register 610 of mutual serial connection.Fig. 6 A only shows N level, (N+1) level and (N+2) level shift register 610 of serial connection.
N level shift register 610 comprises PMOS transistor MP1n, MP2n, MP3n, MP4n and MP5n.The drain electrode of transistor MP1n is receiving inputted signal INPUT (being OUTPUT_N-1), and the grid of transistor MP1n is to receive first clock signal C 1.The drain electrode of transistor MP3n is to be coupled to the first voltage VSS, and the grid of transistor MP3n is to receive the first control signal C1.The source electrode of transistor MP5n is to receive second clock signal C2, and wherein second clock signal C2 is the inversion signal of first clock signal C 1.The grid of transistor MP5n is the source electrode that couples transistor MP1n, and the drain electrode of transistor MP5n is output N level output signal OUTPUT_N.
The source electrode of transistor MP2n is to be coupled to the second voltage VDD, and the grid of transistor MP2n is to receive the second clock signal, and the drain electrode of transistor MP2n is the source electrode that is coupled to transistor MP3n.The source electrode of transistor MP4n is to be coupled to the second voltage VDD, and the grid of transistor MP4n is the drain electrode that is coupled to transistor MP2n, and the drain electrode of transistor MP4n is the drain electrode that is coupled to transistor MP5n.
In addition, (N+1) level shift register 610 also comprises PMOS transistor MP1 (n+1), MP2 (n+1), MP3 (n+1), MP4 (n+1) and MP5 (n+1).Its signal and assembly annexation and N level shift register 610 are roughly the same, unique difference is in the grid of transistor MP1 (n+1) in (N+1) level shift register 610 and the grid of transistor MP3 (n+1) is to receive second clock signal C2 (anti-phase with the signal C1 of N level), and the source electrode of transistor MP5 (n+1) then receives first clock signal C 1 (anti-phase with the signal C2 of N level).
Please refer to Fig. 6 B, it illustrates the time sequential routine figure of N level shift register 610 among Fig. 6 A.In the first sequential period T 1, the input signal INPUT and first clock signal C 1 are to have the first level low in the N level shift register 610, for example are GND.Because the source potential of transistor MP1n is level high in the last cycle, the grid potential of transistor MP1n (low) is lower than source potential (high), therefore transistor MP1n conducting makes the grid potential (being the current potential Va of node A) of transistor MP5 reduce to level low+Vth.Similarly, the source potential of transistor MP3n is level high in the last cycle, and the grid potential of transistor MP3n (low) also is lower than source potential (high), makes that transistor MP3n conducting, the current potential Vb of Node B are the first voltage VSS.Simultaneously, the grid potential of transistor MP4n is VSS also, is lower than source potential VDD, makes transistor MP4n conducting, and the level of output signal OUTPUT_N is VDD.On the other hand, second clock signal C2 has the second level high, for example is VDD, and the source potential VDD of transistor MP5 is higher than grid potential (low+Vth), makes also conducting of transistor MP5n, and output signal OUTPUT_N has level high (VDD).Second clock signal C2 (high) makes not conducting of transistor MP2n simultaneously.
Then, in the second sequential period T 2, the input signal INPUT and first clock signal C 1 all have the second level high in the N level shift register 610.Because the grid potential (high) of transistor MP1n is higher than source potential (low+Vth), make not conducting of transistor MP1n, the grid potential of transistor MP3n (high) is higher than source potential (VSS), so also not conducting of transistor MP3n.Simultaneously, second clock signal C2 has the first level low, makes transistor MP2n conducting, and the current potential Vb of Node B is VDD, and the grid potential of transistor MP4n is VDD also, makes not conducting of transistor MP4n.At this moment, because the stray capacitance Cgs among the transistor MP5n between source electrode and the grid, make when second clock signal C2 drops to level low by level high, the current potential Va of node A also can be pulled down to low+Vth-Δ V (Δ V=high-low), cause transistor MP5n conducting, and output signal OUTPUT has the level low of clock signal C 2.
Then, in the 3rd sequential period T 3, input signal INPUT has the second level high in the N level shift register 610, and first clock signal C 1 has the first level low, make transistor MP1n conducting, the grid potential of transistor MP5n is high, that is current potential Va is high.Simultaneously, also conducting of transistor MP3n, current potential Vb is VSS, and the grid potential of transistor MP4n is VSS.Therefore, also conducting of transistor MP4n, output signal OUTPUT_N has the VDD level.At this moment, second clock signal C2 has level high, and current potential Va is high, makes not conducting of transistor MP5n.
Compared to prior art, because the switch motion of transistor MP2n does not need feedback mechanism, but directly control by clock signal C 2, therefore, can remove existing uncertain factor and cause feedback mechanism can't arrive the shortcoming of balance at short notice.
According to first embodiment, though it is that example explains that the present invention receives first clock signal C 1 with the grid of transistor MP3n, the grid of transistor MP3n also can be the output signal OUTPUT_N+1 that receives (N+1) level shift register 610 in the right N level shift register 610 of the present invention, shown in Fig. 6 C.Because output signal OUTPUT_N+1 has level high, high, low respectively in period T 1, T2 and T3, with level low, high, the low of first clock signal C 1, its difference only is the first sequential period T 1.In period T 1, even the grid of transistor MP3n changes the level high of input OUTPUT_N+1, and causes transistor MP3n and the neither conducting of MP4n, yet because transistor MP5n conducting, therefore, output signal OUTPUT still has the level high of clock signal C 2.Therefore, do not break away from technical scope of the present invention.
In addition, shown in Fig. 6 D, above-mentioned N level shift register 610 can also comprise transistor MP6n.The source electrode of transistor MP6n is coupled to the second voltage VDD, and the grid of transistor MP6n can for example be the output signal OUTPUT_N+2 of (N+2) level in order to receive the output signal of any next stage shift register 610.The drain electrode of transistor MP6n then is coupled to the drain electrode of transistor MP5.Because in period T 1, T2 and T3, the level of signal OUTPUT_N+2 is all high.Therefore, transistor MP6n is a not on-state, does not influence the level size of output signal OUTPUT_N.Yet, can increase the stability of output signal OUTPUT_N.
Second embodiment
Please refer to Fig. 7 A, it illustrates a kind of signal generator structure calcspar according to second embodiment of the invention.Signal generator 700 for example is scanner driver or the data driver that is applied to flat-panel screens, and it comprises the multi-stage shift register 710 of mutual serial connection.Fig. 7 A only shows N level, (N+1) level and (N+2) level shift register 710 of serial connection.
N level shift register 710 comprises PMOS transistor MP1n, MP2n, MP3n, MP4n and MP5n.The drain electrode of transistor MP1n is receiving inputted signal INPUT (being OUTPUT_N-1), and the grid of transistor MP1n is to receive first clock signal C 1.The drain electrode of transistor MP3n is to be coupled to the first voltage VSS, and the grid of transistor MP3n is to receive the first control signal C1.The source electrode of transistor MP5n is to receive second clock signal C2, and wherein second clock signal C2 is the inversion signal of first clock signal C 1.The grid of transistor MP5n is the source electrode that couples transistor MP1n, and the drain electrode of transistor MP5n is output N level output signal OUTPUT_N.
The source electrode of transistor MP4n is to be coupled to the second voltage VDD, and the grid of transistor MP4n is the source electrode that is coupled to transistor MP3n.The source electrode of transistor MP2n is the drain electrode that is coupled to transistor MP4n, and the grid of transistor MP2n is to receive first clock signal C 1, and the drain electrode of transistor MP2n is the drain electrode that is coupled to transistor MP5n.
In addition, (N+1) level shift register 710 also comprises PMOS transistor MP1 (n+1), MP2 (n+1), MP3 (n+1), MP4 (n+1) and MP5 (n+1).Its signal and assembly annexation and N level shift register 710 are roughly the same, unique difference is in the grid of transistor MP1 (n+1) in (N+1) level shift register 710 and the grid of transistor MP3 (n+1) is to receive second clock signal C2 (anti-phase with the signal C1 of N level), and the source electrode of transistor MP5 (n+1) then receives first clock signal C 1 (anti-phase with the signal C2 of N level).
Please refer to Fig. 7 B, it illustrates the time sequential routine figure of N level shift register 710 among Fig. 7 A.In the first sequential period T 1, the input signal INPUT and first clock signal C 1 are to have level low in the N level shift register 710, for example are GND.Because the source potential of transistor MP1n is level high in the last cycle, so transistor MP1n conducting, makes the grid potential (being current potential Va) of transistor MP5 reduce to level low+Vth.Similarly, the source potential of transistor MP3n is level high in the last cycle, makes that transistor MP3n conducting, current potential Vb are the first voltage VSS.And the grid potential of transistor MP4n (Vb) is VSS, is lower than source potential VDD, makes transistor MP4n conducting.Simultaneously, (=C1 level=low), be lower than source potential (VDD) makes transistor MP2n conducting to the grid potential of transistor MP2n, so the level of output signal OUTPUT_N is voltage VDD.On the other hand, second clock signal C2 has the second level high, for example is VDD, and the source potential VDD of transistor MP5 is higher than grid potential (low+Vth), makes also conducting of transistor MP5n, and output signal OUTPUT_N has level high (VDD).
Then, in the second sequential period T 2, the input signal INPUT and first clock signal C 1 all have level high in the N level shift register 710.Because the grid potential (high) of transistor MP1n is higher than source potential (low+Vth), make not conducting of transistor MP1n, the grid potential of transistor MP3n (high) is higher than source potential (VSS), so also not conducting of transistor MP3n.At this moment, transistor MP4n causes the conducting of transistor MP2n simultaneously owing to lack also not conducting of grid current.At this moment, because the stray capacitance Cgs among the transistor MP5n between source electrode and the grid, make when second clock signal C2 drops to level low by level high, current potential Va also can be pulled down to low+Vth-Δ V (Δ V=high-low), cause transistor MP5n conducting, and output signal OUTPUT has the level low of clock signal C 2.
Then, in the 3rd sequential period T 3, input signal INPUT has level high in the N level shift register 710, and first clock signal C 1 has level low, make transistor MP1n conducting, the grid potential of transistor MP5n is high, that is current potential Va is high.Simultaneously, also conducting of transistor MP3n, current potential Vb is VSS, and the grid potential of transistor MP4n is VSS.Therefore, also conducting of transistor MP4n.At this moment, the grid potential of transistor MP2n is the level low of signal C1, and therefore, also conducting of transistor MP2n makes output signal OUTPUT_N have the VDD level.And second clock signal C2 has level high, and current potential Va is high, makes not conducting of transistor MP5n.
Compared to prior art, because the switch motion of transistor MP2n does not need feedback mechanism, but directly control by clock signal C 1, therefore, can remove existing uncertain factor and cause feedback mechanism can't arrive the shortcoming of balance at short notice.
According to second embodiment, though it is that example explains that the present invention receives first clock signal C 1 with the grid of transistor MP3n, the grid of transistor MP3n also can be the output signal OUTPUT_N+1 that receives (N+1) level shift register 710 in the right N level shift register 710 of the present invention, shown in Fig. 7 C.Because output signal OUTPUT_N+1 has level high, high, low respectively in period T 1, T2 and T3, with level low, high, the low of first clock signal C 1, its difference only is the first sequential period T 1.In period T 1, even the grid of transistor MP3n changes the level high of input OUTPUT_N+1, and cause transistor MP3n, MP4n and the neither conducting of MP2, yet because transistor MP1 conducting, make transistor MP5n conducting, therefore, output signal OUTPUT still has the level high of clock signal C 2.Therefore, do not break away from technical scope of the present invention.
In addition, shown in Fig. 7 D, above-mentioned N level shift register 710 can also comprise transistor MP6n.The source electrode of transistor MP6n is coupled to the second voltage VDD, and the grid of transistor MP6n can for example be the output signal OUTPUT_N+2 of (N+2) level in order to receive the output signal of any next stage shift register 610.The drain electrode of transistor MP6n then is coupled to the drain electrode of transistor MP2.Because in period T 1, T2 and T3, the level of signal OUTPUT_N+2 is all high.Therefore, transistor MP6n is a not on-state, does not influence the level size of output signal OUTPUT_N.Yet, can increase the stability of output signal OUTPUT_N.
The 3rd embodiment
Please refer to Fig. 8 A, it illustrates a kind of signal generator structure calcspar according to third embodiment of the invention.Signal generator 800 for example is scanner driver or the data driver that is applied to flat-panel screens, and it comprises the multi-stage shift register 810 of mutual serial connection.Fig. 8 A only shows N level, (N+1) level and (N+2) level shift register 810 of serial connection.
N level shift register 810 comprises PMOS transistor MP1n, MP2n, MP3n, MP4n and MP5n.The drain electrode of transistor MP1n is receiving inputted signal INPUT (being OUTPUT_N-1), and the grid of transistor MP1n is to receive first clock signal C 1.The drain electrode of transistor MP3n is to be coupled to the first voltage VSS, and the grid of transistor MP3n is to receive the first control signal C1.The source electrode of transistor MP5n is to receive second clock signal C2, and wherein second clock signal C2 is the inversion signal of first clock signal C 1.The grid of transistor MP5n is the source electrode that couples transistor MP1n, and the drain electrode of transistor MP5n is output N level output signal OUTPUT_N.
The source electrode of transistor MP4n is to be coupled to the second voltage VDD, and the grid of transistor MP4n is to receive first clock signal C 1.The source electrode of transistor MP2n is the drain electrode that is coupled to transistor MP4n, and the grid of transistor MP2n is the source electrode that is coupled to transistor MP3n, and the drain electrode of transistor MP2n is the drain electrode that is coupled to transistor MP5n.
In addition, (N+1) level shift register 810 also comprises PMOS transistor MP1 (n+1), MP2 (n+1), MP3 (n+1), MP4 (n+1) and MP5 (n+1).Its signal and assembly annexation and N level shift register 810 are roughly the same, unique difference is in the grid of transistor MP1 (n+1) in (N+1) level shift register 810 and the grid of transistor MP3 (n+1) is to receive second clock signal C2 (anti-phase with the signal C1 of N level), and the source electrode of transistor MP5 (n+1) then receives first clock signal C 1 (anti-phase with the signal C2 of N level).
Please refer to Fig. 8 B, it illustrates the time sequential routine figure of N level shift register 810 among Fig. 8 A.In the first sequential period T 1, the input signal INPUT and first clock signal C 1 are to have level low in the N level shift register 810, for example are GND.Because the source potential of transistor MP1n is level high in the last cycle, so transistor MP1n conducting, makes the grid potential (being current potential Va) of transistor MP5n reduce to level low+Vth.Similarly, the source potential of transistor MP3n is level high in the last cycle, makes that transistor MP3n conducting, current potential Vb are the first voltage VSS.The grid potential of transistor MP4n i.e. the level low of first clock signal C 1, is lower than source potential VDD, so transistor MP4n conducting.Simultaneously, the grid potential of transistor MP2n (Vb) is VSS, also is lower than source potential VDD, causes transistor MP2n conducting.Therefore, the level of output signal OUTPUT_N is voltage VDD.On the other hand, second clock signal C2 has the second level high, for example is VDD, and the source potential VDD of transistor MP5 is higher than grid potential (low+Vth), makes also conducting of transistor MP5n, and output signal OUTPUT_N has level high (VDD).
Then, in the second sequential period T 2, the input signal INPUT and first clock signal C 1 all have level high in the N level shift register 810.Because the grid potential (high) of transistor MP1n is higher than source potential (low+Vth), make not conducting of transistor MP1n, the grid potential of transistor MP3n (high) is higher than source potential (VSS), therefore also not conducting of transistor MP3n, and and then cause transistor MP4n and the neither conducting of MP2n.At this moment, because the stray capacitance Cgs among the transistor MP5n between source electrode and the grid, make when second clock signal C2 drops to level low by level high, current potential Va also can be pulled down to low+Vth-Δ V (Δ V=high-low), cause transistor MP5n conducting, and output signal OUTPUT has the level low of clock signal C 2.
Then, in the 3rd sequential period T 3, input signal INPUT has level high in the N level shift register 810, and first clock signal C 1 has level low, make transistor MP1n conducting, and the grid potential of transistor MP5n is high, that is current potential Va is high.Simultaneously, also conducting of transistor MP3n, current potential Vb is VSS, and the grid potential of transistor MP2n is VSS.Because the grid potential of transistor MP4 i.e. the level low of first clock signal C 1, transistor MP4n conducting, and make that the source potential of transistor MP2n is VDD.Simultaneously, the grid potential of transistor MP2n is VSS, therefore, and also conducting of transistor MP2n.At this moment, output signal OUTPUT_N has the VDD level.And second clock signal C2 has level high, and current potential Va is high, makes not conducting of transistor MP5n.
Compared to prior art, because the switch motion of transistor MP4n does not need feedback mechanism, but directly control by clock signal C 1, therefore, can remove existing uncertain factor and cause feedback mechanism can't arrive the shortcoming of balance at short notice.
According to the 3rd embodiment, though it is that example explains that the present invention receives first clock signal C 1 with the grid of transistor MP3n, the grid of transistor MP3n also can be the output signal OUTPUT_N+1 that receives (N+1) level shift register 810 in the right N level shift register 810 of the present invention, shown in Fig. 8 C.Because output signal OUTPUT_N+1 has level high, high, low respectively in period T 1, T2 and T3, with level low, high, the low of first clock signal C 1, its difference only is the first sequential period T 1.In period T 1, even the grid of transistor MP3n changes the level high of input OUTPUT_N+1, and cause transistor MP3n, MP2n and the neither conducting of MP4n, yet because transistor MP1n conducting, make transistor MP5n conducting, therefore, output signal OUTPUT still has the level high of clock signal C 2.Therefore, do not break away from technical scope of the present invention.
In addition, shown in Fig. 8 D, above-mentioned N level shift register 810 can also comprise transistor MP6n.The source electrode of transistor MP6n is coupled to the second voltage VDD, and the grid of transistor MP6n can for example be the output signal OUTPUT_N+2 of (N+2) level in order to receive the output signal of any next stage shift register 610.The drain electrode of transistor MP6n then is coupled to the drain electrode of transistor MP2.Because in period T 1, T2 and T3, the level of signal OUTPUT_N+2 is all high.Therefore, transistor MP6n is a not on-state, does not influence the level size of output signal OUTPUT_N.Yet, can increase the stability of output signal OUTPUT_N.
According to three above-mentioned embodiment, though the present invention receives second clock signal C2 with the grid of transistor MP2n in the N level shift register 610, the drain electrode of transistor MP2n couples the source electrode of transistor MP3n, the source electrode of transistor MP2n and MP4n couples the second voltage VDD, and the drain electrode that the drain electrode of transistor MP4n couples transistor MP5n is an example, perhaps couple the source electrode of transistor MP3n with the grid of transistor MP4n in the N level shift register 710, the source electrode of transistor MP4n couples voltage VDD, the grid of transistor MP2n receives first clock signal C 1, and the drain electrode that the drain electrode of transistor MP4n couples transistor MP5n is an example, perhaps the grid with transistor MP4n in the N level shift register 810 receives first clock signal C 1, the source electrode of transistor MP4n couples voltage VDD, the grid of transistor MP2n couples the source electrode of transistor MP3n, and the drain electrode that the drain electrode of transistor MP2n couples transistor MP5n is that example explains, right shift register of the present invention also can have other controlled switch assembly, be coupled between the drain electrode of voltage VDD and transistor MP5, and have reception first of the first switch control end or second clock signal, and has the source electrode that the second switch control end is coupled to transistor MP3.So long as in period T 1, T2 and T3, the controlled switch assembly is to be respectively conducting, not conducting and conducting state, all can reach the effect with the input signal phase shift.Therefore, do not break away from technical scope of the present invention.
In addition, according to above-mentioned three embodiment, be that example explains though the present invention has five PMOS transistors with shift register 610,710,810, right shift register of the present invention, can also be nmos pass transistor with five single kenels, or or even other switch module.So long as pass through the control of first and second clock signal, can reach effect with the input signal phase shift, also do not break away from technical scope of the present invention.
Moreover, be that example explains though the present invention has five PMOS transistors with shift register 610,710,810, right shift register of the present invention also can be to comprise first switch module, phase-shifts assembly and buck assembly.First switch module is the control of accepting first clock signal C 1, in order to the input of control input signals INPUT; The phase-shifts assembly is to be coupled to first switch module, and accepts the control of second clock signal C2, in order to input signal INPUT is carried out phase-shifts; And the buck assembly is to be coupled to the phase-shifts assembly, and accept first clock signal C 1 or the arbitrarily control of next stage shift register output signal, be used to the current potential that the phase-shifts assembly carries out input signal INPUT to draw high or downgrade after the phase-shifts output signal OUTPUT.So long as can be by the phase shift of phase-shifts assembly with input signal INPUT, and the current potential of output signal is drawn high or downgrades the level identical with input signal when the above-mentioned period T 3 by the buck assembly, can reach the accurate translation purpose in position, therefore also not break away from technical scope of the present invention.
The advantage of above-mentioned three disclosed signal generators of embodiment of the present invention and shift register thereof is to utilize LTPS PMOS or NMOS technology that shift-register circuit is implemented on the glass substrate.Because single PMOS or the employed photomask number of single NMOS technology are few than CMOS, except saving the photomask cost, can improve unit interval panel generation rate (Throughput) in addition, the while can solve prior art circuits signal transition delay and influence the problem that integrated circuit operates.
In sum; though the present invention discloses as above with three preferred embodiments; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims (60)

1. a shift register is also exported an output signal according to this in order to receive an input signal, and this shift register comprises:
One first switch module comprises:
One first input end is in order to receive this input signal;
One first control end is in order to receive one first clock signal; And
One first output terminal;
One second switch assembly comprises:
One second input end is to be coupled to one first voltage;
One second control end is in order to receive one first control signal; And
One second output terminal;
One the 3rd switch module comprises:
One the 3rd input end, in order to receive a second clock signal, this second clock signal inversion signal that is this first clock signal wherein;
One the 3rd control end is to be coupled to this first output terminal; And
One the 3rd output terminal is in order to export this output signal; And
One controlled switch assembly comprises:
One controlled input end is to be coupled to one second voltage;
One first switch control end is in order to receive one second control signal;
One second switch control end is coupled to this second output terminal; And
One controlled output terminal is to be coupled to the 3rd output terminal;
Wherein, in the cycle, this input signal and this first clock signal are to have one first level in one first sequential, this first switch module conducting, and export this input signal to the 3rd control end; Simultaneously, this second clock signal has one second level, makes the also conducting of the 3rd switch module, and this second clock signal is output as this output signal;
Wherein, in the cycle, this input signal, this first clock signal and this first control signal have this second level in one second sequential, make this first switch module and this not conducting of second switch assembly; Simultaneously, this second control signal is controlled this not conducting of controlled switch assembly, and this second clock signal has this first level, and the 3rd switch module conducting, and this second clock signal is output as this output signal;
Wherein, in the cycle, this input signal has this second level in one the 3rd sequential, and this first clock signal has this first level, makes this first switch module conducting, and exports this input signal to the 3rd control end; Simultaneously, this first control signal has this first level, makes this second switch assembly conducting, and exports this first voltage to this second switch control end; This second control signal and this first voltage are this controlled switch assembly conductings of control, and this second voltage is output as this output signal level.
2. shift register as claimed in claim 1, wherein, this controlled switch assembly more comprises:
One the 4th switch module comprises:
One four-input terminal is coupled to this second voltage;
One the 4th control end is in order to receive this second control signal; And
One the 4th output terminal is coupled to this second output terminal; And
One the 5th switch module comprises:
One the 5th input end is coupled to this second voltage;
One the 5th control end is coupled to the 4th output terminal; And
One the 5th output terminal is coupled to the 3rd output terminal.
3. shift register as claimed in claim 2, wherein, this first control signal is this first clock signal, and this second control signal is this second clock signal.
4. shift register as claimed in claim 3, wherein, in this first sequential cycle, this second control signal has this second level, make this not conducting of four switch modules, this first control signal has this first level simultaneously, makes this second switch assembly conducting, and export this first voltage to the 5th control end, make the 5th switch module conducting and export second voltage to the 3rd output terminal; In this second sequential cycle, this input signal, this first clock signal and this first control signal have this second level, make this first switch module and this not conducting of second switch assembly; This second control signal has this first level, makes the 4th switch module conducting, and exports this second voltage to the 5th control end, makes the 5th not conducting of switch module;
In the 3rd sequential in the cycle, this second control signal has this second level, make the 4th not conducting of switch module, and this first control signal has this first level, make this second switch assembly conducting, and export this first voltage to the 5th control end, control the 5th switch module conducting, and export this second voltage to the 3rd output terminal.
5. shift register as claimed in claim 2, wherein, this first control signal is the output signal that couples the next stage shift register of this shift register, and this second control signal is this second clock signal.
6. shift register as claimed in claim 5, wherein, in this first sequential cycle, this first control signal and this second control signal have this second level, make this second switch assembly, the 4th switch module and the neither conducting of this five switch module;
In this second sequential cycle, this input signal, this first clock signal and this first control signal all have this second level, make this first switch module and this not conducting of second switch assembly; This second control signal has this first level, makes the 4th switch module conducting, and exports this second voltage to the 5th control end, makes the 5th not conducting of switch module;
In the 3rd sequential in the cycle, this second control signal has this second level, make the 4th not conducting of switch module, and this first control signal has this first level, make this second switch assembly conducting, and export this first voltage to the 5th control end, control the 5th switch module conducting, and export this second voltage to the 3rd output terminal.
7. shift register as claimed in claim 2, wherein, this controlled switch assembly more comprises one the 6th switch module, and the 6th switch module comprises:
One the 6th input end is coupled to this second voltage;
One the 6th control end couples the output signal of any next stage shift register of this shift register in order to reception: and
One the 6th output terminal is coupled to the 3rd output terminal.
8. shift register as claimed in claim 2, wherein, this first switch module, this second switch assembly, the 3rd switch module, the 4th switch module and the 5th switch module are to be all the PMOS transistor.
9. shift register as claimed in claim 1, wherein, this controlled switch assembly more comprises:
One the 4th switch module comprises:
One four-input terminal is coupled to this second voltage;
One the 4th control end is coupled to this second output terminal; And
One the 4th output terminal; And
One the 5th switch module comprises:
One the 5th input end is coupled to the 4th output terminal;
One the 5th control end is in order to receive this second control signal; And
One the 5th output terminal is coupled to the 3rd output terminal.
10. shift register as claimed in claim 9, wherein, this first control signal is this first clock signal, and this second control signal is this first clock signal.
11. shift register as claimed in claim 10, wherein, in this first sequential cycle, this first control signal has this first level, makes this two switch modules conducting, and exports this first voltage to the 4th control end, control the 4th switch module conducting and export this second voltage to the 5th input end, this second control signal has this first level simultaneously, makes the 5th switch module conducting, and exports this second voltage to the 3rd output terminal;
In this second sequential cycle, this input signal, this first clock signal and this first control signal have this second level, make this first switch module and this not conducting of second switch assembly, and cause the 4th switch module and the neither conducting of the 5th switch module;
In the 3rd sequential in the cycle, this first control signal has this first level, makes this second switch assembly conducting, and exports this first voltage to the 4th control end, control the 4th switch module conducting, and export this second voltage to the 5th input end; This second control signal has this first level simultaneously, makes the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
12. shift register as claimed in claim 9, wherein, this first control signal is the output signal that couples the next stage shift register of this shift register, and this second control signal is this first clock signal.
13. shift register as claimed in claim 12, wherein, in this first sequential cycle, this first control signal has this second level, makes this not conducting of two switch modules, and causes the 4th switch module and the neither conducting of the 5th switch module;
In this second sequential cycle, this first control signal has this second level, makes this not conducting of second switch assembly, and causes the 4th switch module and the neither conducting of the 5th switch module;
In the 3rd sequential in the cycle, this first control signal has this first level, makes this second switch assembly conducting, and exports this first voltage to the 4th control end, control the 4th switch module conducting, and export this second voltage to the 5th input end; This second control signal has this first level simultaneously, makes the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
14. shift register as claimed in claim 9, wherein, this controlled switch assembly more comprises one the 6th switch module, and the 6th switch module comprises:
One the 6th input end is coupled to this second voltage;
One the 6th control end couples the output signal of any next stage shift register of this shift register in order to reception: and
One the 6th output terminal is coupled to the 4th output terminal.
15. shift register as claimed in claim 9, wherein, this first switch module, this second switch assembly, the 3rd switch module, the 4th switch module and the 5th switch module are to be all the PMOS transistor.
16. shift register as claimed in claim 1, wherein, this controlled switch assembly more comprises:
One the 4th switch module comprises:
One four-input terminal is coupled to this second voltage;
One the 4th control end is in order to receive this second control signal; And
One the 4th output terminal; And
One the 5th switch module comprises:
One the 5th input end is coupled to the 4th output terminal;
One the 5th control end is coupled to this second output terminal; And
One the 5th output terminal is coupled to the 3rd output terminal.
17. shift register as claimed in claim 16, wherein this first control signal is this first clock signal, and this second control signal is this first clock signal.
18. shift register as claimed in claim 17, wherein, in this first sequential cycle, this second control signal has this first level, makes the 4th switch module conducting, and exports this second voltage to the 5th input end; This first control signal has this first level simultaneously, makes this two switch modules conducting, and exports this first voltage to the 5th control end, controls the 5th switch module conducting and exports this second voltage to the 3rd output terminal;
In this second sequential cycle, this input signal, this first clock signal and this first control signal have this second level, make this first switch module and this not conducting of second switch assembly, and cause the 4th switch module and the neither conducting of the 5th switch module;
In cycle, this second control signal has this first level in the 3rd sequential, makes the 4th switch module conducting, and exports this second voltage to the 5th input end; This first control signal has this first level simultaneously, makes this second switch assembly conducting, and exports this first voltage to the 5th control end, controls the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
19. shift register as claimed in claim 16, wherein, this first control signal is the output signal that couples the next stage shift register of this shift register, and this second control signal is this first clock signal.
20. shift register as claimed in claim 19, wherein, in this first sequential cycle, this first control signal has this second level, makes this not conducting of two switch modules, and causes the 4th switch module and the neither conducting of the 5th switch module;
In this second sequential cycle, this first control signal has this second level, makes this not conducting of second switch assembly, and causes the 4th switch module and the neither conducting of the 5th switch module;
In cycle, this second control signal has this first level in the 3rd sequential, makes the 4th switch module conducting, and exports this second voltage to the 5th input end; This first control signal has this first level simultaneously, makes this second switch assembly conducting, and exports this first voltage to the 5th control end, controls the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
21. shift register as claimed in claim 16, wherein, this controlled switch assembly more comprises one the 6th switch module, and the 6th switch module comprises:
One the 6th input end is coupled to this second voltage;
One the 6th control end couples the output signal of any next stage shift register of this shift register in order to reception: and
One the 6th output terminal is coupled to the 4th output terminal.
22. shift register as claimed in claim 16, wherein, this first switch module, this second switch assembly, the 3rd switch module, the 4th switch module and the 5th switch module are to be all the PMOS transistor.
23. a signal generator comprises:
Multi-stage shift register, each is in order to receive an input signal and to export an output signal according to this, and shift registers at different levels comprise:
One first switch module comprises:
One first input end is in order to receive this input signal;
One first control end, in order to receive one first clock signal, the inversion signal of this first clock signal of this grade shift register this first clock signal that is the next stage shift register wherein; And
One first output terminal;
One second switch assembly comprises:
One second input end is to be coupled to one first voltage;
One second control end is in order to receive one first control signal; And
One second output terminal;
One the 3rd switch module comprises:
One the 3rd input end, in order to receive a second clock signal, this second clock signal inversion signal that is this first clock signal wherein;
One the 3rd control end is to be coupled to this first output terminal; And
One the 3rd output terminal is in order to export this output signal; And
One controlled switch assembly comprises:
One controlled input end is to be coupled to one second voltage;
One first switch control end is in order to receive one second control signal;
One second switch control end is coupled to this second output terminal; And
One controlled output terminal is to be coupled to the 3rd output terminal;
Wherein, in the cycle, this input signal and this first clock signal are to have one first level in this grade shift register in one first sequential, this first switch module conducting, and export this input signal to the 3rd control end; Simultaneously, this second clock signal has one second level, makes the also conducting of the 3rd switch module, and this second clock signal is output as this output signal;
Wherein, in the cycle, this input signal, this first clock signal and this first control signal have this second level in this grade shift register in one second sequential, make this first switch module and this not conducting of second switch assembly; Simultaneously, this second control signal is controlled this not conducting of controlled switch assembly, and this second clock signal has this first level, and the 3rd switch module conducting, and this second clock signal is output as this output signal;
Wherein, in the cycle, this input signal has this second level in this grade shift register in one the 3rd sequential, and this first clock signal has this first level, makes this first switch module conducting, and exports this input signal to the 3rd control end; Simultaneously, this first control signal has this first level, makes this second switch assembly conducting, and exports this first voltage to this second switch control end; This second control signal and this first voltage are this controlled switch assembly conductings of control, and this second voltage is output as this output signal level.
24. signal generator as claimed in claim 23, wherein, each these these controlled switch assembly more comprises:
One the 4th switch module comprises:
One four-input terminal is coupled to this second voltage;
One the 4th control end is in order to receive this second control signal; And
One the 4th output terminal is coupled to this second output terminal; And
One the 5th switch module comprises:
One the 5th input end is coupled to this second voltage;
One the 5th control end is coupled to the 4th output terminal; And
One the 5th output terminal is coupled to the 3rd output terminal.
25. signal generator as claimed in claim 24, wherein, this first control signal is this first clock signal in each these shift register, and this second control signal is this second clock signal.
26. signal generator as claimed in claim 25, wherein, in this first sequential cycle, this second control signal has this second level in this grade shift register, make this not conducting of four switch modules, this first control signal has this first level simultaneously, makes this second switch assembly conducting, and export this first voltage to the 5th control end, make the 5th switch module conducting and export second voltage to the 3rd output terminal;
In this second sequential cycle, this input signal, this first clock signal and this first control signal have this second level in this grade shift register, make this first switch module and this not conducting of second switch assembly; This second control signal has this first level, makes the 4th switch module conducting, and exports this second voltage to the 5th control end, makes the 5th not conducting of switch module;
In the 3rd sequential in the cycle, this second control signal has this second level in this grade shift register, make the 4th not conducting of switch module, and this first control signal has this first level, make this second switch assembly conducting, and export this first voltage to the 5th control end, control the 5th switch module conducting, and export this second voltage to the 3rd output terminal.
27. signal generator as claimed in claim 24, wherein, the output signal that this first control signal is the next stage shift register in each these shift register, and this second control signal is this second clock signal.
28. signal generator as claimed in claim 27, wherein, in this first sequential cycle, this first control signal and this second control signal have this second level in this grade shift register, make this second switch assembly, the 4th switch module and the neither conducting of this five switch module;
In this second sequential cycle, this input signal, this first clock signal and this first control signal all have this second level in this grade shift register, make this first switch module and this not conducting of second switch assembly; This second control signal has this first level, makes the 4th switch module conducting, and exports this second voltage to the 5th control end, makes the 5th not conducting of switch module;
In the 3rd sequential in the cycle, this second control signal has this second level in this grade shift register, make the 4th not conducting of switch module, and this first control signal has this first level, make this second switch assembly conducting, and export this first voltage to the 5th control end, control the 5th switch module conducting, and export this second voltage to the 3rd output terminal.
29. signal generator as claimed in claim 24, wherein, this controlled switch assembly of each these shift register more comprises one the 6th switch module, and the 6th switch module comprises:
One the 6th input end is coupled to this second voltage;
One the 6th control end, in order to receive this output signal of any next stage shift register: and
One the 6th output terminal is coupled to the 3rd output terminal.
30. signal generator as claimed in claim 24, wherein, this first switch module, this second switch assembly, the 3rd switch module, the 4th switch module and the 5th switch module are to be all the PMOS transistor.
31. signal generator as claimed in claim 23, wherein, this controlled switch assembly more comprises in each these shift register:
One the 4th switch module comprises:
One four-input terminal is coupled to this second voltage;
One the 4th control end is coupled to this second output terminal; And
One the 4th output terminal; And
One the 5th switch module comprises:
One the 5th input end is coupled to the 4th output terminal;
One the 5th control end is in order to receive this second control signal; And
One the 5th output terminal is coupled to the 3rd output terminal.
32. signal generator as claimed in claim 31, wherein, this first control signal is this first clock signal in each these shift register, and this second control signal is this first clock signal.
33. signal generator as claimed in claim 32, wherein, in this first sequential cycle, this first control signal has this first level in this grade shift register, make this two switch modules conducting, and export this first voltage to the 4th control end, control the 4th switch module conducting and export this second voltage to the 5th input end, this second control signal has this first level simultaneously, make the 5th switch module conducting, and export this second voltage to the 3rd output terminal;
In this second sequential cycle, this input signal, this first clock signal and this first control signal have this second level in this grade shift register, make this first switch module and this not conducting of second switch assembly, and cause the 4th switch module and the neither conducting of the 5th switch module;
In the 3rd sequential in the cycle, this first control signal has this first level in this grade shift register, makes this second switch assembly conducting, and exports this first voltage to the 4th control end, control the 4th switch module conducting, and export this second voltage to the 5th input end; This second control signal has this first level simultaneously, makes the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
34. signal generator as claimed in claim 31, wherein, this output signal that this first control signal is the next stage shift register in each these shift register, and this second control signal is this first clock signal.
35. signal generator as claimed in claim 34, wherein, in this first sequential cycle, this first control signal has this second level in this grade shift register, make this not conducting of two switch modules, and cause the 4th switch module and the neither conducting of the 5th switch module;
In this second sequential cycle, this first control signal has this second level in this grade shift register, makes this not conducting of second switch assembly, and causes the 4th switch module and the neither conducting of the 5th switch module;
In the 3rd sequential in the cycle, this first control signal has this first level in this grade shift register, makes this second switch assembly conducting, and exports this first voltage to the 4th control end, control the 4th switch module conducting, and export this second voltage to the 5th input end; This second control signal has this first level simultaneously, makes the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
36. signal generator as claimed in claim 31, wherein, this controlled switch assembly more comprises one the 6th switch module in each these shift register, and the 6th switch module comprises:
One the 6th input end is coupled to this second voltage;
One the 6th control end couples this output signal of any next stage shift register in order to reception: and
One the 6th output terminal is coupled to the 4th output terminal.
37. signal generator as claimed in claim 31, wherein, this first switch module, this second switch assembly, the 3rd switch module, the 4th switch module and the 5th switch module are to be all the PMOS transistor.
38. signal generator as claimed in claim 23, wherein, this controlled switch assembly more comprises in each these shift register:
One the 4th switch module comprises:
One four-input terminal is coupled to this second voltage;
One the 4th control end is in order to receive this second control signal; And
One the 4th output terminal; And
One the 5th switch module comprises:
One the 5th input end is coupled to the 4th output terminal;
One the 5th control end is coupled to this second output terminal; And
One the 5th output terminal is coupled to the 3rd output terminal.
39. signal generator as claimed in claim 38, wherein this first control signal is this first clock signal in each these shift register, and this second control signal is this first clock signal.
40. signal generator as claimed in claim 39, wherein, in this first sequential cycle, this second control signal has this first level in this grade shift register, makes the 4th switch module conducting, and exports this second voltage to the 5th input end; This first control signal has this first level simultaneously, makes this two switch modules conducting, and exports this first voltage to the 5th control end, controls the 5th switch module conducting and exports this second voltage to the 3rd output terminal;
In this second sequential cycle, this input signal, this first clock signal and this first control signal have this second level in this grade shift register, make this first switch module and this not conducting of second switch assembly, and cause the 4th switch module and the neither conducting of the 5th switch module;
In cycle, this second control signal has this first level in this grade shift register in the 3rd sequential, makes the 4th switch module conducting, and exports this second voltage to the 5th input end; This first control signal has this first level simultaneously, makes this second switch assembly conducting, and exports this first voltage to the 5th control end, controls the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
41. signal generator as claimed in claim 38, wherein, this first control signal is the output signal that couples the next stage shift register of this shift register, and this second control signal is this first clock signal.
42. signal generator as claimed in claim 41, wherein, in this first sequential cycle, this first control signal has this second level in this grade shift register, make this not conducting of two switch modules, and cause the 4th switch module and the neither conducting of the 5th switch module;
In this second sequential cycle, this first control signal has this second level in this grade shift register, makes this not conducting of second switch assembly, and causes the 4th switch module and the neither conducting of the 5th switch module;
In cycle, this second control signal has this first level in this grade shift register in the 3rd sequential, makes the 4th switch module conducting, and exports this second voltage to the 5th input end; This first control signal has this first level simultaneously, makes this second switch assembly conducting, and exports this first voltage to the 5th control end, controls the 5th switch module conducting, and exports this second voltage to the 3rd output terminal.
43. signal generator as claimed in claim 38, wherein, this controlled switch assembly more comprises one the 6th switch module in each these shift register, and the 6th switch module comprises:
One the 6th input end is coupled to this second voltage;
One the 6th control end, in order to receive this output signal of any next stage shift register: and
One the 6th output terminal is coupled to the 4th output terminal.
44. signal generator as claimed in claim 38, wherein, this first switch module, this second switch assembly, the 3rd switch module, the 4th switch module and the 5th switch module are to be all the PMOS transistor.
45. a shift register, in order to receive an input signal and to export an output signal according to this, this shift register comprises:
One first switch module receives one first clock signal, and controls the input of this input signal according to this first clock signal;
One phase-shifts assembly is coupled to this first switch module, receives a second clock signal, and according to this second clock signal this input signal is carried out phase-shifts; And
One buck assembly is coupled to this phase-shifts assembly, receives one first control signal, after this phase-shifts assembly carries out phase-shifts with this input signal, draws high or downgrade the current potential of this output signal according to this first control signal.
46. shift register as claimed in claim 45, wherein, this phase-shifts assembly more comprises:
One second switch assembly is to be coupled to this first switch module, and in order to control the input of this second clock signal; And
One the 3rd switch module is to be coupled to one second voltage, and accepts the control of this second clock signal;
Wherein, this second clock signal inversion signal that is this first clock signal.
47. shift register as claimed in claim 46, wherein, this buck assembly more comprises:
One the 4th switch module is to be coupled to the 3rd switch module, and accepts the control of this first control signal, in order to control the input of one first voltage; And
One the 5th switch module is to be coupled to the 4th switch module and second switch assembly, in order to controlling the input of this second voltage, and exports this output signal according to this.
48. shift register as claimed in claim 47, wherein, this first control signal is this first clock signal.
49. shift register as claimed in claim 47, wherein, this first control signal is the output signal of next stage shift register.
50. shift register as claimed in claim 47, wherein, this buck assembly more comprises one the 6th switch module, is to be coupled to the 5th switch module, and accept the control of any next stage shift register output signal, in order to control the input of this second voltage.
51. shift register as claimed in claim 45, wherein, this phase-shifts assembly more comprises:
One second switch assembly is to be coupled to this first switch module, and in order to controlling the input of this second clock signal, and export this output signal according to this; And
One the 3rd switch module is to be coupled to this second switch assembly, and accepts the control of this first clock signal;
Wherein, this second clock signal inversion signal that is this first clock signal.
52. shift register as claimed in claim 51, wherein, this buck assembly more comprises:
One the 4th switch module is the control of accepting this first control signal, in order to control the input of one first voltage; And
One the 5th switch module is to be coupled to the 4th switch module and the 3rd switch module, in order to control the input of one second voltage.
53. shift register as claimed in claim 52, wherein, this first control signal is this first clock signal.
54. shift register as claimed in claim 52, wherein, this first control signal is the output signal of next stage shift register.
55. shift register as claimed in claim 52, wherein, this buck assembly more comprises one the 6th switch module, is to be coupled to the 5th switch module, and accept the control of any next stage shift register output signal, in order to control the input of this second voltage.
56. shift register as claimed in claim 45, wherein, this phase-shifts assembly more comprises:
One second switch assembly is to be coupled to this first switch module, and in order to controlling the input of this second clock signal, and export this output signal according to this; And
One the 3rd switch module is to be coupled to this second switch assembly;
Wherein, this second clock signal inversion signal that is this first clock signal.
57. shift register as claimed in claim 56, wherein, this buck assembly more comprises:
One the 4th switch module is to be coupled to the 3rd switch module, and accepts the control of this first control signal, in order to control the input of one first voltage; And
One the 5th switch module is to be coupled to the 3rd switch module, and accepts the control of this first clock signal, in order to control the input of this second voltage.
58. shift register as claimed in claim 57, wherein, this first control signal is this first clock signal.
59. shift register as claimed in claim 57, wherein, this first control signal is the output signal of next stage shift register.
60. shift register as claimed in claim 57, wherein, this buck assembly more comprises one the 6th switch module, is to be coupled to the 5th switch module, and accept the control of any next stage shift register output signal, in order to control the input of this second voltage.
CN200610006077A 2006-01-26 2006-01-26 Signal generator and its shift register Expired - Fee Related CN100578673C (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915698A (en) * 2012-10-18 2013-02-06 京东方科技集团股份有限公司 Shifting register unit, grid electrode drive circuit and display device
CN104202035A (en) * 2014-06-20 2014-12-10 友达光电股份有限公司 Bidirectional selection circuit, gate driver using the bidirectional selection circuit, and test circuit
CN105679238A (en) * 2016-01-05 2016-06-15 京东方科技集团股份有限公司 Shift register circuit, driving method, array substrate and display device thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102915698A (en) * 2012-10-18 2013-02-06 京东方科技集团股份有限公司 Shifting register unit, grid electrode drive circuit and display device
CN102915698B (en) * 2012-10-18 2016-02-17 京东方科技集团股份有限公司 Shift register cell, gate driver circuit and display device
CN104202035A (en) * 2014-06-20 2014-12-10 友达光电股份有限公司 Bidirectional selection circuit, gate driver using the bidirectional selection circuit, and test circuit
CN104202035B (en) * 2014-06-20 2017-04-12 友达光电股份有限公司 Bidirectional selection circuit, gate driver using the bidirectional selection circuit, and test circuit
CN105679238A (en) * 2016-01-05 2016-06-15 京东方科技集团股份有限公司 Shift register circuit, driving method, array substrate and display device thereof
CN105679238B (en) * 2016-01-05 2018-06-29 京东方科技集团股份有限公司 Shift-register circuit and its driving method, array substrate, display device

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