CN101008964A - Method and system for verifying multiple power supply regional design in application specific integrated circuit - Google Patents
Method and system for verifying multiple power supply regional design in application specific integrated circuit Download PDFInfo
- Publication number
- CN101008964A CN101008964A CN 200710063431 CN200710063431A CN101008964A CN 101008964 A CN101008964 A CN 101008964A CN 200710063431 CN200710063431 CN 200710063431 CN 200710063431 A CN200710063431 A CN 200710063431A CN 101008964 A CN101008964 A CN 101008964A
- Authority
- CN
- China
- Prior art keywords
- module
- register
- functional entity
- power supply
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013461 design Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012360 testing method Methods 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 230000006870 function Effects 0.000 claims description 6
- 238000012795 verification Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract 1
- 238000010200 validation analysis Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
This invention discloses one method to validate special integration circuit multiple power area design, which comprises the following steps: a, after electrifying the single panel, the said user terminal runs the said chip codes through validation software and aligning the said first register to close the relative function part to the first register; b, when the said user terminal judges function part relative second register status parameters and preset status parameters to determine multiple power area design error. This invention also discloses one validation system.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, in particular, is a kind of method and system of verifying multi-power supply area design in the special IC.
Background technology
In present special IC (ASIC) design, need carry out emulation to ASIC by the whole bag of tricks, thereby the function of checking ASIC can adopt wherein field programmable gate array (FPGA) chip to carry out simulating, verifying.In ASIC, have some modules usually and be operated under the different voltage, in actual applications, also will dynamically close or open certain module sometimes.For example, the LCDs of mobile phone needs to close under ideal case, and squeezes into when maybe needing to use other functions of mobile phone as phone, then needs to open LCDs.Thereby can module be divided according to the power supply area (Power Domain) of module work is different.Existing power supply area is divided into two kinds usually: the first, always be in the power supply area of opening, and for example (Power Manage Unit PMU) is exactly the module that belongs to this power supply area to Power Management Unit, is responsible for opening or closing other modules by it.The second, can be in opening or be in the power supply area of closed condition, for example LCD, sensor etc. are the modules that belongs to this power supply area.
Referring to shown in Figure 1, be the method for ASIC design in the prior art.Wherein, the first power supply area module is for always being in the module of opening, promptly when chip operation, belong to the just work of module of this power supply area, can control the unlatching of the module that belongs to this power supply area by the mode of configuration register or close in chip exterior.The second source regions module is for being in the module of On/Off state, and the module that belongs to this power supply area can be unlocked or be closed when chip operation.Register 11 is used for disposing the module of first power supply area that fpga chip connects; Register 13 is used for disposing the module in the second source zone that fpga chip connects; Isolated location 12 is used to prevent that the signal that belongs to the transmission of second source regions module from entering first power supply area; Isolated location 14 is used to prevent that the signal that belongs to the transmission of the first power supply area module from entering the second source zone, in the prior art, though there is isolated location in the signal of the first power supply area module and second source regions module but still can flows, cause the correctness that to verify the ASIC design between first power supply area and second source zone.
In sum, in the prior art ASIC is carried out in the process of simulation, have the design correct method whether to verify multi-power supply area in the ASIC design as yet.
Summary of the invention
The invention provides a kind of method and system of verifying multi-power supply area design in the special IC, can not effectively verify the problem that whether has mistake in the special IC in the multi-power supply area design in order to what the solution prior art existed.
The inventive method provides a kind of and verifies that the module in the method special IC that multi-power supply area designs in the special IC is divided into the first power supply area module and second source regions module, preserve the code after described special IC uses the hardware description language conversion in the field programmable gate array chip, described chip links to each other with testing single-board, the corresponding functional entity of each described second source regions module, described functional entity links to each other with described chip by described testing single-board, described testing single-board links to each other with user terminal, the described first power supply area module comprises first registers group and second registers group, one first register and one second corresponding described functional entity of register, this method comprises:
Behind A, the described Board Power up, described user terminal moves code in the described chip by verifying software, disposes the described functional entity that described first register cuts out this first register correspondence;
B, judge this functional entity correspondence when described user terminal the state parameter of second register when default state parameter does not conform to, determine that there is mistake in the multi-power supply area design.
Between steps A and step B, this method also comprises:
A1, described functional entity are revised the state parameter of the second corresponding register before closing fully.
The described first power supply area module is for always being in the module of initial state when described chip power, described second source regions module is for being in the module of On/Off state when described chip power.
Described first registers group is the control register group, and described second registers group is the status register group.
The invention also discloses a kind of verification system, module in the special IC is divided into the first power supply area module and second source regions module, the corresponding functional entity of each described second source regions module, the described first power supply area module comprises first registers group and second registers group, one first register and one second corresponding described functional entity of register, this system comprises: veneer, proofing chip, functional entity and user terminal;
Described veneer is used to connect the functional entity of described proofing chip and second source regions module correspondence; Link to each other with described user terminal;
Described proofing chip is used to preserve and move the code after special IC uses the hardware description language conversion;
Described functional entity is used for linking to each other with described proofing chip by described veneer, realizes the function of second source regions module;
Described user terminal is used for behind described Board Power up, moves code in the described chip by verifying software, disposes the described functional entity that described first register cuts out this first register correspondence; When the state parameter of second register of judging this functional entity correspondence does not conform to the state parameter of presetting, determine that there is mistake in the multi-power supply area design.
Described functional entity also is used for before closing fully revising the state parameter of the second corresponding register.
Described user terminal comprises: control module, analysis module;
Described control module is used for closing the described functional entity of this first register correspondence by disposing described first register; Obtain the state parameter of second register of described functional module correspondence;
Described authentication module is used for determining that there is mistake in the code in the described chip when the state parameter of second register of judging this functional entity correspondence does not conform to the state parameter of presetting.
The described first power supply area module is for always being in the module of initial state when described chip power, described second source regions module is for being in the module of On/Off state when described chip power.
Described first registers group is the control register group, and described second registers group is the status register group.
The method and system of multi-power supply area design in the checking special IC that the application of the invention provides, can verify in special IC and whether have mistake in the multi-power supply area design, shorten the cycle of chip checking, reduced the expense of chip checking.
Description of drawings
Fig. 1 is the synoptic diagram of ASIC design in the prior art;
Fig. 2 is a method synoptic diagram of the present invention;
Fig. 3 is a system architecture synoptic diagram of the present invention;
Fig. 4 is the system architecture synoptic diagram of user terminal among the present invention;
Fig. 5 is the system architecture synoptic diagram of one embodiment of the present of invention.
Embodiment
The present invention can't verify in the prior art for solving whether multi-power supply area design in the special IC exists the problem of mistake, following technical conceive is provided: the module in the special IC is divided into the first power supply area module and second source regions module, preserve the code after described special IC uses the hardware description language conversion in the field programmable gate array chip, described chip links to each other with testing single-board, the corresponding functional entity of each described second source regions module, described functional entity links to each other with described chip by described testing single-board, described testing single-board links to each other with user terminal, the described first power supply area module comprises first registers group and second registers group, one first register and one second corresponding described functional entity of register, behind the described Board Power up, described user terminal moves code in the described chip by verifying software, disposes the described functional entity that described first register cuts out this first register correspondence; When described user terminal judges that the state parameter of second register of this functional entity correspondence does not conform to the state parameter of presetting, determine that there is mistake in the multi-power supply area design.Compared with prior art, method of the present invention can verify effectively whether the multi-power supply area design exists mistake in the special IC, has shortened the cycle of special IC checking, has reduced the expense of checking.
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described.
Module in the special IC is divided into the first power supply area module and second source regions module, the corresponding functional entity of each described second source regions module, the described first power supply area module comprises control register group and status register group, a control register and the corresponding described functional entity of status register.
Referring to shown in Figure 2, the step that multi-power supply area designs in the checking special IC among the present invention comprises:
The functional entity of step 22, described second source regions module correspondence is placed on the described FPGA veneer, and described functional entity links to each other with described field programmable gate array chip by described FPGA veneer, and described FPGA veneer links to each other by base band with user terminal.
Behind step 23, the described Board Power up, user terminal moves code after the conversion of described use hardware description language by verifying software in described field programmable gate array chip, close the functional entity of this control register correspondence by the control register that disposes the described first power supply area module.
After described control register cut out described functional module, described functional module can be revised the state parameter of the status register of its described correspondence before closing fully.
Because the code in the described chip converts according to special IC, thereby there is mistake in the multi-power supply area design of determining special IC.
Referring to shown in Figure 3, system of the present invention comprises: veneer 31, proofing chip 32, second source zone entity 33, user terminal 34.
Wherein, described veneer 31 is used to connect described proofing chip 32 and second source zone entity 33; Link to each other with described user terminal 34;
Described proofing chip 32 is used to preserve and move the code after special IC uses the hardware description language conversion;
Described second source zone entity 33 is used for linking to each other with described proofing chip 32 by described veneer 31, realizes the function of second source regions module;
Described user terminal 34 is used for after described veneer 31 powers on, and moves code in the described proofing chip 32 by verifying software, disposes the described second source zone entity 33 that described first register cuts out this first register correspondence; When the state parameter of second register of judging these second source zone entity 33 correspondences does not conform to the state parameter of presetting, determine that there is mistake in the multi-power supply area design.
Described second source zone entity 33 also is used for revising the state parameter of second register of correspondence closing fully before.
Referring to shown in Figure 4, the user terminal among the present invention comprises: control module 41, authentication module 42.
Wherein, described control module 41 is used for closing the described functional entity of this first register correspondence by disposing described first register; Obtain the state parameter of second register of described functional module correspondence;
Described authentication module 42 is used for determining that there is mistake in the code in the described chip when the state parameter of second register of judging this functional entity correspondence does not conform to the state parameter of presetting.
Referring to shown in Figure 5, system architecture synoptic diagram for one embodiment of the present of invention, the module of special IC is divided into the first power supply area module and second source regions module, and described special IC uses the code after the hardware description language conversion to be kept in the proofing chip.The described first power supply area module is a Power Management Unit 51, and described Power Management Unit 51 comprises control register group 511 and status register group 512.Described second source regions module comprises: sensor assembly, liquid crystal display panel module, USB (universal serial bus) (USB) interface module, the functional entity of then described second source regions module correspondence comprises: sensor 52, LCD 53, USB interface 54.A control register and a status register in the corresponding described Power Management Unit of each functional entity, for example, described sensor 52 corresponding control register 1 and status registers 1, described LCD 53 corresponding control register 2 and status registers 2, described USB interface 54 corresponding control register 3 and status registers 3, by that analogy.Open or close by described control register control function entity, by the running status of described status register measuring ability entity.Since comprise three corresponding functional entitys in second source zone in the system that present embodiment provides, corresponding, in described Power Management Unit 51, comprise three control registers and three status registers.
Described proofing chip is positioned on the FPGA veneer, is used for the described special IC of emulation.Described sensor 52, LCDs 53 and USB interface 54 link to each other with described proofing chip 55 by described FPGA veneer, and described FPGA veneer links to each other with user terminal by base band.Behind the described Board Power up, described user terminal moves code in the described proofing chip 55 by verifying software.When described user terminal need verify whether the multi-power supply area design exists mistake, can dispose control register in the described Power Management Unit 51 and close a functional entity of second source regions module correspondence, for example, user terminal is closed described sensor 52 by the control register 1 that disposes described sensor 52 correspondences, and described sensor 52 can revise the state parameter of the status register 1 of its described correspondence before cutting out fully.Described user terminal is from described status register 1 described sensor 52 amended state parameters, when judging that described state parameter does not conform to the state parameter of presetting, determine that there is mistake in the code in the described proofing chip 55, thereby determine that there is mistake in the multi-power supply area design in the described special IC.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (9)
1, a kind of method of verifying multi-power supply area design in the special IC, module in the special IC is divided into the first power supply area module and second source regions module, preserve the code after described special IC uses the hardware description language conversion in the field programmable gate array chip, described chip links to each other with testing single-board, the corresponding functional entity of each described second source regions module, described functional entity links to each other with described chip by described testing single-board, described testing single-board links to each other with user terminal, the described first power supply area module comprises first registers group and second registers group, one first register and one second corresponding described functional entity of register, it is characterized in that this method comprises:
Behind A, the described Board Power up, described user terminal moves code in the described chip by verifying software, disposes the described functional entity that described first register cuts out this first register correspondence;
B, judge this functional entity correspondence when described user terminal the state parameter of second register when default state parameter does not conform to, determine that there is mistake in the multi-power supply area design.
2, method according to claim 1 is characterized in that, between steps A and step B, this method also comprises:
A1, described functional entity are revised the state parameter of the second corresponding register before closing fully.
3, method according to claim 1, it is characterized in that, the described first power supply area module is for always being in the module of initial state when described chip power, described second source regions module is for being in the module of On/Off state when described chip power.
4, method according to claim 1 is characterized in that, described first registers group is the control register group, and described second registers group is the status register group.
5, a kind of verification system, module in the special IC is divided into the first power supply area module and second source regions module, the corresponding functional entity of each described second source regions module, the described first power supply area module comprises first registers group and second registers group, one first register and one second corresponding described functional entity of register, it is characterized in that this system comprises: veneer, proofing chip, functional entity and user terminal;
Described veneer is used to connect the functional entity of described proofing chip and second source regions module correspondence; Link to each other with described user terminal;
Described proofing chip is used to preserve and move the code after special IC uses the hardware description language conversion;
Described functional entity is used for linking to each other with described proofing chip by described veneer, realizes the function of second source regions module;
Described user terminal is used for behind described Board Power up, moves code in the described chip by verifying software, disposes the described functional entity that described first register cuts out this first register correspondence; When the state parameter of second register of judging this functional entity correspondence does not conform to the state parameter of presetting, determine that there is mistake in the multi-power supply area design.
6, system according to claim 5 is characterized in that,
Described functional entity also is used for before closing fully revising the state parameter of the second corresponding register.
7, system according to claim 5 is characterized in that, described user terminal comprises: control module, analysis module;
Described control module is used for closing the described functional entity of this first register correspondence by disposing described first register; Obtain the state parameter of second register of described functional module correspondence;
Described authentication module is used for determining that there is mistake in the code in the described chip when the state parameter of second register of judging this functional entity correspondence does not conform to the state parameter of presetting.
8, system according to claim 5, it is characterized in that, the described first power supply area module is for always being in the module of initial state when described chip power, described second source zone film piece is for being in the module of On/Off state when described chip power.
9, system according to claim 5 is characterized in that, described first registers group is the control register group, and described second registers group is the status register group.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100634312A CN100561489C (en) | 2007-01-31 | 2007-01-31 | A kind of method and system of verifying multi-power supply area design in the special IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100634312A CN100561489C (en) | 2007-01-31 | 2007-01-31 | A kind of method and system of verifying multi-power supply area design in the special IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101008964A true CN101008964A (en) | 2007-08-01 |
| CN100561489C CN100561489C (en) | 2009-11-18 |
Family
ID=38697391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100634312A Expired - Fee Related CN100561489C (en) | 2007-01-31 | 2007-01-31 | A kind of method and system of verifying multi-power supply area design in the special IC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100561489C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719181B (en) * | 2009-12-03 | 2012-07-04 | 无锡中星微电子有限公司 | Dynamic verification device and dynamic verification method for multi-power domain integrated circuit |
| CN105137330A (en) * | 2014-05-22 | 2015-12-09 | 炬芯（珠海）科技有限公司 | Verification device of multiple-voltage domain digital circuit and operation method thereof |
| CN110114768A (en) * | 2016-10-31 | 2019-08-09 | 美商新思科技有限公司 | Power calculation logic |
-
2007
- 2007-01-31 CN CNB2007100634312A patent/CN100561489C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101719181B (en) * | 2009-12-03 | 2012-07-04 | 无锡中星微电子有限公司 | Dynamic verification device and dynamic verification method for multi-power domain integrated circuit |
| CN105137330A (en) * | 2014-05-22 | 2015-12-09 | 炬芯（珠海）科技有限公司 | Verification device of multiple-voltage domain digital circuit and operation method thereof |
| CN105137330B (en) * | 2014-05-22 | 2018-09-25 | 炬芯（珠海）科技有限公司 | The verification device and its operation method of multiple voltage domain digital circuit |
| CN110114768A (en) * | 2016-10-31 | 2019-08-09 | 美商新思科技有限公司 | Power calculation logic |
| CN110114768B (en) * | 2016-10-31 | 2023-09-08 | 美商新思科技有限公司 | Power calculation logic |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100561489C (en) | 2009-11-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103678745B (en) | Cross-platform multi-level integrated design system for FPGA | |
| CN104483959A (en) | Fault simulation and test system | |
| CN104076814A (en) | Automobile ECU measurement system based on hardware-in-loop simulation | |
| CN106569118A (en) | Chip short circuit failure detection system and method | |
| CN100561489C (en) | A kind of method and system of verifying multi-power supply area design in the special IC | |
| CN204086979U (en) | A kind of electric vehicle motor controller hardware-in―the-loop test system | |
| CN102479132A (en) | Test system and test method for multiple chips | |
| CN101714110A (en) | Computer mainboard and startup power on self detection method thereof | |
| WO2008048512A3 (en) | Trusted platform module management system and method | |
| CN104219003A (en) | Communication device, test system and test method thereof | |
| CN106200840A (en) | A kind of computer temperature method for handover control | |
| CN109885905A (en) | A kind of verifying system improving digital circuitry functions verification efficiency | |
| CN105279081A (en) | In-loop test method for car controller development software | |
| CN103514074A (en) | MVB network card development method and platform | |
| CN103576667B (en) | Method, device and system for testing main control board | |
| CN114840191A (en) | Software code automatic generation method, device, equipment and readable storage medium | |
| CN101251823B (en) | DSP assembly language program verification method and device | |
| CN110096291A (en) | Power management chip upgrades circuit, method and the network equipment | |
| EP1850230A3 (en) | Feature-oriented test program development and execution | |
| CN103543682A (en) | Method and device for identifying input state by common IO port | |
| US7415685B2 (en) | Method of verifying the power off effect of a design entity at register transfer level and method of modeling the power off effect | |
| CN103871298A (en) | Server demonstration platform | |
| CN102609270B (en) | A kind of monitoring mechanism being applied to ECU configuration interface | |
| CN105137330A (en) | Verification device of multiple-voltage domain digital circuit and operation method thereof | |
| CN113283008A (en) | Civil aircraft system behavior state safety verification method based on model conversion |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: WUXI VIMICRO CO., LTD. Free format text: FORMER OWNER: BEIJING ZHONGXING MICROELECTRONICS CO., LTD. Effective date: 20110119 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 100083 15/F, SHI'NING BUILDING, NO.35, XUEYUAN ROAD, HAIDIAN DISTRICT, BEIJING TO: 214028 610, NATIONAL IC DESIGN PARK (CHUANGYUAN BUILDING), NO.21-1, CHANGJIANG ROAD, NEW DISTRICT, WUXI CITY, JIANGSU PROVINCE |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20110119 Address after: 214028 national integrated circuit design (21-1), Changjiang Road, New District, Jiangsu, Wuxi, China, China (610) Patentee after: Wuxi Vimicro Co., Ltd. Address before: 100083, Haidian District, Xueyuan Road, Beijing No. 35, Nanjing Ning building, 15 Floor Patentee before: Beijing Vimicro Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091118 Termination date: 20130131 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |