CN100595879C - Scheduling method of silicon slice transmission course - Google Patents
Scheduling method of silicon slice transmission course Download PDFInfo
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- CN100595879C CN100595879C CN200710062728A CN200710062728A CN100595879C CN 100595879 C CN100595879 C CN 100595879C CN 200710062728 A CN200710062728 A CN 200710062728A CN 200710062728 A CN200710062728 A CN 200710062728A CN 100595879 C CN100595879 C CN 100595879C
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Abstract
The invention discloses a dispatching method in the process of transiting silicon chips, which comprises firstly calculating the transmission cost S(i)(j) of joints from the ith to the jth of any silicon chip in a plurality of silicon chips, then calculating the transmission costs S(i)(k)+S(i)(k) of joints from the ith to the kth and from the kth to the jth of the silicon chip, comparing S(i)(j) with S(i)(k)+S(i)(k), if S(i)(j)>S(i)(k)+S(i)(k), then replacing S(i)(j) with S(i)(k)+S(i)(k), and so forth, finally obtaining the least transmission cost S(i)(j) min of joints from the ith to the jthof the silicon chip, which is the shortest way. The invention has the advantages that the transmission of the silicon chip is reasonable, the manufacturing period is short, the work efficiency is high, and the invention is mainly adapted to the manufacturing procedure of semi-conductor silicon chip and dispatches the transmission of the silicon chips in the silicon chip processing device.
Description
Technical field
The present invention relates to a kind of production technology dispatching method, be specifically related in a kind of semiconductor silicon machining process the dispatching method of silicon slice transmission course.
Background technology
Semi-conductor silicon chip processed needs multiple working procedure, and the silicon chip process equipment comprises a plurality of chambers that silicon chip is processed.As shown in Figure 1, comprise that four are carried out the reaction chamber of etching technics to silicon chip, are respectively PM1, PM2, PM3, PM4; Also comprise three sheet storehouses, be respectively P1, P2, P3, be used for depositing the silicon chip of process task; Also comprise an AL2 (locating calibration device), be used for silicon chip is positioned calibration; Also comprise a propagation in atmosphere chamber and a vacuum transmission chamber, between be communicated with by LA, LB (vacuum lock).Be provided with an AFE (atmosphere manipulator) in the propagation in atmosphere chamber, be used between P1, P2, P3, AL2, LA, LB, transmitting silicon chip; Be provided with a VBE (vacuum mechanical-arm) in the vacuum transmission chamber, be used between LA, LB, PM1, PM2, PM3, PM4, transmitting silicon chip.
In the silicon chip working process, manipulator is got sheet successively from the sheet storehouse, through transmission chamber, imports silicon chip the reaction chamber of every process steps correspondence into according to definition, carries out etching technics and handles or other processing technology.
In this process, process task enters the silicon chip process equipment to the total time of leaving the silicon chip process equipment, just the arbitrary silicon chip that is comprised from process task enters the time that all silicon chips that the silicon chip process equipment comprised in the process task leave the silicon chip process equipment, is called a manufacturing cycle.
The factor of decision manufacturing cycle mainly contains the following aspects:
AFE gets sheet time=AFE time of moving horizontally+and AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AFE film releasing time=AFE time of moving horizontally+AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AL2 locatees the alignment time to silicon chip;
LA, LB pumpdown time;
LA, LB fill the atmosphere time;
VBE gets sheet time=VBE rotational time+VBE semi-girder time+VBE and contracts the arm time;
Silicon chip carries out the processing technology time in PM1, PM2, PM3, PM4.
In above-mentioned silicon chip working process, a plurality of nodes such as P1, P2, P3, AFE, AL2, LA, LB, VBE, PM1, PM2, PM3, PM4 are arranged in the transmission path of silicon chip, select different biography sheet paths, use different scheduling strategies, can obtain different temporal summation.
At present, ordinary circumstance is after all processing steps of the current silicon chip of processing are finished, and imports a slice down again into, that is to say, and be that unit is dispatched with single silicon chip.The situation that so just has most node free time, the path of chip transmission be shortest path not necessarily also, and the manufacturing cycle is longer, and production efficiency is low.
Summary of the invention
The dispatching method that the purpose of this invention is to provide the silicon slice transmission course that a kind of manufacturing cycle is short, production efficiency is high.
The objective of the invention is to be achieved through the following technical solutions:
The dispatching method of silicon slice transmission course of the present invention is used for dispatching the transmission path of a plurality of silicon chips in N node of silicon chip process equipment, and wherein N is a positive integer, comprises step:
A, at first calculate the transmission cost S[i of arbitrary silicon chip in a plurality of silicon chips from i node to j node] [j], wherein 1≤i, j≤N;
B, calculate described silicon chip from i node to k node, the transmission cost S[i from k node to j node again] [k]+S[k] [j], wherein 1≤k≤N;
C, comparison S[i] [j] and S[i] [k]+S[k] size of [j], if S[i] [j]＞S[i] [k]+S[k] [j], then use S[i] [k]+S[k] [j] replace S[i] [j], and the like, get all numerical value of k=1～N, obtain the minimum transfer cost S[i of described silicon chip at last from i node to j node] [j] min.
Before the described steps A, at first calculate the transmission cost S of the direct connection between any two nodes in the N of silicon chip in the silicon chip process equipment node, if the S[i in the described steps A] [j] different with S, then use S[i] [j] replace S.
Described node comprises following at least two nodes:
First storehouse P1; Second storehouse P2; The 3rd storehouse P3; Locating calibration device AL2; The first vacuum lock LA; The second vacuum lock LB; Atmosphere manipulator AFE; Vacuum mechanical-arm VBE; The first reaction chamber PM1; The second reaction chamber PM2; The 3rd reaction chamber PM3; The 4th reaction chamber PM4.
Described transmission cost S[i] [j] comprise following at least one:
AFE gets sheet time=AFE time of moving horizontally+and AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AFE film releasing time=AFE time of moving horizontally+AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AL2 locatees the alignment time to silicon chip;
LA and/or LB pumpdown time;
LA and/or LB fill the atmosphere time;
VBE gets sheet time=VBE rotational time+VBE semi-girder time+VBE and contracts the arm time;
Silicon chip carries out the processing technology time in PM1, PM2, PM3, PM4.
As seen from the above technical solution provided by the invention, the dispatching method of silicon slice transmission course of the present invention, owing at first calculate the transmission cost S[i of arbitrary silicon chip in a plurality of silicon chips from i node to j node] [j], calculate then described silicon chip from i node to k node, transmission cost S[i from k node to j node again] [k]+S[k] [j], S[i relatively] [j] and S[i] [k]+S[k] size of [j], if S[i] [j]＞S[i] [k]+S[k] [j], then use S[i] [k]+S[k] [j] replace S[i] [j], and the like, get all numerical value of k=1～N, obtain the minimum transfer cost S[i of silicon chip at last from i node to j node] [j] min, i.e. shortest path.Chip transmission is reasonable, the manufacturing cycle is short, production efficiency is high, mainly is applicable in the semi-conductor silicon chip course of processing, dispatches the transmission of a plurality of silicon chips in the silicon chip process equipment.
Description of drawings
Fig. 1 is the floor plan schematic diagram of silicon chip process equipment.
Embodiment
The dispatching method of silicon slice transmission course of the present invention is mainly used in the semi-conductor silicon chip course of processing, dispatches the transmission path in the N of a plurality of silicon chips in the silicon chip process equipment node, and wherein N is a positive integer, also can be used for the scheduling of other transmission equipment.
As shown in Figure 1, the silicon chip process equipment comprises following node:
First storehouse P1; Second storehouse P2; The 3rd storehouse P3; Locating calibration device AL2; The first vacuum lock LA; The second vacuum lock LB; Atmosphere manipulator AFE; Vacuum mechanical-arm VBE; The first reaction chamber PM1; The second reaction chamber PM2; The 3rd reaction chamber PM3; The 4th reaction chamber PM4.
The dispatching method of silicon slice transmission course of the present invention can calculate the shortest path between above-mentioned any two nodes, certainly, also comprises the situation that also comprises a node in theory.
Concrete computational process comprises:
Step 1, at first calculate the transmission cost S[i of arbitrary silicon chip in a plurality of silicon chips from i node to j node] [j], wherein 1≤i, j≤N;
Step 2, calculate described silicon chip from i node to k node, the transmission cost S[i from k node to j node again] [k]+S[k] [j], wherein 1≤k≤N;
Step 3, S[i relatively] [j] and S[i] [k]+S[k] size of [j], if S[i] [j]＞S[i] [k]+S[k] [j], then use S[i] [k]+S[k] [j] replace S[i] [j], and the like, get all numerical value of k=1～N, obtain the minimum transfer cost S[i of described silicon chip at last from i node to j node] [j] min.
Above-mentioned transmission cost S[i] [j] be the length of i node to the path of j node, here said path length be not simple span from length, and be meant power on the transmission path, complexity just, in the transmission course of silicon chip, mainly be time factor, can certainly comprise other factors.
The concrete time that influences chip transmission comprises following at least one:
AFE gets sheet time=AFE time of moving horizontally+and AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AFE film releasing time=AFE time of moving horizontally+AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AL2 locatees the alignment time to silicon chip;
LA and/or LB pumpdown time;
LA and/or LB fill the atmosphere time;
VBE time=VBE rotational time+VBE semi-girder time+VBE contracts the arm time;
Silicon chip carries out the processing technology time in PM1, PM2, PM3, PM4.
At present, mathematical Floyd shortest path first can simply be described as:
In one network, if between two nodes direct causality is arranged, then these two nodes directly are communicated with, on the arc that connects two nodes, put on its cost or power, it should be noted that such cost not necessarily the symmetry, being A needs not be equal to the cost of B to A to the cost of B, is example to navigate in the practical problem, has downstream and difference against the current.In network, provide two nodes, ask path the shortest between these two nodes, make through the cost sum minimum on this paths Here it is shortest route problem.
The present invention is applied to the Floyd shortest path first scheduling of silicon slice transmission course just, in fact separating of requiring is a matrix S [N] [N], S[i wherein] [j] expression node i is to the shortest path of j, algorithm is the spitting image of dynamic programming algorithm, even it is more simpler, different is, and what to plan here is a matrix, rather than simple array.
In concrete the calculating, before the described step 1, at first calculate the transmission cost S of the direct connection between any two nodes in the N of silicon chip in the silicon chip process equipment node, as initial value, if the S[i in the described step 1] [j] different with S, then use S[i] [j] replace S, then in the process of carrying out step 2 and step 3 to S[i] value of [j] constantly upgrades, obtain the minimum transfer cost S[i of described silicon chip at last from i node to j node] [j] min, just so-called shortest path.
With the chip transmission between sheet storehouse and the vacuum lock is example:
Have 7 node P1, P2, P3, AFE, LA, LB, AL2
The transmission cost that directly is communicated with between these 7 nodes, the initial value of transmission cost S is as shown in table 1, the big more expression access path of numeral is long more, when between two nodes direct path being arranged, value corresponding is a minimum value 1, because physically do not have direct path between some node, when not having direct path between two nodes, its corresponding numerical value is maximum 65535.
Table 1, the initial value of the transmission cost S that directly is communicated with between node P1, P2, P3, AFE, LA, LB, the AL2:
| P1 | P2 | P3 | AL2 | AFE | LA | LB | |
| P1 | 1 | 65535 | 65535 | 65535 | 1 | 65535 | 65535 |
| P2 | 65535 | 1 | 65535 | 65535 | 1 | 65535 | 65535 |
| P3 | 65535 | 65535 | 1 | 65535 | 1 | 65535 | 65535 |
| AL2 | 65535 | 65535 | 65535 | 1 | 1 | 65535 | 65535 |
| AFE | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| LA | 65535 | 65535 | 65535 | 65535 | 1 | 1 | 65535 |
| LB | 65535 | 65535 | 65535 | 65535 | 1 | 65535 | 1 |
When state changes, dynamically update table 1.The renewal principle is as follows:
Numerical value between different P1, P2, P3 and the AFE is determined according to the distance whether silicon chip and AFE and P1, P2, P3 are arranged among P1, P2, the P3.If there is not silicon chip, then transmission cost is 65535, if silicon chip is arranged, then distance is far away more, and it is long more that just AFE moves horizontally the time, and transmission cost is big more
Whether the numerical value between LA, LB and the AFE according to having vacant position among the pressure state among LA, the LB and LA, the LB is decided, if there is not the room, then transmission cost is 65535, if have vacant position, then pressure is more near atmosphere, and the time that promptly needs to open vacuum lock is short more, and transmission cost is more little
According to real-time status, carry out the shortest path between above-mentioned step 1, step 2, every pair of node of step 3 calculating successively, relatively (P1 then, LA), (P1, LB), (P2, LA), (P2, LB), (P3, LA), (P3, LB) the path numerical value of these 6 pairs of nodes is selected the shortest a pair of node, and is right as the node that passes sheet.After the biography sheet was finished, the update mode table calculated next time.
When not having among LA or the LB under the situation in room, then close door between LA or LB and the propagation in atmosphere chamber, vacuumize among LA or the LB, open the door between LA or LB and the vacuum transmission chamber.Then, between LA, LB, VBE, PM1, PM2, PM3, PM4, transmit silicon chip in a manner described.
The present invention is applied to the scheduling of silicon slice transmission course with the Floyd shortest path first, and chip transmission is reasonable, the manufacturing cycle is short, production efficiency is high, mainly is applicable in the semi-conductor silicon chip course of processing, dispatches the transmission of a plurality of silicon chips in the silicon chip process equipment.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.
Claims (2)
1, a kind of dispatching method of silicon slice transmission course is used for dispatching the transmission path of a plurality of silicon chips in N node of silicon chip process equipment, and wherein N is a positive integer, it is characterized in that, comprises step:
A, at first calculate the transmission cost S[i of arbitrary silicon chip in a plurality of silicon chips from i node to j node] [j], wherein 1≤i, j≤N;
B, calculate described silicon chip from i node to k node, the transmission cost S[i from k node to j node again] [k]+S[k] [j], wherein 1≤k≤N;
C, comparison S[i] [j] and S[i] [k]+S[k] size of [j], if S[i] [j]＞S[i] [k]+S[k] [j], then use S[i] [k]+S[k] [j] replace S[i] [j], and the like, get all numerical value of k=1～N, obtain the minimum transfer cost S[i of described silicon chip at last from i node to j node] [j] min;
Described node comprises following at least two nodes:
First storehouse P1; Second storehouse P2; The 3rd storehouse P3; Locating calibration device AL2; The first vacuum lock LA; The second vacuum lock LB; Atmosphere manipulator AFE; Vacuum mechanical-arm VBE; The first reaction chamber PM1; The second reaction chamber PM2; The 3rd reaction chamber PM3; The 4th reaction chamber PM4;
Described transmission cost S[i] [j] comprise following at least one:
AFE gets sheet time=AFE time of moving horizontally+and AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AFE film releasing time=AFE time of moving horizontally+AFE vertical moving time+AFE semi-girder time+AFE contracts the arm time;
AL2 locatees the alignment time to silicon chip;
LA and/or LB pumpdown time;
LA and/or LB fill the atmosphere time;
VBE gets sheet time=VBE rotational time+VBE semi-girder time+VBE and contracts the arm time;
Silicon chip carries out the processing technology time in PM1, PM2, PM3, PM4.
2, the dispatching method of silicon slice transmission course according to claim 1, it is characterized in that, before the described steps A, at first calculate the transmission cost S of the direct connection between any two nodes in the N of silicon chip in the silicon chip process equipment node, if the S[i in the described steps A] [j] different with S, then use S[i] [j] replace S.
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| CN101751025B (en) * | 2008-12-12 | 2012-06-06 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon slice optimal scheduling method and device |
| CN103811292B (en) * | 2012-11-07 | 2016-08-10 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Silicon chip process and treat system and processing method |
| CN104752128A (en) * | 2013-12-25 | 2015-07-01 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Wafer processing system and wafer processing method |
| CN103700022A (en) * | 2013-12-27 | 2014-04-02 | 浙江大学 | Methods and device for scheduling production of semiconductor products |
| CN105552010A (en) * | 2015-12-11 | 2016-05-04 | 中国电子科技集团公司第四十八研究所 | Substrate conveying system for silicon epitaxial growth |
| CN106898572B (en) * | 2015-12-17 | 2019-07-05 | 北京北方华创微电子装备有限公司 | Material dispatch method and system based on equipment real-time status |
| CN107871195A (en) * | 2016-09-28 | 2018-04-03 | 北京北方华创微电子装备有限公司 | The schedule sequences generation method and device of a kind of apparatus for production line |
| CN110632902B (en) * | 2019-09-06 | 2021-03-02 | 北京北方华创微电子装备有限公司 | Material processing path selection method and device |
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Address after: 100176 Beijing economic and Technological Development Zone, Wenchang Road, No. 8, No. Patentee after: Beijing North China microelectronics equipment Co Ltd Address before: 100016, building 2, block M5, No. 1 East Jiuxianqiao Road, Beijing, Chaoyang District Patentee before: Beifang Microelectronic Base Equipment Proces Research Center Co., Ltd., Beijing |