CN100589082C - The testing fixture debug system - Google Patents
The testing fixture debug system Download PDFInfo
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- CN100589082C CN100589082C CN200410076920A CN200410076920A CN100589082C CN 100589082 C CN100589082 C CN 100589082C CN 200410076920 A CN200410076920 A CN 200410076920A CN 200410076920 A CN200410076920 A CN 200410076920A CN 100589082 C CN100589082 C CN 100589082C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3664—Environments for testing or debugging software
Abstract
The invention provides be not with reference to testing fixture and constitute testing fixture inscape each figure and following signal path successively and can know the bang path of essential signal and the testing fixture debug system of relevant information easily.The indexing unit 60 that has the mutual link information 59 of internal wiring information 58, the inscape of the inscape that constitutes testing fixture and come the recall signal bang path according to wiring information 58 and link information 59, by specifying any terminal or wiring arbitrarily, obtain desirable signaling path information.In addition, direct input media 63, storage with the input of wiring information and conversion interface arrangement 62, wiring information and the hardware expanding of testing fixture partly constitute relevant information set up hardware information 65, program internal variable and with the link information 68 of the input and output terminal of testing fixture and with the corresponding label information 69 of program internal variable, comprise these information and come the recall signal bang path interior.
Description
Technical field
The present invention relates to be applicable to the testing fixture that carries out product examination in the production line of general industry products such as electric product and engineering goods and the production system, relate to according to checking that the object utilization is programmed and realize the testing fixture debug system able to programme of checks sequence and judgment processing.
Background technology
It was a kind of method of computer program in the past, be to store the storer of carrying out the information that function and a plurality of data mode define to a plurality of to comprising, in order to control virtual device and device at least 1 and the display device of display image, accept the device of user's input, and the method for the executive program of data processor, this method has the data flow diagram number of assembling steps, the front panel number of assembling steps, and executable program generates step, aforementioned data flow graph number of assembling steps is with the data flow diagram on the aforementioned display, promptly comprise and aforementioned a plurality of some corresponding function icons of carrying out function, some corresponding variable icon with aforementioned a plurality of data modes, the scheduling icon of the control stream of expression aforementioned data flow graph, and the data flow diagram of aforementioned functions icon and aforementioned variable icon and the interconnective camber line of aforementioned scheduling icon assembled according to aforementioned user's input, aforementioned front panel number of assembling steps is assembled front panel (frontpanel) according to user's input on display, and aforementioned executable program generates step with executable program, promptly comprise shown in the aforementioned functions icon and utilize shown in the aforementioned camber line the interconnective aforementioned function of carrying out more than 1 and 1 like that, and utilize the executable program that has the control stream that aforementioned at least 1 the 1st function icon is established shown in the aforementioned scheduling icon like that, according to providing the aforementioned front panel of user interface to generate to aforementioned data flow graph and aforementioned executable program, aforementioned data flow graph number of assembling steps comprises at least 1 the 1st function icon in the aforementioned data flow graph is placed step in the aforementioned scheduling icon of aforementioned data flow graph in fact, aforementioned executable program has as the control stream that aforementioned 1 the 1st function icon is established shown in placing aforementioned 1 the 1st function icon in the aforementioned scheduling icon in fact at least at least, aforementioned data flow graph number of assembling steps comprises the outer step of aforementioned scheduling icon that at least 1 the 2nd function icon in the aforementioned data flow graph is placed the aforementioned data flow graph in fact, aforementioned executable program does not have the control stream that aforementioned at least 1 the 2nd function is determined for aforementioned at least 1 the 2nd function icon is placed in fact outside the aforementioned scheduling icon.(for example with reference to patent documentation 1)
In addition, wire harness test unit in the past, be that each terminal inspection by the connector that connects respectively for the two ends with each electric wire that constitutes wire harness has or not and other terminal conducting, whether test wire harness good, in such wire harness test unit, has 1 control module, and a plurality of inspection units of sharing the regulation terminal checking in the terminal of aforementioned connector respectively, aforementioned control module has the normal normal connection memory storage that connects data of storage, read aforementioned normal connection data of storing in the aforementioned memory storage and the conveyer of reading that sends aforementioned a plurality of inspection units to according to checking commencing signal, from the terminal of aforementioned connector, select to send after 1 the indication of the terminal that drives this selection successively and output unit is indicated in the driving of aforementioned a plurality of inspection unit outputs, send indication that utilizes beginning checking between this driving indication output unit is selected and indication drives aforementioned drive terminal and other terminal and the inspection that aforementioned a plurality of inspection units are exported are begun to indicate output unit, and send collect utilize this inspection begin to indicate the checking that output unit begins the result indication and to the collection indication output unit of aforementioned a plurality of inspection units outputs, each inspection unit of aforementioned a plurality of inspection units has storage from the aforementioned memory storage of reading the aforementioned normal connection data of conveyer transmission, according to indicating the drive unit that drives selected terminal from the driving of aforementioned driving indication output unit, begin to indicate according to the inspection that begins to indicate output unit from aforementioned inspection and check successively between the terminal that aforementioned drive unit drives and the terminal that this inspection unit except the terminal of this driving is shared that to utilizing formation after the conducting is connected the testing fixture of data, aforementioned normally be connected the comparison device that data contrast back formation inspection result data with what store in the connection data of utilizing this testing fixture to form and the aforementioned memory storage, and the carrying device of aforementioned control module being sent according to the inspection result data that the collection indication from aforementioned collection indication output unit will utilize aforementioned comparison device to form as a result, aforementioned control module is collected the aforementioned inspection result data of sending out from the aforementioned result carrying device of aforementioned a plurality of inspection units, whether according to the inspection result data of this collection, it is good to test wire harness.(for example with reference to patent documentation 2)
[patent documentation 1] No. the 3016783rd, patent (claim 1)
[patent documentation 2] No. the 2907249th, patent (claim 1)
In the program technic of aforementioned patent document 1, as not comprising wire harness, wiring conversion substrate and anchor clamps in the inscape of testing fixture.Thereby in the debugging operation of reality, the problem of existence is to take time and energy and make mistakes easily.
In addition, be that only relevant wire harness itself is checked design mistake and assembly defect in the debugging of the wire harness shown in the aforementioned patent document 2 operation.That is not that the testing fixture of the key element part that constitutes wire harness is debugged.
The invention provides not with reference to testing fixture and constitute testing fixture inscape each figure and following signal path successively and can know the bang path of essential signal and the testing fixture debug system of relevant information easily.
Summary of the invention
Testing fixture debug system according to the present invention is in the debug system of the testing fixture checked according to program, the indexing unit that has the mutual link information of internal wiring information, the inscape of the inscape that constitutes testing fixture and come the recall signal bang path according to these wiring information and link information, by indicating any terminal or wiring arbitrarily, obtain desirable signaling path information.
According to the present invention, in the testing fixture debug system of checking according to program, because the indexing unit that has the mutual link information of internal wiring information, the inscape of the inscape that constitutes testing fixture and come the recall signal bang path according to wiring information and above-mentioned link information, therefore can be correctly and know desirable signaling path easily, have the effect that improves the debugging efficiency of operation.
Description of drawings
Figure 1 shows that the pie graph of the testing fixture of prerequisite technology according to the present invention.
The process flow diagram of the checks sequence that the testing fixture that Figure 2 shows that Fig. 1 carries out according to program and the process flow diagram of test signal and answer signal.
Fig. 3 (a) is the harness wiring figure between DA transducer and wiring conversion substrate in the testing fixture of Fig. 1.
Fig. 3 (b) is the wiring diagram of wiring conversion substrate in the testing fixture of Fig. 1.
Fig. 3 (c) is the harness wiring figure between wiring conversion substrate and anchor clamps in the testing fixture of Fig. 1.
Fig. 3 (d) is the wiring diagram of anchor clamps in the testing fixture of Fig. 1.
Fig. 4 is the process flow diagram of the order of debugging with method in the past in the testing fixture of Fig. 1.
Fig. 5 (a) is depicted as the formation block scheme according to the testing fixture debug system of the invention process form 1.
Fig. 5 (b) is depicted as the formation block scheme according to the testing fixture debug system of the invention process form 2.
Fig. 5 (c) is depicted as the formation block scheme according to the testing fixture debug system of the invention process form 3.
Fig. 5 (d) is depicted as the formation block scheme according to the testing fixture debug system of the invention process form 4.
Fig. 5 (e) is depicted as the formation block scheme according to the testing fixture debug system of the invention process form 5.
Figure 6 shows that formation block scheme according to the testing fixture debug system of the invention process form 6.
Figure 7 shows that concrete example according to the testing fixture debug system of the invention process form 6.
The key diagram that Fig. 8 (a) exports as complete list for the signaling path that the testing fixture debug system that will utilize the invention process form 1 is retrieved.
The key diagram that Fig. 8 (b) exports as complete list for the signaling path that the testing fixture debug system that will utilize the invention process form 4 is retrieved.
The signaling path that Fig. 9 (a) retrieves for the testing fixture debug system that will utilize example 1 in the wiring diagram of Fig. 3 (a) is drawn as the key diagram of thick line output.
The signaling path that Fig. 9 (b) retrieves for the testing fixture debug system that will utilize example 1 in the wiring diagram of Fig. 3 (b) is drawn as the key diagram of thick line output.
The signaling path that Fig. 9 (c) retrieves for the testing fixture debug system that will utilize example 1 in the wiring diagram of Fig. 3 (c) is drawn as the key diagram of thick line output.
The signaling path that Fig. 9 (d) retrieves for the testing fixture debug system that will utilize example 1 in the wiring diagram of Fig. 3 (d) is drawn as the key diagram of thick line output.
Figure 10 shows that process flow diagram according to the retrieval flow of the testing fixture debug system of the invention process form.
Figure 11 shows that testing fixture figure with device that the hardware of the invention process form 2 is expanded.
Label declaration
1 display device, 2 robot calculator, 3DA translation circuit, 4,6,9 wire harness, 5 wiring conversion substrates, 7 check object, 8 anchor clamps, 10AD translation circuit, 36,41,46,52 wiring diagrams, 37,42,45,47,49,50,53,55 connectors, 38,43,44,48,51,54,56 pins, No. 391 pin, 40 pin name, the essential part of 57 testing fixture debug systems, 58 wiring information, 59 link informations, 60 indexing units, 61 output units, input of 62 wiring information and conversion interface arrangement, the direct input media of 63 wiring information, 64 configurations, 65 set up hardware information, 66 program editings, 67 programs, 68 program internal variables, 69 label informations, 76 desirable terminals, 77 complete lists, the row of the inscape of 78 expression testing fixtures, the row of 79 expression connector numberings, the row of 80 expression pin numberings, 81 program internal variables, 82～93,109 thick lines
Embodiment
Technology as the invention prerequisite
On production line or in the production system, carried out certain processing and assembling to manufacturing a product after, whether product or semi-manufacture have been finished, utilize testing fixture inspection according to standard in order to check.Testing fixture provides test signal to checking each position order according to the rules that object promptly manufactures a product.This signal each functional block by manufacturing a product is checked by testing fixture answer signal.When this answer signal belongs in the scope of regulation, judge to manufacture a product, in the time of beyond specialized range, for defective to qualified.Under underproof situation, after perhaps reprocessing, utilize testing fixture inspection again, perhaps get rid of from production line.
For example, under the situation of electric product, it is made up of various circuit modules, when checking whether certain circuit module utilizes qualified components and parts correctly to assemble, testing fixture proposes the voltage or the electric current of test usefulness to this circuit module, this test signal is by this circuit module, export to the outside as output voltage or electric current, perhaps the circuit module to next stage transmits, testing fixture detects this output signal, and compare with the specified standard value, by so whether qualified this circuit module being carried out judgement.In general, electric product is the aggregate of such circuit module, and testing fixture utilizes test signal to test successively to each module order according to the rules, finally is the certified products or the judgement of unacceptable product.
Figure 1 shows that the pie graph of the testing fixture of testing successively according to the order of afore mentioned rules.In the drawings, testing fixture is the center from robot calculator 2 generally, by display device 1, the DA translation circuit 3 of test signal takes place, detect the AD translation circuit 10 of answer signal, DA translation circuit 3 is combined the connector cable (wire harness) 4 and 9 of usefulness with AD translation circuit 10, it is the wiring conversion substrate 5 that a wire harness is used that a plurality of wire harness are gathered, the wire harness 6 of connecting wiring conversion substrate 5 and anchor clamps 8, and have checking that object 7 directly provides the anchor clamps 8 of the pin of signal and acknowledge(ment) signal to constitute, and can enumerate a guy's computing machine as an example of this robot calculator 2.Here, checks sequence, the reference value that judges whether qualified usefulness and comparison process thereof are to utilize the program in the robot calculator to describe and carry out.
Below, the example that the testing fixture that Figure 2 shows that Fig. 1 utilizes processing that program carries out and signal to transmit.The order of checking utilizes the program shown in the process flow diagram of Fig. 2 to realize, utilizes language such as C or BASIC to describe.In this checks sequence, in the step S14 of test signal is provided, by DA translation circuit 3 to external output signal.This signal is via wire harness 4 and wiring conversion substrate 5, and the wire harness 6 via next stage is added on the detected object 7 via anchor clamps 8 then.This test signal forms the output signal of this functional module by checking the functional module in the object 7.This output signal is opposite with test signal, via anchor clamps 8, wire harness 6, wiring conversion substrate 5, wire harness 9 and AD translation circuit 10, the robot calculator 2 of echo check device.In the signal detection step S15 of Fig. 2, will be taken into the processing inside of program from the signal of this AD translation circuit 10.Then, with the determining step S17 of standard value in carry out the comparison of output signal and standard value, whether carry out qualified determining step S18, carry out the judgement of OK (step S19) or NG (step S20).In addition, show on the display device 1 of general robot calculator 2 in Fig. 1 that according to the whether qualified judged result of checking for example be the treatment state that carry out the inside of testing fixtures such as the message of OK or NG or detected signal waveform, allow the people see easily from the outside.
Order in the generation phase of testing fixture of narration Figure 1 and Figure 2 below.The genesis sequence of testing fixture and program thereof generally generates the process flow diagram of wiring diagram, checks sequence of the design drawing of testing fixture, various translation circuit and wire harness and actual program that makes the computing machine flowchart etc. successively, constitute hardware and assemble according to these figure and wiring diagram, with the program robot calculator of packing into, constitute whole testing fixture like this.Then, be referred to as the operation of debugging.This debugging operation is that one side makes the testing fixture action, one side confirms whether the hardware of drawing and wiring diagram or formation does not have mistake in design or assembling, further whether do not have design mistake or code error in the also affirmation program, it is constantly revised when wrong having found.If debugging finishes, can confirm that the action of testing fixture is normal, then testing fixture is finally finished, and moves to production line etc. and locates operation then.
The most general method in this debugging operation is an executive routine step by step, whether correct whether the data of confirming each variable in the logic of program and the program successively correct, particularly in the DA of Fig. 2 shift step S14, variable in the program is carried out the DA conversion, utilize measuring equipment observation waveforms such as oscillograph or tester, confirm that whether it correctly arrive the pin of terminal anchor clamps 8 as signal, confirm that whether it equate with variable change in the original program.Equally, in AD shift step S15, the whether regulation variable in the correct read-in programme of signal that the pin at anchor clamps 8 utilizes measuring equipment observation is confirmed in the variation of observation variable.In this debugging operation, the signal waveform of for example supposing the DA conversion is not when the pin of anchor clamps 8 correctly observes, that then judges DA translation circuit 3, wire harness 4, wiring conversion substrate 5 or wire harness 6 somely has a design mistake assembly defect, not pin then to anchor clamps 8, but the signal of observing each location detection of wire harness, wiring conversion substrate or DA translation circuit go out with measuring equipment, determine error location, and it is made amendment.
In this case, the various figure such as wiring diagram of pie graph, inscape table and each inscape of data that program or program is relevant, testing fixture take the phenomenon of debugging operation.In order to know the position that to observe, perhaps in order to know the signal path that links to each other with the position of observation, the position that will link to each other with the next stage inscape according to the wiring diagram inspection of the inscape at this position, then according to pie graph, check the connection between these inscapes figure, above-mentioned such operation is repeated at the position that links to each other with the inscape of next stage again according to the wiring diagram inspection of next stage again, until till the position of target configuration key element.
For example, in the testing fixture of Fig. 1, when signal output waveform that obtains at No. 1 pin observing anchor clamps 8 or numerical value and the desirable signal output waveform of testing fixture developer or numerical value are inequality, debug operation according to order shown in Figure 4.In addition, in the following description, harness wiring figure between the DA transducer 3 of the testing fixture of Fig. 3 (a) presentation graphs 1 and the wiring conversion substrate 5, the wiring diagram of the wiring conversion substrate 5 of the testing fixture of Fig. 3 (b) presentation graphs 1, the wiring conversion substrate 5 of the testing fixture of Fig. 3 (c) presentation graphs 1 and the harness wiring figure between the anchor clamps 8, the wiring diagram of the anchor clamps 8 of the testing fixture of Fig. 3 (d) presentation graphs 1.
In Fig. 4, the debugging operation 21 of No. 1 pin 39 at first from the wiring diagram of anchor clamps 8 with reference to step S22.That is, take out wiring Figure 36 of the anchor clamps 8 of Fig. 3 (d) institute tool, checks the numbering of connector 37 of No. 1 pin 39 connections and the numbering of pin 38 thereof.Then, observe output signals (step S23) for the pin 38 of this connector 37 on the anchor clamps 8.Here, check the whether desirable signal of testing fixture developer (step S24) of output signal.If output signal is the desirable signal of testing fixture developer, then finish operation.Here, when output signal and the desirable signal of testing fixture developer are inequality,, confirm the wire harness 6 that is connected with anchor clamps 8 then with reference to the pie graph (step S25) of Fig. 1 of testing fixture, and with reference to the wiring Figure 41 (step S26) of the wire harness 6 shown in Fig. 3 (c).According to wiring Figure 41 of this wire harness 6, check with wire harness 6 that No. 1 pin 39 of anchor clamps 8 links to each other on the numbering of connector 45 and the numbering of pin 44, observe output signal (step S27) for it.Here, check whether output signal is the desirable signal of testing fixture developer (step S28), when output signal and the desirable signal of testing fixture developer are inequality, then with reference to the testing fixture pie graph (step S30) of Fig. 1, the wiring conversion substrate 5 that affirmation is connected with wire harness 6, and with reference to the wiring Figure 46 (step S31) shown in Fig. 3 (b).According to wiring Figure 46 of this wiring conversion substrate 5, check with wiring conversion substrate 5 that No. 1 pin 36 of anchor clamps 8 links to each other on connector 47 and 50 the numbering and the numbering of pin 48 and 51, observe output signal (step S32) for it.Here, observe desirable signal on the connector 47 of output signal path upstream side among this wiring Figure 46,, then be judged as this wiring conversion substrate 5 certain problems of existence if hypothesis does not observe desirable signal on the connector 50 of its downstream side.
In addition,, check the position of observation and the relation of program internal variable or program,, the hardware and the software of testing fixture are debugged operation by comparing with the actual observation result also with reference to program or the relevant data of program.Here, so-called program internal variable provides the variable to testing fixture able to programme, is the numbering that inputs or outputs that the user handles in program, or the register of numerical value such as stored count value or analog quantity or bit string.
Testing fixture for aforementioned patent document 1, if for example compare with above-mentioned Fig. 1, then robot calculator 2, produce test signal DA translation circuit 3, detect the AD translation circuit 10 of answer signal and situation about having under display device 1 constitute the inscape scope of testing fixture in the past.In addition, in the example of the wire harness debugging relevant, be design mistake and the assembly defect of checking wire harness itself with aforementioned patent document 2.
In the testing fixture for aforementioned patent document 1, as not comprising wire harness, wiring conversion substrate and anchor clamps in the inscape of testing fixture.Thereby in the debugging operation of reality, the problem of existence is the expense time and makes mistakes easily.Promptly, when debugging, in order to know the position that to observe, perhaps in order to know the signal path that links to each other of position with observation, the position that link to each other with the next stage inscape according to the wiring diagram inspection of the inscape at this position is followed according to pie graph, check the connection between these inscapes figure, above-mentioned such operation is repeated at the position that links to each other with the inscape of next stage again according to the wiring diagram inspection of next stage again, until till the position of target configuration key element.Utilize the signal path on the handwork tracking wiring diagram like this or also will relate to the operation that several figure come track signal path, just take very much the time and make mistakes easily.In addition, the mistake of making so also is the significantly reduced reason of debugging efficiency of operation that makes as target.
Generally, the figure of wire harness as described above, wiring conversion substrate and anchor clamps etc. is owing to be to utilize general mapping data input device to map, and therefore formation and the debug system with testing fixture is independently, manages respectively.Therefore, can not make these respectively information such as information of managing and pie graph, program internal variable, program, mark couple together and handle, identical with above-mentioned problem, in order to know and the relation at the position of observing, must carry out checking the operation of corresponding information with reference to each figure.Under the situation of this operation, also there is the problem of taking the time and makeing mistakes easily.Here, so-called mark is that program internal variable and input and output terminal that testing fixture has are numbered the arbitrary name of being given.
In addition, in the relevant example of the debugging of the wire harness shown in the aforementioned patent document 2, be that only relevant wire harness itself is checked design mistake and assembly defect.That is, be not to wire harness is debugged as the testing fixture of the part of inscape, because of rather than address the above problem.
In addition, as mentioned above, the scene that is provided with or the debugging that various figure must be taken testing fixture are on-the-spot when debugging, and the other problem of Cun Zaiing also has like this, the labour who needs a large amount of drawings of carrying does not perhaps disappear because of site environment or operator do not note waiting the information that causes, lost or stained etc.
The present invention provides and does not need each figure of above-mentioned such reference and following signal path successively and can know the bang path of essential signal and the testing fixture debug system of relevant information easily.
Example 1
Following with reference to description of drawings example of the present invention.Fig. 5 (a) is depicted as the formation block scheme of the testing fixture debug system of the invention process form 1.
Shown in Fig. 5 (a), the essential part 57 of the testing fixture debug system of this example checks that by the link information 59 between each inscape of the internal wiring signal 58 of inscapes such as wiring conversion substrate that constitutes testing fixture and anchor clamps, testing fixture and according to above-mentioned wiring information 58 and above-mentioned link information 59 indexing unit 60 of desirable signaling path constitutes.The results such as signaling path that output unit 61 outputs utilize indexing unit 60 to extract are made of display or printer etc.
If lifting the testing fixture of Fig. 1 is example, then above-mentioned wiring information 58 means it is to constitute the wiring conversion substrate 5 of this testing fixture and the internal wiring information of anchor clamps 8, stores the internal wiring information of the wiring conversion substrate 5 shown in Fig. 3 (b) and the internal wiring information of the anchor clamps 8 shown in Fig. 3 (d) etc.
If lifting the testing fixture of Fig. 1 is example, then above-mentioned link information 59 means be the DA translation circuit 3 that constitutes this testing fixture, wiring conversion substrate 5 with anchor clamps 8 between link information, store the DA translation circuit 3 shown in Fig. 3 (a) and connect up link information between the conversion substrate 5 and the link information between wiring conversion substrate 5 shown in Fig. 3 (c) and the anchor clamps 8.
When the testing fixture debug system that adopts this example is debugged operation, the commissioning staff utilizes indexing unit 60, according to wiring information 58 and link information 59 desirable terminals of retrieval or wiring etc., extract desirable signaling path, by implementing debugging like this.
Following process flow diagram according to Figure 10 illustrates the flow process example that the testing fixture debug system of utilizing this example is retrieved.At first, specify desirable terminal, then other terminal that 58 retrievals are connected with this terminal according to wiring information.That is, be the step 71 of utilizing desirable terminal to retrieve according to wiring information 58.Then, according to the information and the link information 59 of step 71 retrieval, the inscape that retrieval connects and connector numbering and pin numbering.That is, be the step 72 of the inscape that retrieval connects according to link information.Then, in step 73, judge whether the inscape of connection in the abovementioned steps 72,, then enter step 74,, then enter step 75, end retrieval like this if there is not the inscape of connection if there is the inscape that connects.In step 74, according to the information and the wiring information 58 of retrieval in the step 72, other terminal that retrieval is connected with this terminal.This is the step of retrieving according to result for retrieval and wiring information.Like this, repeat the retrieval of wiring information 58 and link information 59, when arriving the terminal that connects, arrive retrieval end step 75.
For example, as if desirable terminal in the process flow diagram of establishing Figure 10 is No. 6 pins 54 of the 1st connector 53 among Fig. 3 (a), then according to Fig. 3 (a) to resulting wiring information of Fig. 3 (d) and link information, the terminal that retrieves connection is No. 5 pins 56 of the 2nd connector 55.Then, to resulting wiring information of Fig. 3 (d) and link information, retrieving the terminal that is connected with No. 5 pins 56 of the 2nd connector 55 among Fig. 3 (a) is No. 5 pins 48 of the 1st connector 47 among Fig. 3 (b) according to the pie graph of Fig. 1 and Fig. 3 (a).Same as described above again, according to wiring information and link information, retrieving what be connected with No. 5 pins 48 of the 1st connector 47 among Fig. 3 (b) is No. 7 pins 51 of the 3rd connector 50 among Fig. 3 (b), again then according to wiring information and link information, retrieving what be connected with aforementioned pin 51 is No. 1 pin 43 of the 1st connector 42 among Fig. 3 (c).By repeating such operation, finally arrive No. 1 pin 39 among Fig. 3 (d), be confirmed to be terminal, retrieval finishes.As mentioned above, extract the mark bang path of No. 6 pins 54 beginning of the 1st connector 53 from desirable Fig. 3 (a), comprise No. 1 pin 38 of No. 1 pin 44, the 1st connector 37 among Fig. 3 (d) of No. 7 pins 43, the 2nd connector 45 among Fig. 3 (c) of No. 7 pins 51, the 1st connector 42 among Fig. 3 (c) of No. 5 pins 48, the 3rd connector 50 among Fig. 3 (b) of No. 5 pins 56, the 1st connector 47 among Fig. 3 (b) of the 2nd connector 55 among Fig. 3 (a) and No. 1 pin 39 among Fig. 3 (d).
In above-mentioned retrieval example, be No. 6 pins 54 that adopt the 1st connector 53 among Fig. 3 (a) as desirable terminal, but also can with any terminal in wiring information 58 and the link information 59 or arbitrarily wiring portion retrieve.
Be depicted as the output form of the signaling path of the testing fixture debug system retrieval that utilizes this example below.The key diagram that Fig. 8 (a) exports as complete list 77 for the signaling path that will utilize the retrieval of testing fixture debug system.In Fig. 8 (a), be to specify the examples of No. 5 pins of wiring conversion substrate the 1st connector, utilize complete list 77 usefulness of the signaling path of testing fixture debug system retrieval to represent the row 78 of the inscape of testing fixture, represent the row 79 that connector is numbered and represent that the row 80 of pin numbering represent as desirable terminal 76.
Fig. 9 (a)～Fig. 9 (d) is drawn as the key diagram of thick line output for the signaling path that will utilize the retrieval of testing fixture debug system.That is, to shown in Fig. 9 (d), the signaling path that will retrieve on wiring diagram is represented with the thick line 82,83,84,85,86,87,88,89,90,91,92,93 and 109 of connector, pin, wiring and connection as Fig. 9 (a).Its result can come clear and definite signaling path with the wiring and other the wiring difference of signaling path.
Below, illustrate that shown in Fig. 5 (a) wiring information 58 to the essential part 57 of testing fixture debug system has the input of wiring information and the system of conversion interface arrangement 62.Here, the input of so-called wiring information and conversion interface arrangement 62 are devices that wiring information 58 to the testing fixture debug system of this example was taken into, further was transformed to the data mode that this testing fixture debug system can handle.
Usually, wiring diagram is to utilize general mapping data input device to generate.Therefore, in this example, utilize the input media of above-mentioned wiring information to be taken into this testing fixture debug system the wiring information of utilizing such mapping data input device to generate.Meanwhile, the wiring information of input utilizes the conversion interface arrangement to be transformed to the data mode that this testing fixture debug system can be handled, as wiring information 58.
In addition, illustrate shown in Fig. 5 (a) as the replacement device of the input of above-mentioned wiring information and conversion interface arrangement 62 or selecting arrangement are had the testing fixture debug system of the direct input media 63 of wiring information.Here, the direct input media 63 of so-called wiring information is the mapping data input device that this testing fixture debug system is had.
That is, when testing fixture is developed, utilize the direct input media 63 of the wiring information of this testing fixture debug system, the inscape figure of testing fixtures such as generation wiring diagram.In this process, the data mode of the wiring information that can handle with this testing fixture debug system generates wiring information 58.
Example 2
In the invention process form 2, when in testing fixture, having the device that hardware expanding is used, to partly constitute the link information that relevant information is taken into example 1 with the hardware expanding of testing fixture, come the recall signal bang path in hardware components that its company is expanded is also contained in.
Example 2 of the present invention below is described with reference to the accompanying drawings.Fig. 5 (b) is depicted as the formation block scheme of the testing fixture debug system of the invention process form 2.Generally in exploitation during testing fixture, generate pie graph or generate the operation of the what is called configuration 64 that its inscape connects.Then, link information is mainly to utilize this configuration 64 and the information that obtains.In addition, when testing fixture has the device that hardware expanding is used, the hardware of expansion on testing fixture and information such as hardware terminal also utilize configuration 64 to obtain.This is to set up hardware information 65 among Fig. 5 (b).In this example, indexing unit 60 will be set up hardware information 65 and link information 59 additions, come the recall signal bang path according to this link information 59 and wiring information 58.
For example the following describes situation as shown in figure 11, the hardware expanding device of testing fixture is the notch 99,100,101 and 102 on the base plate 94, the hardware of expansion be on aforementioned notch 99,100,101 and 102, set up set up plate 98.In this case, the connector 96 that utilize that configuration 64 generates the kind of the notches numbering of the plate of setting up 98, the plate set up and function, is connected in the plate 98 set up with the wire harness of outside etc. and the information such as numbering of terminal 97 are set up hardware information 65.Link information 59 is taken into the above-mentioned hardware information 65 of setting up.By like this, in the signaling path that obtains by retrieval terminal and wiring according to wiring information 58 and link information 59, except the wiring and terminal of wire harness, wiring conversion substrate and anchor clamps, can also comprise the numbering of the notch of setting up plate 98 99 of expansion, the numbering of connector 96 and the numbering of the terminal on the connector 97 in addition.Its result when checking signaling path, can know the position of the notch 99 of hardware expanding, the numbering of connector 96 and the numbering of terminal 97 thereof easily.
Example 3
In example 3 of the present invention, be the link information of the input and output terminal of program internal variable and testing fixture can be included in the link information 59 of essential part 57 of testing fixture debug system to retrieve.
Example 3 of the present invention below is described with reference to the accompanying drawings.Fig. 5 (c) is depicted as the formation block scheme of the testing fixture debug system of the invention process form 3.Shown in Fig. 5 (c), when carrying out program editing 66, the program internal variable 65 that obtains using and the link information of the input and output terminal of testing fixture.For example when providing test signal to the inspection object, the program internal variable 68 of the value of this test signal of storage that uses in the program is actually the terminal numbering of the testing fixture of this test signal of output.The link information of the input and output terminal of this program internal variable 68 and testing fixture also is taken into the link information 59 of the essential part 57 of above-mentioned testing fixture debug system.
Its result, the link information of the input and output terminal of program internal variable and testing fixture is also contained in the link information 59 and retrieves, and obtains desirable signaling path.In this signaling path, also comprise the result that the link information according to said procedure internal variable 68 and the input and output terminal of testing fixture obtains, for example also can as Fig. 8 (b), the relation of the terminal on program internal variable 81 and the signaling path be represented as result for retrieval.
Example 4
In the example 4 of the present invention,, the routine package that utilizes program editing and generate can also be contained in the link information of testing fixture debug system and retrieve except the program internal variable of example 3.
Example 4 of the present invention below is described with reference to the accompanying drawings.Fig. 5 (d) is depicted as the formation block scheme of the testing fixture debug system of the invention process form 4.Shown in Fig. 5 (d), except program internal variable 68, the program 67 that also will utilize program editing 66 to generate is included in the link information 59 of essential part 57 of this testing fixture debug system.In this case, when implementing the retrieval of signaling path, can access for example such result for retrieval of Fig. 8 (b).Have again, under the situation of this embodiment, can also represent relation with program.For example, the expression of the display packing at position relevant with program internal variable 81 in the program and the difference of other information can being come.By like this, in the debugging operation of testing fixture, can know the relation of program and signaling path easily.
Example 5
In example 5 of the present invention, can with the corresponding label information of program internal variable as the replacement of program internal variable or append information, be taken into the link information of testing fixture debug system, retrieve.
Example 5 of the present invention below is described with reference to the accompanying drawings.Fig. 5 (e) is depicted as the formation block scheme of the testing fixture debug system of the invention process form 5.Generally, mark is at program editing 66 or generates when disposing 64 operation.The testing fixture developer logins serving as a mark for the meaning of this program internal variable 68 on the program.Label information 69 are expressions with the mark corresponding programs internal variable 68 that provides or with the information of the relation of the input and output terminal of testing fixture.
For example, serve as a mark and provide " analog output value " program internal variable 68.In this case, program internal variable 81 among replacement Fig. 8 (b) or the corresponding mark of demonstration together.The signal that its result, commissioning staff can analogize before actual measurement on the signaling path is the signal with what meaning.
Example 6
In example 6 of the present invention, it is characterized in that, be to have storage wire information 58 and link information 59 in the testing fixture debug system of above-mentioned example explanation and come device 57, the output of the indexing unit 60 of retrieving information bang path information information output apparatus 61 relevant and the communicator 104 that transmission information is used between above-mentioned 2 devices, obtain the result for retrieval of desired information and desirable signaling path in the on-site place of leave message with above-mentioned signaling path according to these information.
Followingly example 6 of the present invention is described with reference to Fig. 6 and Fig. 7.The formation of this example is except the formation of example 1～example 6, adds the device 103 of essential information such as storage wire information 58 and link information 59, the result's of expression retrieving information bang path etc. output unit 61 and transmission information is used between above-mentioned 2 devices communicator 104 and constitutes.
In concrete example shown in Figure 7, the memory storage 103 of the essential information of storage is a server 107, represents that the result's etc. of recall signal bang path output unit 61 is terminals 108, and communicator 104 is LAN105 and relay 106.
As mentioned above, according to example 6, the device of the signaling path by will exporting desirable wiring information and link information and retrieval, separate with the device of storage wire information and link information, can make the scene that is provided with or the on-the-spot above-mentioned output unit miniaturization of going of debugging of taking testing fixture, this point is resultful.Have again since with essential information stores in the place of leaving operating environment, therefore prevent from not note because of site environment or operator the beyond thought information disappearance that causes lost or stained on also be resultful.
Claims (6)
1. the debug system of a testing fixture of checking according to program is characterized in that,
Described testing fixture is made of robot calculator, display device, DA translation circuit, AD translation circuit, wire harness, wiring conversion substrate and anchor clamps,
The debug system of described testing fixture has:
Store the mutual link information of the internal wiring information of described wiring conversion substrate and described anchor clamps and described DA translation circuit, described wiring conversion substrate and described anchor clamps memory storage and
Come the indexing unit of recall signal bang path according to described internal wiring information and described link information,
In described indexing unit, by specifying any terminal or the wiring arbitrarily in described internal wiring information and the described link information, obtain desirable signaling path information,
The debug system of described testing fixture also have with the output unit of the relevant information of the signaling path output of retrieval and the described internal wiring information of transmission and described link information are used between described memory storage and described output unit communicator,
Leaving the result for retrieval that described internal wiring information and the on-site place of described link information obtain desirable described internal wiring information and described link information and desirable signaling path,
The debug system of described testing fixture also has the wiring information that is used for utilizing the mapping data input device to generate and inputs to the debug system of this testing fixture, is transformed to the input and the conversion interface arrangement of the wiring information of the data mode that the debug system of this testing fixture can handle simultaneously.
2. the debug system of a testing fixture of checking according to program is characterized in that,
Described testing fixture is made of robot calculator, display device, DA translation circuit, AD translation circuit, wire harness, wiring conversion substrate and anchor clamps,
The debug system of described testing fixture has:
Store the mutual link information of the internal wiring information of described wiring conversion substrate and described anchor clamps and described DA translation circuit, described wiring conversion substrate and described anchor clamps memory storage and
Come the indexing unit of recall signal bang path according to described internal wiring information and described link information,
In described indexing unit, by specifying any terminal or the wiring arbitrarily in described internal wiring information and the described link information, obtain desirable signaling path information,
The debug system of described testing fixture also have with the output unit of the relevant information of the signaling path output of retrieval and the described internal wiring information of transmission and described link information are used between described memory storage and described output unit communicator,
Leaving the result for retrieval that described internal wiring information and the on-site place of described link information obtain desirable described internal wiring information and described link information and desirable signaling path,
The debug system of described testing fixture also has the direct input media of wiring information,
During described testing fixture, utilize the direct input media of described wiring information in exploitation, in the process of the inscape figure that generates this testing fixture, the data mode of the wiring information that can handle with the debug system of this testing fixture generates internal wiring information.
3. the debug system of testing fixture as claimed in claim 1 or 2 is characterized in that,
When in testing fixture, having the device that hardware expanding is used, be taken into described link information, make the hardware components of expansion come the recall signal bang path in being included in partly constituting relevant information with the hardware expanding of testing fixture.
4. the debug system of testing fixture as claimed in claim 1 or 2 is characterized in that,
Have the program internal variable and with the link information of the input and output terminal of testing fixture, the link information of the input and output terminal of program internal variable and pick-up unit is included in the mutual link information of described DA translation circuit, described wiring conversion substrate and described anchor clamps comes the recall signal bang path.
5. the debug system of testing fixture as claimed in claim 1 or 2 is characterized in that,
Have and the corresponding label information of program internal variable, described label information is taken in the mutual link information of described DA translation circuit, described wiring conversion substrate and described anchor clamps comes the retrieving information bang path.
6. the debug system of testing fixture as claimed in claim 4 is characterized in that,
Have the program of utilizing program editing and generating, described routine package is contained in the mutual link information of described DA translation circuit, described wiring conversion substrate and described anchor clamps comes the recall signal bang path.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003310892 | 2003-09-03 | ||
| JP2003310892A JP2005157409A (en) | 2003-09-03 | 2003-09-03 | Inspection device debugging system |
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| Publication Number | Publication Date |
|---|---|
| CN1591031A CN1591031A (en) | 2005-03-09 |
| CN100589082C true CN100589082C (en) | 2010-02-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200410076920A Expired - Fee Related CN100589082C (en) | 2003-09-03 | 2004-09-03 | The testing fixture debug system |
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|---|---|
| JP (1) | JP2005157409A (en) |
| KR (2) | KR20050025278A (en) |
| CN (1) | CN100589082C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1342281A (en) * | 1999-12-30 | 2002-03-27 | 索尼公司 | Diagnosis system, diagnosis apparatus and diagnosis method |
| CN1274889C (en) * | 2000-05-22 | 2006-09-13 | 齐默股份有限公司 | Method for extruding continuous shaped body |
-
2003
- 2003-09-03 JP JP2003310892A patent/JP2005157409A/en active Pending
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2004
- 2004-08-25 KR KR1020040066980A patent/KR20050025278A/en active Search and Examination
- 2004-09-03 CN CN200410076920A patent/CN100589082C/en not_active Expired - Fee Related
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1342281A (en) * | 1999-12-30 | 2002-03-27 | 索尼公司 | Diagnosis system, diagnosis apparatus and diagnosis method |
| CN1274889C (en) * | 2000-05-22 | 2006-09-13 | 齐默股份有限公司 | Method for extruding continuous shaped body |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060108257A (en) | 2006-10-17 |
| KR20050025278A (en) | 2005-03-14 |
| CN1591031A (en) | 2005-03-09 |
| JP2005157409A (en) | 2005-06-16 |
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