CN100583459C - Pixel structure and its thin film transistor - Google Patents
Pixel structure and its thin film transistor Download PDFInfo
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- CN100583459C CN100583459C CN200810161039A CN200810161039A CN100583459C CN 100583459 C CN100583459 C CN 100583459C CN 200810161039 A CN200810161039 A CN 200810161039A CN 200810161039 A CN200810161039 A CN 200810161039A CN 100583459 C CN100583459 C CN 100583459C
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Abstract
The invention discloses a pixel structure and a thin-film transistor. A grid connecting scanning line of the thin-film transistor is arranged at one surface of an insulating layer, and a semiconductor layer, a source electrode and a drain electrode are arranged at the other surface of the insulating layer. The source electrode is connected with a data line and the semiconductor layer. The first branch of the drain electrode is connected with the semiconductor layer and is partially aligned and superposed with the grid so as to induce parasitic capacitance. The second branch and the first branch of the drain electrode extend in the same direction and perpendicularly go across from above the scanning line. The second branch is partially aligned and superposed with the scanning line so as to induce a first compensation capacitance. A compensation electrode is connected with the second branch and is partially vertically arranged above the scanning line so as to induce a second compensation capacitance. The width of the line of compensation electrode is the total of the widths of the lines of the first branch and the second branch, so that the sum of the parasitic capacitance, the first compensation capacitance and the second compensation capacitance is constant. The invention provides the pixel structure and the thin-film transistor and can effectively solve the problem of uneven feed-through voltage due to displacement deviation of the two metal layers.
Description
Technical field
The invention relates to a kind of thin-film transistor, and particularly relevant for the layout of thin film transistor (TFT) array.
Background technology
There is many flat-panel screens (Flat Panel Display) technology to be developed in succession in recent years, as LCD (Liquid Crystal Display; LCD).Because advantages such as LCD have compact, low power consumption, radiationless danger, and flat square shows and image stabilization is not glimmered, become the main flow of following display gradually.
Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) belong to a kind of of flat-panel screens, its panel can be considered two sheet glass substrate sandwich one deck liquid crystal, the glass substrate on upper strata is and the colored filter combination that the glass substrate of lower floor then has thin film transistor (TFT) array to inlay thereon.
See also Figure 1A, it is depicted as a conventional thin film transistor array approximate vertical view.Thin film transistor (TFT) array has dot structure 10, and it mainly is made up of a plurality of pixel cells 12 that are arranged in array.A thin-film transistor 100, a storage capacitors 160 and pixel electrode 180 are arranged in each pixel cell 12.Also include scan line 140 in the dot structure 10 and be connected each thin-film transistor 100 with data wire 150, to provide thin-film transistor 100 suitable operation transformation.
As everyone knows, the grid 110 of thin-film transistor 100 and drain the zone that overlaps each other is arranged between 120, and then bring out gate-to-drain parasitic capacitance 170 (gate drain parasitic capacitance, Cgd).Gate-to-drain parasitic capacitance 170 can exert an influence for the electric field of liquid crystal capacitance.Particularly, coupling effect can take place with gate-to-drain parasitic capacitance 170 in liquid crystal capacitance, make the voltage that is kept on the liquid crystal capacitance be subjected to the change of data wire 150 power on signal and change that departed from predetermined value, the voltage that wherein departs from is called feed-trough voltage (feed-through voltage).
On the other hand, in the technology of present thin film transistor (TFT) array, the offset deviation amount that board moves can cause the position difference of each element of thin-film transistor 100, causes grid 110 different with the overlapping area of drain electrode 120.
Please also refer to Figure 1A and Figure 1B, Figure 1B illustrates as the shown conventional thin film transistor array of Figure 1A approximate vertical view.Because when the photoetching carried out of people having a common goal's photomask and etch process, the process shifts that fabrication error caused can not found through comparing two figure, grid 110 is different with the relative position of data wire 150 with respect to drain electrode 120, source electrode 130 with scan line 140.When the overlapping area of grid 110 and drain electrode 120 not simultaneously, can cause gate-to-drain parasitic capacitance 170 differences, cause the feed-trough voltage difference in each pixel cell 12.
In view of this, need a kind of new thin film transistor (TFT) array and layout thereof, can effectively solve the uneven problem of feed-trough voltage that causes because of two metal level offset deviations.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of dot structure and thin-film transistor thereof exactly, in order to solve the inconsistent problem of feed-trough voltage that causes each thin-film transistor because of fabrication error.
Have thin-film transistor, scan line and data wire in the dot structure.Data wire and scan line are staggered.Thin-film transistor comprises a grid, a drain electrode and an one source pole at least, and wherein grid electrically connects scan line, and source electrode electrically connects data wire, and drain electrode electrically connects pixel electrode.
Grid is in abutting connection with an insulating barrier and be positioned at a surface of insulating barrier.Semi-conductor layer is positioned at another surface of insulating barrier.Source electrode is positioned at another surface and the coupling part semiconductor layer of insulating barrier.
Drain electrode is positioned at another surface of insulating barrier.Wherein, drain electrode has that one first side is propped up, one second side is propped up and a compensating electrode.First side is propped up the coupling part semiconductor layer, and part first side is propped up the overlapping grid of alignment and brought out parasitic capacitance.Second side is propped up to prop up with first side and is extended same direction, and vertically crosses the scan line top.Part second side is propped up alignment overlapping scan line and is brought out first building-out capacitor.Compensating electrode connects second side and props up, and the part compensating electrode vertically is positioned at the scan line top and brings out second building-out capacitor.The live width that the live width that the live width of compensating electrode is propped up for this first side and this second side are propped up and.
Because first side is propped up with the second side Zhi Jun and extended same direction, therefore when skew took place, first side was propped up with second side and is propped up and can be offset along equidirectional.In other words, when skew propped up the side of winning to dwindle with the gate overlap area, second side was propped up with the scan line overlapping area and is also dwindled synchronously.Thus, the parasitic capacitance and first building-out capacitor together diminish.
On the other hand, compensating electrode is to connect second side to prop up.In afore-mentioned, prop up when dwindling when second side with the scan line overlapping area, compensating electrode can increase compensating electrode and the overlapping area of scan line along with the second side Zhi Yidong, makes second building-out capacitor increase.
Because the live width that the live width that the live width of compensating electrode is propped up for this first side and this second side are propped up and.So first side is propped up the overlapping area of being dwindled with grid and second side and is propped up the overlapping area of being dwindled with scan line and can be equal to the overlapping area that compensating electrode and scan line increase.Therefore, the amount that increased of second building-out capacitor can equal the amount that parasitic capacitance and first building-out capacitor are reduced.
Thus, parasitic capacitance, first building-out capacitor and second building-out capacitor and can keep constantly, and then make feed-trough voltage constant, be not subjected to process shifts and influence.On the other hand, see through second side and prop up setting with compensating electrode, can make each thin-film transistor in the thin film transistor (TFT) array all have identical and constant parasitic capacitance, first building-out capacitor and second building-out capacitor and.In other words, each thin-film transistor all has identical feed-trough voltage in the thin film transistor (TFT) array.
Description of drawings
For above-mentioned purpose of the present invention, feature, advantage and embodiment can be become apparent, being described in detail as follows of accompanying drawing:
Figure 1A illustrates the vertical view according to known thin film transistor (TFT) array.
Figure 1B illustrates the vertical view according to the shown thin film transistor (TFT) array of Figure 1A, represents the situation after the two metal level translations.
Fig. 2 A illustrates the vertical view according to the thin film transistor (TFT) array of one of the present invention embodiment.
Fig. 2 B illustrates according to the amplification profile of the shown thin film transistor (TFT) array of Fig. 2 A along A-A ' line.
Fig. 2 C illustrates according to the amplification profile of the shown thin film transistor (TFT) array of Fig. 2 A along B-B ' line.
Fig. 2 D illustrates the vertical view according to the shown thin film transistor (TFT) array of Fig. 2 A, represents the situation after the two metal level translations.
Fig. 3 A illustrates the vertical view according to the shown thin-film transistor of Fig. 2 A.
Fig. 3 B illustrates the vertical view according to the shown thin-film transistor of Fig. 2 D.
Fig. 4 illustrates the vertical view according to the thin-film transistor of one embodiment of the invention
And the description of reference numerals in the above-mentioned accompanying drawing is as follows:
10: thin film transistor (TFT) array
110: grid
114: the second limits
Side was propped up in 122: the first
126: compensating electrode
130: source electrode
142: the three limits
150: data wire
170: parasitic capacitance
174: the second building-out capacitors
W2: live width
100: thin-film transistor
112: the first limits
120: drain electrode
Side was propped up in 124: the second
Side was propped up in 128: the three
140: scan line
144: the four limits
160: storage capacitors
172: the first building-out capacitors
W1: live width
W3: live width
Embodiment
Please refer to Fig. 2 A, the vertical view shown in it according to the dot structure 10 of one embodiment of the invention.Dot structure 10 mainly has several thin-film transistors that is arranged in array 100.Each thin-film transistor 100 has grid 110, drain electrode 120 and source electrode 130, and wherein grid 110 electrically connects scan line 140, and source electrode 130 electrically connects data wire 150.
Please also refer to Fig. 2 A to Fig. 2 C.Fig. 2 B illustrates the amplification profile according to the AA ' line shown in Fig. 2 A, and Fig. 2 C illustrates the amplification profile according to the BB ' line shown in Fig. 2 A.
With the bottom-gate structure is example, and grid 110 and scan line 140 all are configured on the substrate 200.One layer insulating 210 is in abutting connection with cover gate 110 and scan line 140.Then on insulating barrier 210, cover one semiconductor layer 220.Form drain electrode 120 and source electrode 130 on the semiconductor layer 220 again.Wherein, the semiconductor layer 220 of source electrode 130 meeting coupling parts.Hence one can see that, and grid 110 is surfaces that are positioned at insulating barrier 210, semiconductor layer 220, source electrode 130 and 120 another surfaces that all are positioned at insulating barrier 210 that drain.Similarly, the present invention also is applicable to the top grid structure.
Second side is propped up 124 and is extended to scan line 140 tops, and vertically crosses scan line 140 tops.Thus, second side of part is propped up 124 meeting alignment overlapping scan lines 140, and then brings out first building-out capacitor 172.In an embodiment of the present invention, second side prop up 124 with first side to prop up 122 bearing of trend identical.
Compensating electrode 126 connects second side and props up 124.Particularly, compensating electrode 126 is to be connected second side to prop up an end of 124.Compensating electrode 126 also extends to the top of scan line 140, makes the compensating electrode 126 of part vertically be positioned at scan line 140 tops, and then brings out second building-out capacitor 174.
Please also refer to Fig. 2 A and Fig. 2 D.Fig. 2 D illustrates the vertical view according to the shown dot structure 10 of Fig. 2 A, the situation of expression after the offset of grid 110 and drain electrode 120.Compared to Fig. 2 A, drain electrode 120, makes the side of winning prop up 122 and dwindles with the overlapping area of grid 110, and then make parasitic capacitance 170 reduce with respect to grid 110 skew along direction 230 among Fig. 2 D.
Because first side is propped up 122 and second side and is propped up 124 and all extend same direction.Therefore, in Fig. 2 D, first side prop up 122 and second side prop up 124 can be offset along equidirectional.Second side prop up 124 with scan line 140 overlapping areas also along with dwindling, the building-out capacitor 172 of winning is reduced.That is to say that the parasitic capacitance 170 and first building-out capacitor 172 together diminish.
On the other hand, compensating electrode 126 is connected second side and props up an end of 124.In Fig. 2 D, to prop up 122 and second side when first side and prop up 124 when direction 230 moves, second side is propped up 124 and can be driven compensating electrodes 126 and move, and makes compensating electrode 126 and scan line 140 overlapping areas increase, and then increases by second building-out capacitor 174.
Please also refer to Fig. 3 A and Fig. 3 B.Fig. 3 A illustrates the amplification plan view according to the shown thin-film transistor 100 of Fig. 2 A.Fig. 3 B illustrates the amplification plan view according to the shown thin-film transistor 100 of Fig. 2 D.
As previously mentioned, prop up 122, second side when first side and prop up 124 and compensating electrode 126 during along direction 230 skew, because first side prop up 122 and the overlapping area of grid 110 and second side prop up 124 and dwindle with scan line 140 overlapping areas, make the parasitic capacitance 170 and first building-out capacitor 172 diminish.And compensating electrode 126 increases with scan line 140 overlapping areas, makes second building-out capacitor 174 increase.
The capacitance that reduces in order to make equals the capacitance that increased, in an embodiment of the present invention, the live width W3 of compensating electrode 126 be first side prop up 122 live width W1 and second side prop up 124 live width W2's and.Particularly because first side prop up 122, second side prop up 124 identical with the displacement of compensating electrode 126 skew, and the live width W3 of compensating electrode 126 be first side prop up 122 live width W1 and second side prop up 124 live width W2's and.So first side is propped up the size of 122 overlapping areas of being dwindled with grid 110 and added that second side props up the size of 124 overlapping areas of being dwindled with scan line 140, can be equal to the size of the overlapping area that compensating electrode 126 and scan line 140 increased.Hence one can see that, and the amount that second building-out capacitor 174 is increased can equal the amount that parasitic capacitance 170 and first building-out capacitor 172 are reduced.Therefore, parasitic capacitance 170, first building-out capacitor 172 and second building-out capacitor 174 and can keep constant.
In an embodiment of the present invention, further limiting first side props up 122 live width W1 and equals second side and prop up 124 live width W2.In other words, the live width W3 of compensating electrode 126 will equal the twice that first side is propped up 122 live width W1, also equal the twice that second side is propped up 124 live width W2.
Those of ordinary skill in the technology of the present invention field knows that all drain electrode 120 can connect a storage capacitors 160.In an embodiment of the present invention, drain electrode 120 has more one the 3rd side and props up 128 and connect first side and prop up 122 an end and storage capacitors 160.The 3rd side prop up 128 and grid 110 be positioned at the same side of scan line 140.Particularly, the 3rd side prop up 128 be positioned at first limit 112 of grid 110 and scan line 140 the 3rd limit 142 outside.The 3rd side is propped up 128 out of plumb and is crossed grid 110, and also out of plumb is crossed scan line 140.In other words, the 3rd side is propped up 128 and can not brought out generation electric capacity with grid 110 or scan line 140.
In an embodiment of the present invention, second side is propped up an end of 124 and is directly connected to storage capacitors 160, the second sides and props up 124 the other end and then vertically cross scan line 140.
Please refer to Fig. 4, it illustrates a kind of according to another embodiment of the present invention amplification plan view of thin-film transistor 100.In an embodiment of the present invention, it is to be connected the 3rd side to prop up on 128 that second side is propped up an end of 124, and the other end is then vertically crossed scan line 140.
By above-mentioned each embodiment as can be known, prop up 122, second side and prop up 124 and compensating electrode 126 by be provided with first side at thin-film transistor 100, the summation of bringing out parasitic capacitance 170, first building-out capacitor 172 and second building-out capacitor 174 of generation is constant, and then make feed-trough voltage constant, be not subjected to pattern shift and influence.
On the other hand and since in the dot structure 10 parasitic capacitance 170, first building-out capacitor 172 and second building-out capacitor 174 of each thin-film transistor 100 and be constant and even, so the feed-trough voltage of each thin-film transistor 100 will be identical and even.Thus, it is inhomogeneous and the problem of the brightness irregularities that causes can also be saved the formality that process aspect is adjusted feed-trough voltage one by one not only to have removed feed-trough voltage from, simplifies technological process.
Though the present invention with a plurality of embodiment openly as above; yet it is not to be used for limiting the present invention; any those of ordinary skills; without departing from the spirit and scope of the present invention; can make various changes and retouching, so protection scope of the present invention should be looked the scope of being protected with claims and is as the criterion.
Claims (9)
1. thin-film transistor comprises at least:
One grid electrically connects the one scan line;
One insulating barrier is adjacent to this grid, and this grid is positioned at a surface of this insulating barrier;
Semi-conductor layer is positioned at another surface of this insulating barrier;
One source pole is positioned at another surface of this insulating barrier, and this semiconductor layer of coupling part, and this source electrode electrically connects a data wire; And
One drains, and is positioned at another surface of this insulating barrier, comprises:
One first side is propped up, this semiconductor layer of coupling part, and this first side of part is propped up overlapping this grid of alignment and is brought out a parasitic capacitance;
One second side is propped up, and props up with this first side and extends same direction, and vertically cross this scan line top, and wherein this second side of part is propped up overlapping this scan line of alignment and brought out one first building-out capacitor; And
One compensating electrode, be arranged at the end that this second side is propped up, connect this second side and prop up, this compensating electrode of part vertically is positioned at this scan line top and brings out one second building-out capacitor, the live width that the live width that the live width of this compensating electrode is propped up for this first side and this second side are propped up and
Wherein this scan line has relative to each other one the 3rd limit and one the 4th limit, the 3rd limit that this second side Zhi Chuizhi crosses this scan line, and this compensating electrode is vertically crossed the 4th limit of this scan line.
2. thin-film transistor as claimed in claim 1, wherein this first side live width of propping up equals the live width that this second side is propped up.
3. thin-film transistor as claimed in claim 1, wherein this first side Zhi Chuizhi crosses one first limit of this grid.
4. thin-film transistor as claimed in claim 1, wherein one second limit of this grid connects the 3rd limit of this scan line, and this second limit and this first limit are a pair of opposed side edges of this grid.
5. thin-film transistor as claimed in claim 1, wherein this drain electrode more comprises one the 3rd side and props up and connect an end and the storage capacitors that this first side is propped up, and does not cross this grid.
6. thin-film transistor as claimed in claim 5, wherein the 3rd side is propped up the same side that all is positioned at this scan line with this grid.
7. thin-film transistor as claimed in claim 5, wherein the other end that props up of this second side connects the 3rd side and props up.
8. thin-film transistor as claimed in claim 1, wherein the other end that props up of this second side connects a storage capacitors.
9. dot structure comprises at least:
The one scan line;
One data wire, staggered with this scan line;
One grid electrically connects this scan line;
One insulating barrier is adjacent to this grid, and this grid is positioned at a surface of this insulating barrier;
Semi-conductor layer is positioned at another surface of this insulating barrier;
One source pole is positioned at another surface of this insulating barrier, and this semiconductor layer of coupling part, and this source electrode electrically connects this data wire; And
One drains, and is positioned at another surface of this insulating barrier, and this drain electrode comprises:
One first side is propped up, this semiconductor layer of coupling part, and this first side of part is propped up overlapping this grid of alignment and is brought out a parasitic capacitance;
One second side is propped up, and props up with this first side and extends same direction, and vertically cross this scan line top, and wherein this second side of part is propped up overlapping this scan line of alignment and brought out one first building-out capacitor; And
One compensating electrode, be arranged at the end that this second side is propped up, connect this second side and prop up, this compensating electrode of part vertically is positioned at this scan line top and brings out one second building-out capacitor, the live width that the live width that the live width of this compensating electrode is propped up for this first side and this second side are propped up with; And
One pixel electrode electrically connects this drain electrode,
Wherein this scan line has relative to each other one the 3rd limit and one the 4th limit, the 3rd limit that this second side Zhi Chuizhi crosses this scan line, and this compensating electrode is vertically crossed the 4th limit of this scan line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810161039A CN100583459C (en) | 2008-09-24 | 2008-09-24 | Pixel structure and its thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810161039A CN100583459C (en) | 2008-09-24 | 2008-09-24 | Pixel structure and its thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101359692A CN101359692A (en) | 2009-02-04 |
| CN100583459C true CN100583459C (en) | 2010-01-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200810161039A Expired - Fee Related CN100583459C (en) | 2008-09-24 | 2008-09-24 | Pixel structure and its thin film transistor |
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Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101614923B (en) * | 2009-08-04 | 2011-02-16 | 华映光电股份有限公司 | Pixel set |
| CN101673736B (en) * | 2009-09-25 | 2012-11-14 | 上海宏力半导体制造有限公司 | Method for compensating voltage modulation effect of capacitor |
| CN101738805B (en) * | 2009-12-03 | 2011-11-16 | 深超光电（深圳）有限公司 | Pixel structure |
| US7932519B1 (en) | 2009-12-28 | 2011-04-26 | Century Display(Shenzhen)Co.,Ltd. | Pixel structure |
| CN101750826B (en) * | 2009-12-28 | 2011-09-14 | 深超光电（深圳）有限公司 | Pixel structure |
| KR20230155614A (en) | 2010-02-26 | 2023-11-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Liquid crystal display device |
| CN101901802B (en) * | 2010-08-12 | 2012-11-07 | 友达光电股份有限公司 | Active component array substrate |
| TWI415100B (en) * | 2010-12-30 | 2013-11-11 | Au Optronics Corp | Lcd panel for compensating the feed-through voltage |
| KR102097024B1 (en) * | 2013-01-04 | 2020-04-06 | 삼성디스플레이 주식회사 | Thin film transistor array panel |
| CN103413834B (en) * | 2013-07-25 | 2016-01-20 | 北京京东方光电科技有限公司 | A kind of thin-film transistor and preparation method thereof, array base palte and display unit |
| KR102396288B1 (en) | 2014-10-27 | 2022-05-10 | 삼성디스플레이 주식회사 | Organic light emitting diode display device |
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2008
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