CN100583294C - Sensitive amplifier used for EEPROM and read circuit constituted of the same - Google Patents

Abstract

The invention discloses a sensitive amplifier for an EEPROM and a read circuit consisting of the sensitive amplifier. The sensitive amplifier for the EEPROM provided by the invention comprises a charge control circuit, a detection circuit and an output maintaining and shaping circuit, wherein, the charge control circuit consists of two same charge control sub-circuits; the detection circuit has a XNOR gate; the output maintaining and shaping circuit maintains the output of the detection circuit and shapes the output into a standard digital level. The read circuit formed by the sensitive amplifier comprises a first memory module and a second memory module which are completely symmetrical, two bit lines of each sensitive amplifier are respectively switched to corresponding bit lines of the first memory module and the second memory module. The sensitive amplifier has a circuit with simple structure, small occupied area, high read speed, low dynamic power, wide range of operation voltage and almost-zero static power and does not need a biasing circuit; the read circuit formed by the sensitive amplifier has the characteristics of anti-degradation of the properties of elements and stable performance.

Description

The sense amplifier of a kind of EEPROM of being used for reaches by its reading circuit that constitutes

Technical field

The invention belongs to the nonvolatile memory technology field, the sense amplifier that is specifically related to a kind of EEPROM of being used for reaches by its reading circuit that constitutes, and is particularly suitable for using in built-in EEPROM.

Background technology

Eeprom memory can be rewritten memory contents at any time owing to both have RAM, has ROM long-term characteristics that keep memory contents under powering-off state again, therefore is used widely.Particularly under the situation of SoC (System on Chip) widespread use at present, EEPROM realizes the online configurable characteristic of system as the in-line memory store configuration information, has widely to use.

Whole EEPROM is made of storage array (memory array) and peripheral circuit two parts, and peripheral circuit is made up of column decoder (column decoder), row decoding (row decoder), sense amplifier (senseamplifier), high pressure generation (high voltage generator) and logic control (control logic), data latching circuit such as (data latch).

When EEPROM carried out read operation, the main power consumption of chip derived from sense amplifier, and was proportional to the bit wide of EEPROM, i.e. the number of sense amplifier.Therefore in the application of low-power consumption, need reduce the power consumption of sense amplifier as much as possible, reduce the purpose that whole EEPROM reads power consumption thereby reach.

Along with the raising of present SoC working frequency of chip, the built-in EEPROM that also needs to have high reading speed adapts with it, otherwise EEPROM may become whole SoC bottleneck of performance.

Summary of the invention

The object of the present invention is to provide the sense amplifier of a kind of EEPROM of being used for, this sensitive amplifier circuit is simple in structure, does not need biasing circuit, and area occupied is little, and reading speed is fast, and dynamic power consumption is low, and quiescent dissipation is almost 0; Operating voltage range is big; The present invention also provides the reading circuit that is made of it, has anti-device property and degenerates the characteristics of stable performance.

The sense amplifier that is used for EEPROM provided by the invention is characterized in that: it comprises charging control circuit, testing circuit and maintenance shaping output circuit;

Charging control circuit is used to control the charging and the bleed off of pairs of bit line electric capacity, and it is made of two identical charging control electronic circuits, and two charging control electronic circuits are controlled by the charging control end, and respectively two bit lines are discharged and recharged;

Testing circuit is used to detect the difference in above-mentioned two bit line duration of charging, be one with or door, the voltage of two bit lines as with or the input of door; Its output is connected to the grid that keeps PMOS pipe P9 in the shaping output circuit;

Keep the shaping output circuit to comprise first, second PMOS pipe P9, P10, first, second NMOS pipe N9, N10 and capacitor C 1; The grid of the one PMOS pipe P9 connects the output terminal of testing circuit, and the grid of NMOS pipe N9 connects the charging control end, and its public drain electrode connects the top crown of capacitor C 1; Capacitor C 1 is connected into capacitive form by the NMOS pipe and constitutes, and top crown is the grid of NMOS pipe, is connected with the input of the public drain electrode of PMOS pipe P9 and NMOS pipe N9 and subordinate phase inverter, and bottom crown is connected with ground; The 2nd PMOS pipe P10 and the 2nd NMOS pipe N10 form inverter structure, and its public grid is as the top crown of input termination capacitor C 1, and its public drain electrode is as the output terminal of sense amplifier.

The reading circuit that constitutes by above-mentioned sense amplifier, it is characterized in that: it comprises K sense amplifier and first, second memory module, 1≤K≤64 wherein, two bit lines of each sense amplifier are received respectively on the corresponding bit line of first, second memory module, the control-grid voltage input end of first, second memory module, its common source end and each selecting side correspondence respectively link together, wherein the common source end is connected with ground by the 3rd NMOS pipe N11 that is controlled by the control end that charges, and the word line of first, second storage block is independently control separately.

Sense amplifier of the present invention use with or the door mode of carrying out voltage detecting judge storage tube institute canned data, comparing with traditional sense amplifier does not need biasing circuit, can adopt charging control circuit and same or door formation core circuit flexibly, charging control circuit is finished the pre-charge process of pairs of bit line, by with or the door as testing circuit, structure is very simple.Charging control circuit discharges to big capacitive node when idle condition, and the interference electric charge of having avoided unsettled node to exist in the time of the starting condition unanimity that guarantees at every turn to read has guaranteed the stability of read output signal; Because voltage detecting circuit adopts the form of CMOS gate circuit to carry out, therefore possessed the extremely low advantage of CMOS gate circuit quiescent dissipation; The testing circuit of this sense amplifier just detects when the bit line of charging circuit begins precharge, and only need wait until voltage on the bit line rise to or the turnover level of door after, just can output to the next stage circuit to testing result, be that charging circuit and testing circuit are almost worked simultaneously, so realized the target of reading fast.In sum, the sense amplifier of this new structure utilize cell stores information be 1 be the different principle that 0 o'clock bit line drives the total capacitance size, about passing through again two bit lines to about the difference in two memory module duration of charging, and this species diversity causes in the sense amplifier spy to put what of quantity of electric charge accumulation on the transistor capacitance, decide sense amplifier output high level or low level, thereby realized reading fast smoothly of storage data.

The reading circuit that is made of above-mentioned sense amplifier has anti-device property degeneration, the characteristics of stable performance.

Description of drawings

Fig. 1 is the structural representation of sense amplifier of the present invention.

Fig. 2 is an example of sense amplifier of the present invention.

Fig. 3 is the structural representation of half of storage unit tissue.

Fig. 4 is the structural representation of the reading circuit that is made of sense amplifier.

Embodiment

The present invention is further detailed explanation below in conjunction with accompanying drawing and example.

As shown in Figure 1, sense amplifier provided by the invention comprises charging control circuit 1, testing circuit 2 and keeps shaping output circuit 3.

Charging control circuit 1 is used to control the charging and the bleed off of pairs of bit line electric capacity, and charging control circuit 1 is made of two identical charging control electronic circuits 11,12, respectively two bit lines is charged.In idle condition, the electric charge on the charging control circuit pairs of bit line carries out bleed off, makes the voltage on the bit line keep original state; In the time of in working order, be controlled by the control signal pairs of bit line and charge.Charging control circuit can have flexile implementation, the single-stage phase inverter is the simplest structure, also can use the cascade of 2n+1 (n is not less than 0 integer) grade of phase inverter of amplifying step by step to realize, can also adopt controlled current source to realize discharging and recharging of constant current for increasing driving force.

Testing circuit 2 is used to detect the difference in both sides bit line duration of charging, and it is a same or door.With or door also flexible implementation can be arranged, can adopt complementary cmos on the logic style, have than logic (pseudo-NMOS), DCVSL, transfer tube logic and dynamic CMOS etc., can adopt on the logical organization L=AB+AB, $L=\stackrel{\‾}{\stackrel{\‾}{\mathrm{AB}}\·\stackrel{\‾}{\stackrel{\‾}{A}\stackrel{\‾}{B}}},$ $L=\stackrel{\‾}{\stackrel{\‾}{A+B}+\mathrm{AB}}$ Deng.

Keep shaping output circuit 3 to be used for sense data is kept, and, export to subordinate's digital circuit and use its digital level that is shaped as standard.When EN is high level, and the grid of PMOS pipe P9 is high level, and to ground, so the top crown voltage of C1 is low level (0V) to the electric charge on the C1 by NMOS pipe N9 pipe bleed off, through the anti-phase back of phase inverter output terminal OUT output high level; When EN is low level, NMOS pipe N9 closes, grid input low level pulse in short-term as PMOS pipe P9, PMOS pipe P9 opens, by it capacitor C 1 is charged, when pulses low time during long enough, C1 be charged to high level (near or equal VCC), through the anti-phase back of phase inverter output low level (0V), compole in short-term when pulses low, C1 can not be charged to high level and keep low level (near or equal 0V), through the anti-phase back of phase inverter output terminal OUT output high level (VCC); At this moment, be low level as long as guarantee EN, then NMOS pipe N9 closes, after PMOS pipe P9 grid came back to high level, PMOS pipe P9 closed, because charge stored does not have the loop of charging and discharging on the capacitor C 1, therefore C1 top crown voltage remains unchanged, and the data of reading have obtained maintenance.

Be example with the simplest single-stage inverter structure below, the concrete structure of charging control circuit 1 is described.

Charging control circuit comprises PMOS pipe P1, P2 and NMOS pipe N1, N2; PMOS pipe P1 and NMOS pipe N1 form inverter structure, and its public grid is as charging control end EN, and its public drain electrode links to each other with the bit line BLR of the second memory module RB as the first charging output terminal; P2, N2 adopt same connected mode, and its public drain electrode links to each other with the bit line BLL of the first memory module LB as the second charging output terminal; When EN was high level, PMOS pipe P1, P2 closed, and NMOS pipe N1, N2 open, and the bit line BLL of first, second memory module LB, RB and the current potential of BLR all are pulled to low level.The bit line BLL of first, second memory module LB, RB and BLR are as the output of charging control circuit, and output signal enters the testing circuit of next stage.When EN was low level, two charging control circuits charged to bit line BLL and the BLR of first, second memory module LB, RB respectively simultaneously by two PMOS pipe P2 and P1.

Below adopting complementary cmos logic style, $L=\stackrel{\‾}{\stackrel{\‾}{A+B}+\mathrm{AB}}$ Same or the door of logical organization is an example, and the concrete structure of testing circuit 2 is described.

Testing circuit comprises PMOS pipe P3, P4, P5, P6, P7, P8 and NMOS pipe N3, N4, N5, N6, N7, N8.PMOS pipe P3, P4 and NMOS pipe N3, N4 form the rejection gate structure; It is 1-2 AND structure that PMOS pipe P5, P6, P7 and NMOS pipe N5, N6, N7 form logical relation; PMOS pipe P8 and NMOS pipe N8 form inverter structure.The public grid of PMOS pipe P3 and NMOS pipe N3 is as an input end of rejection gate, link to each other with the bit line BLL of the first memory module LB, the public grid of PMOS pipe P4 and NMOS pipe N4 is as another input end of rejection gate, link to each other with the bit line BLR of the second memory module RB, the drain electrode of PMOS pipe P3 links to each other with the source electrode of PMOS pipe P4, the public drain electrode of PMOS pipe P4 and NMOS pipe N3, N4 is as the output of rejection gate, with in the 1-2 AND structure of next stage or input end link to each other; The public grid of PMOS pipe P5 and NMOS pipe N5 is as one and input end of 1-2 AND, link to each other with the bit line BLL of the first memory module LB, the public grid of PMOS pipe P6 and NMOS pipe N6 is as another and input end of 1-2 AND, link to each other with the bit line BLR of the second memory module RB, the source electrode of NMOS pipe N5 links to each other with the drain electrode of NMOS pipe N6, the drain electrode of PMOS pipe P5, P6 links to each other with the source electrode of PMOS pipe P7, and the public drain electrode of PMOS pipe P7 and NMOS pipe N5, N7 links to each other with back level phase inverter as the output of 1-2 AND; The common gate of PMOS pipe P8 and NMOS pipe N8 links to each other with the output of prime 1-2 AND as the input of phase inverter, and its public drain electrode keeps the shaping output circuit to link to each other as output terminal with subordinate.Above structure constitutes together or door, promptly exports L=BLL ⊙ BLR.(when being high level or being low level) is output as high level when BLL is identical with the BLR level; When BLL and BLR level (be BLL be that low level or BLR are when being low level for high level BLL for high level BLR) not simultaneously, be output as low level.The output signal of testing circuit enters the maintenance shaping circuit of next stage.

As shown in Figure 3, the half of storage array basic structure of the EEPROM that sense amplifier is connected, the half of storage array capacity of EEPROM is n * m byte, the minimum selected cell that is organized into the capable n row of m is the structure of a byte, the bit line of corresponding position in the same row (BLxy, wherein x ∈ (0,1..., m), y ∈ (0,1..., n)) link together, (WLx) links together with the word line in the delegation, word line (WL0-WLm) is selected m is capable, and the selected line word line is a high level, and simultaneously control corresponding gate voltage CG is admitted on the control gate of floating-gate pipe of the storage unit of being expert at, the selected line unit is not a low level, and the floating-gate pipe of place line storage unit keeps low level; Selection wire (SG0-SGn) is selected the n row, selects to be communicated to the row of sense amplifier, and selected column selection line is a high level, does not choose and classifies low level as.

As shown in Figure 4, the structure of the reading circuit that is made of sense amplifier is: SA0 represents 8 sense amplifier modules to SA7, and wherein the internal circuit of sense amplifier as shown in Figure 1.LB, RB are respectively first, second memory module, and the internal circuit of first, second memory module correspondence all as shown in Figure 3.The BLL of sense amplifier and BLR end are received respectively on the corresponding bit line of first, second memory module LB, RB, the control-grid voltage input end CG of first, second memory module, common source end S line and selection wire SG0-SGn correspondence respectively link together, wherein common source end S is connected with ground by the NMOS pipe N11 that is controlled by charging control end EN, the independent control of the word line of first, second storage block (WL0-WLm).

Above-mentioned institutional framework is 8 to be example with the storer bit wide, storer for other bit wides (1-64) is suitable equally, only need corresponding increase simultaneously or reduce by first storage block and second storage block in minimum selected cell in the number of storage unit (Cell) and the number of sense amplifier get final product.

Voltage unit described below is a volt (V).The threshold voltage of the floating-gate pipe of definition storage " 0 " information is Vtprogram, and the threshold voltage of the floating-gate pipe of storage " 1 " information is Vterase.(Vterase is greater than Vtprogram)

The circuit working process is as follows:

When not working, EN is a high level, NMOS pipe N1 among Fig. 2 in the charging control circuit 1 of sense amplifier, N2 conducting, the bit line BLL of first, second storage block and BLR go up electric charge and carry out bleed off by N1 and N2 respectively, all pulled down to low level, same or door in the testing circuit 2 is exported high level at this moment, therefore keep the PMOS pipe P9 in the shaping output circuit 3 to turn-off, NMOS pipe N9 opens, electric charge on the capacitor C 1 carries out bleed off by N9, capacitor C 1 top crown voltage pulled down to ground, exports high level by the phase inverter that PMOS pipe P10 and NMOS pipe N10 form; Simultaneously because EN is a high level, the NMOS pipe N11 among Fig. 4 opens, and the current potential of common source end (S) is pulled down to ground;

During work, illustrate as shown in Figure 4 with the data instance of reading first storage block, second row, first row, at first EN still keeps high level, the corresponding selection signal SG0 input high level (3.3V) of selected row (first row), other select signal SG1-SGn input low level (0), selected row (second row) corresponding word lines signal WLL1 input high level (3.3V), other word-line signals WLL0, the equal input low level of WLL2-WLLm, WLR0-WLRm (0), control-grid voltage input end CG are sent into and are read voltage V _CG:

V _CG=(Vtprogram+Vterase)/2 remove control gate this moment in the selected storage unit and select that node voltage is respectively VCC and V on the grid _CGOutward, other all nodes are all pulled down to ground (0) by following trombone slide NMOS pipe N2 and N9 among Fig. 2;

EN is changed to low level (0) then, and the NMOS pipe N11 among Fig. 4 turn-offs, and common source end S disconnects with ground and being connected, and PMOS pipe P1, P2 among Fig. 2 open, and bit line BLL, the BLR to first, second storage block charges respectively; Bit line for second storage block, because all word line WLR0-WLRm are low level, all storage unit are all opened, and the PMOS pipe P1 among Fig. 2 only needs the capacitance of drain of the selection pipe of m storage unit connecting on the pairs of bit line to charge, and total charging capacitor size is C _Ref=C _MSD* m, wherein C _MSDFor selecting the drain electrode parasitic capacitance value over the ground of pipe MS; For first storage block, will analyze respectively according to the difference of canned data.

When canned data on the storage unit was " 1 ", the threshold voltage of floating-gate pipe was Vterase, because V _CG=(Vtprogram+Vterase)/2＜Vterase, the floating-gate pipe of corresponding stored unit is not opened, PMOS among Fig. 2 pipe P2 only need the capacitance of drain of 1 selected storage unit floating-gate pipe connecting on the pairs of bit line and (m-1) capacitance of drain of individual not selected memory cell selecting pipe charge total charging capacitor size C _Tot=C _MCD+ C _MSD* (m-1), C wherein _MCDBe floating-gate pipe drain electrode parasitic capacitance value over the ground, owing to select the size of pipe and floating-gate pipe approaching, so can think C _MCD≈ C _MSD, C is then arranged _Tot≈ C _RefBe that the precharge charging capacitor is identical, simultaneously because charging valve PMOS pipe P1, the size of P2 equates, and bias condition identical (both grid all are connected with charging control end EN), and the initial potential of BLL and BLR is all identical (all to pulled down to ground when idle condition, current potential is 0), therefore in the time of can thinking to BLL and BLR charging, both ascending velocity much at one, and the turnover level of almost same by testing circuit among Fig. 2 simultaneously or door, the logic level that is both has only extremely short asynchronism(-nization), therefore testing circuit is only understood a short low level pulse of output stage, and owing to the low level pulse time is too short, C1 is short by the time compole of the pipe of the PMOS among Fig. 2 P9 charging, C1 top crown current potential rises slightly, but does not reach the turnover level of the phase inverter of being made up of PMOS pipe P10 among Fig. 2 and NMOS pipe N10, so sense amplifier output terminal OUT is output as high level (VCC); After this when EN is low level, PMOS pipe P9 guarantees and holds shutoff among Fig. 2, and NMOS pipe N9 keeps turn-offing, and C1 does not have the loop of charging and discharging, and current potential keeps low level (0) constant, and output terminal is still exported high level (VCC);

When canned data on the storage unit was " 0 ", the threshold voltage of floating-gate pipe was Vtprogram, because V _CG=(Vtprogram+Vterase)/2＞Vtprogram, the floating-gate pipe of corresponding stored unit is opened, the shared source end S of all storage unit that PMOS among Fig. 2 pipe P2 needs to connect on the pairs of bit line charge and (m-1) capacitance of drain of individual not selected memory cell selecting pipe charge total charging capacitor size C _Tot=C ' _SOURCE+ C _MSD* (m-1), C ' wherein _SOURCEBe the source end capacitance size that this sense amplifier is all assigned to, C ' _SOURCE=C _SOURCE/ x, wherein x is that canned data is the number of " 0 " in the selected byte, x ∈ (1,2,3...8), C _SOURCEBe the total stray capacitance of source end, C _SOURCE=8 * m * n * C _MCS, owing to select the size of pipe and floating-gate pipe approaching, so can think C _MCS≈ C _MSD, C is then arranged _TotWith C _RefRatio be k=C _Tot/ C _Ref=(8 * n)/x+1-(1/m) chooses suitable n, m value (promptly selecting the structure of suitable storer) can guarantee k＞＞1, i.e. C _Tot＞＞C _RefAt charging valve PMOS pipe P1, the size of P2 equates, and bias condition identical (both grid all are connected with charging control end EN), and the initial potential of BLL and BLR is all identical (all to pulled down to ground when idle condition, current potential is 0) situation under, BLR is because charging capacitor is little, voltage rises to high level rapidly, and BLL is because charging capacitor is big, ascending velocity is slow, therefore in charging process, have a period of time, during this period of time BLR boosted above testing circuit with or the turnover level of door, and this moment the BLL current potential still testing circuit with or the turnover level of door under, this moment with or door be output as low level, and because the difference of charging capacitor is bigger, therefore the low level duration is longer, C1 is longer by the time of the pipe of the PMOS among Fig. 2 P9 charging, by a period of time Δ t, C1 top crown current potential just rises and reaches the turnover level of the phase inverter of being made up of PMOS pipe P10 among Fig. 2 and NMOS pipe N10, so sense amplifier output terminal OUT is output as low level (0); After this when EN is low level, when BLL, BLR all above with or the turnover level of door after, PMOS pipe P9 guarantees and holds shutoff among Fig. 2, NMOS pipe N9 keeps turn-offing, C1 does not have the loop of charging and discharging, and C1 top crown current potential keeps high level (being about VCC) constant, and output terminal is output low level (0) still.

Example:

The description of this example is based on to adopt on SMIC (SMIC) the 0.35 μ m band built-in EEPROM technology basis carries out circuit design.The threshold voltage of the floating-gate pipe MC pipe of technology library definition storage " 1 " information is 4V, and the threshold voltage of the floating-gate pipe MC pipe of storage " 0 " information is-1V.The operating voltage VCC=3V of whole EEPROM.

During circuit working, the voltage that adds at CG and SG is respectively 1.5V and 3V, after the BL charging, if floating-gate pipe MC pipe storage " 0 " information, then floating-gate pipe MC conducting, the bit line capacitance of the storage block of choosing obtain the read output signal of " 0 " much larger than the electric capacity of not choosing storage block at output terminal; If floating-gate pipe MC pipe storage " 1 " information, then floating-gate pipe MC manages not conducting, and the bit line capacitance of both sides storage block is basic identical, therefore reads as " 1 ".

Claims (2)

1, a kind of sense amplifier that is used for EEPROM is characterized in that: it comprises charging control circuit (1), testing circuit (2) and keeps shaping output circuit (3);

Charging control circuit (1) is used to control the charging and the bleed off of pairs of bit line electric capacity, it is made of identical two charging control electronic circuits (11,12), two charging control electronic circuits (11,12) are controlled by charging control end (EN), and respectively two bit lines (BLL, BLR) are discharged and recharged;

Testing circuit (2) is used to detect the difference in above-mentioned two bit lines (BLL, BLR) duration of charging, be one with or door, the voltage of two bit lines (BLL, BLR) as with or the input of door; Its output is connected to the grid that keeps PMOS pipe (P9) in the shaping output circuit (3);

Keep shaping output circuit (3) to comprise that PMOS pipe (P9), PMOS pipe (P10), NMOS pipe (N9), the 2nd NMOS manage (N10) and electric capacity (C1); The grid of the one PMOS pipe (P9) connects the output terminal of testing circuit, and the grid of NMOS pipe (N9) connects charging control end (EN), and its public drain electrode connects the top crown of electric capacity (C1); Electric capacity (C1) is connected into capacitive form by the NMOS pipe and constitutes, and top crown is the grid of NMOS pipe, and the public drain electrode of managing (N9) with a PMOS pipe (P9) and a NMOS is connected with the input of subordinate's phase inverter, and bottom crown is connected with ground; The 2nd PMOS pipe (P10) and the 2nd NMOS pipe (N10) are formed inverter structure, and its public grid is as the top crown of input termination capacitor (C1), and its public drain electrode is as the output terminal of sense amplifier.

2, the reading circuit that constitutes by the described sense amplifier of claim 1, it is characterized in that: it comprises K sense amplifier and first, second memory module (the LB, RB), 1≤K≤64 wherein, two bit line (BLL of each sense amplifier, BLR) receive first respectively, second memory module (the LB, RB) on the corresponding bit line, first, second memory module (the LB, RB) control-grid voltage input end (CG), its common source end (S) and each selecting side correspondence respectively link together, wherein common source end (S) is connected first by the 3rd NMOS pipe (N11) that is controlled by charging control end (EN) with ground, second memory module (the LB, RB) word line is independently control separately.

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