CN100582970C - B-code demodulation method and demodulator - Google Patents
B-code demodulation method and demodulator Download PDFInfo
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- CN100582970C CN100582970C CN200510064505A CN200510064505A CN100582970C CN 100582970 C CN100582970 C CN 100582970C CN 200510064505 A CN200510064505 A CN 200510064505A CN 200510064505 A CN200510064505 A CN 200510064505A CN 100582970 C CN100582970 C CN 100582970C
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Abstract
The present invention discloses B-code demodulation method, and the key points of the method include that the B(AC) signal or the generated and received analog signal has the same frequency, the same phase and different amplitude with the analog reference signal and meets b1<c<b2, where c is the amplitude of the analog reference signal, b1 is the low amplitude of the analog signal and b2 is the high amplitude of the analog; and that the analog signal sampling voltage value Ei and the analog reference signal sampling voltage value Di in every set sample period are compared, and one high level is output if |Ei|>|Di| and one low level is output or else as the digital B signal B(DC). The present invention has precise demodulation of B code to meet the requirement of high precision time sync.
Description
Technical field
The present invention relates to the demodulation method and the demodulating equipment of synchronizing clock signals, relate in particular to a kind of IRIG-B sign indicating number demodulation method of (Inter Range Instrumentation Group-B is called for short the B sign indicating number).
Background technology
Most countries accepted standard time scale is based on the astronomical time of earth rotation and the Coordinated Universal Time(UTC) UTC that obtains based on the atomic time that atom vibrates in the world.The UTC time can disseminate by a lot of approach, such as: wireless and satellite navigation system, telephone modem and portable timer.The time reference of satellite navigation system is by the ground elapsed time reference source time service of country separately, therefore, adopts the receiver of GPS/GLONAS just can obtain the UTC time easily.Novel GPS/GLONASS receiver can directly be exported the format signal of 1PPS, RS-232, IRIG-B, for present widespread use temporal information lays the foundation.
IRIG (Inter Range Instrumentation Group) is the mechanism of the work such as responsible formulation target range standard under the U.S. RCC (Range CommandersCouncil).IRIG-B timing code (being called for short the B sign indicating number) is exactly a kind of serial timing code of being worked out by the TCG under the IRIG (Telecommunication Group).B sign indicating number major parameter is:
(1) structure
Corresponding code element of each pulse in the B sign indicating number, the punctual reference point of each code element is the rising edge of this pulse.The speed that code element repeats is called chip rate, and the chip rate of B sign indicating number is 100pps.
The different information of the different in width of code element representative in the B sign indicating number, the information that is the B sign indicating number adopts the method for width modulation to represent, the symbol width of B sign indicating number has three kinds, pulsewidth is that the code element information of 2ms is " 0 ", pulsewidth is that the code element information of 5ms is " 1 ", pulsewidth is that the code element information of 8ms is location recognition sign " P ", as shown in Figure 1.
(2) temporal information
The time letter of B sign indicating number adopts the metric coding of binary number representation, and promptly each decimal number of decimal system temporal information uses the binary number coding, and order from low to high during expression.Its expressed time is:
Second: the 1st～4,6～8 code elements.A position of using 4 code elements to represent second uses 3 code elements to represent ten of second to use 7 code elements altogether;
Divide: the 10th～13,15～17 code elements.Use 4 code elements to represent a position of branch, use 3 code elements to represent ten of branch to use 7 code elements altogether;
The time: the 20th～23,25,26 code elements.A position of using 4 code elements to represent hour, ten of using 2 code elements to represent hour use 6 code elements altogether;
My god: the 30th～33,35～38,40,41 code elements.Be decided to be the 1st day the January 1 in every year, the totally 365 days whole year (leap year is 366 days).Each uses 4 each code element to represent a position of fate and ten to use 2 code elements to represent hundred of fate to use 10 code elements altogether.
Time of day: the 80th～88,90～97 code elements.Use 17 code elements altogether.
See also Fig. 2, it is the B sign indicating number synoptic diagram of a time frame.The location recognition sign is called P1, P2, P3, P4, P5, P6, P7, P8, P9, P0, PR.The speed of location recognition sign is 10pps, leading 10ms when it is calibrated constantly.Witness marker is made up of location recognition mark P 0 and adjacent PR, and the rising edge of reference symbols sn PR is exactly the accurate second moment of this frame, so reference symbols sn PR is a most important code element in the B sign indicating number.From PR begin to position distinguishing mark P0 (be next witness marker before code element) totally 100 code elements form a time frame.The time frame rate of B sign indicating number is per second 1 frame.The all corresponding index count numeral of each code element of B sign indicating number is 0 to begin to be 99, to amount to 100 to P0 from PR, and index number is only for ease of each code element of statement B sign indicating number.
Utilize the regulation of IRIG-B, can know the time that obtains Fig. 2: 365 days (Dec 31 non-leap year) 23: 59: 59.95 TOD 86399 seconds.According to the respective specified of (2) temporal information, promptly as can be known second, branch, the time, day time, now mainly be the algorithm of explanation 0.95 and the algorithm of TOD.
0.95 algorithm: stipulate mark P in the IRIG-B standard
RSecond of rising edge correspondence be 0.00 second constantly, the width of each pulse is 10ms, i.e. 0.01s is so the rising edge position moment corresponding of the pulse of the arrow indication of letter " TOD " top is 0.95s in Fig. 2.
86399 algorithms that obtain: from zone bit P
8To P
0Between pulse as shown in Figure 2, submeter is represented each time power of 2, according to the pulse shown in the figure as can be known, current TOD is that the corresponding decimal number of " 11111110100010101 " (low level is preceding, and being expressed as binary number is exactly " 10101000101111111 ") is 86399 constantly.
From above-mentioned example as can be known, with code element is direct current (DC) sign indicating number (being called for short B (DC) sign indicating number) of B sign indicating number as pulse signal directly, it can realize the time synchronized of degree of precision (microsecond magnitude), but because the frequency spectrum of pulse signal is very abundant, narrow band channel can't transmit, and only is applicable to and uses the cable short range transmission; Long-distance transmissions is needed two processes usually:
Modulated process:, need be modulated into interchange (AC) sign indicating number (being called for short B (AC) sign indicating number) to direct current sign indicating number B (DC) sign indicating number at the reference source end;
Demodulating process:, B (AC) sign indicating number need be demodulated to B (DC) sign indicating number at receiving end.
B (DC) sign indicating number obtains B (AC) sign indicating number through ovennodulation, and its biggest advantage is that bandwidth greatly reduces.The frequency band of B (AC) sign indicating number is 100Hz～3kHz by analysis, and its energy mainly concentrates near the 1kHz.This just makes most of channel that transmits speech can be used for transmitting B (AC) sign indicating number, thereby makes time signal can be sent to tens kilometers user places in addition.
(1) at first simply introduces modulated process.
B (DC) sign indicating number carries out amplitude modulation(PAM) to the 1kHz sinusoidal signal, but because B (DC) sign indicating number transmits is the chronometer time signal, therefore different with general amplitude modulation(PAM).The one, the 1kHz sinusoidal signal must with the signal common source that produces B (DC) sign indicating number, can guarantee that so just both time relationships are constant always; The 2nd, can obtain the precise time signal in order to make receiving end, require B (AC) sign indicating number from by a narrow margin to the sinusoidal signal zero crossing of high-amplitude and B (DC) yard rising edge of a pulse strictness be consistent (seeing also Fig. 3).Receiving end can be by B (AC) sign indicating number is obtained the correct time signal from detecting to the precision of the quadrature zero crossing of high-amplitude by a narrow margin like this.IRIG standard-required B (AC) sign indicating number by a narrow margin with the ratio of high-amplitude, promptly modulation ratio will be between 1: 3 to 1: 6.Recommendation is 3: 10.
(2) then introduce demodulating process.
See also Fig. 4, it is a kind of demodulation principle structural representation.It comprises A/D converter 11 and comparer 12.The input end of A/D converter 11 according to predefined sample frequency sampled analog voltage of signals value e, and sends it to comparer 12 in order to receive simulating signal (being B (AC) sign indicating number).Comparer 12 compares the fixed voltage value a of the magnitude of voltage e that receives and the input of another input end, produces B (DC) sign indicating number with this.
Its amplitude demodulation ground concrete steps are as follows:
(1) produce a magnitude of voltage a, and b1＜a＜b2, wherein b1 is the magnitude of voltage of summit by a narrow margin of B (AC) sign indicating number modulation signal, b2 is the high-amplitude summit magnitude of voltage of B (AC) sign indicating number modulation signal.In fact, in order to improve precision, a is set to be slightly larger than the value of b1 usually;
(2) simulating signal e and a that receives compared,, then export high level, otherwise output low level demodulates B (DC) sign indicating number with this if more than or equal to a.
This demodulation method carries out demodulation and has time-delay.See also Fig. 5, the zero crossing n of B (AC) simulating signal is corresponding to time t
n, be t and adopt the corresponding time of the zero crossing of above-mentioned demodulation method acquisition
m, produce time-delay X=t thus
n-t
m
Stipulate in the IRIG-B 200-95 standard that IRIG-B AC signal magnitude of size ratio is 1: 3～1: 6, so according to Fig. 5 analysis as can be known, the span of time-delay X is
Millisecond, for the time synchronism equipment that time precision is had relatively high expectations, the time-delay that this classic method produces can not have been satisfied the synchronous requirement of split-second precision.
Summary of the invention
The object of the present invention is to provide a kind of demodulation method of B sign indicating number, to solve the technical matters of life period time-delay in the prior art.
For addressing the above problem, the invention discloses a kind of demodulation method of B sign indicating number, be used for receiver the B sign indicating number interchange simulating signal that receives is demodulated to B sign indicating number DC digital signal, comprising:
(1) produce and the reference analog signal of described simulating signal with frequency homophase and different amplitudes, and satisfy b1＜c＜b2, c is the amplitude of reference analog signal, and b1 is the amplitude by a narrow margin of described simulating signal, and b2 is the high-amplitude amplitude of described simulating signal;
(2) the sample voltage value e in comparison each predefined sampling period of simulating signal
iMagnitude of voltage d with same sampling period internal reference simulating signal
i, if | e
i|＞| d
i|, then export high level, otherwise, output low level, with output B sign indicating number DC digital signal, wherein i is the current period number.
Obtain the magnitude of voltage d of described reference analog signal
iSpecific implementation comprise: a1: the amplitude c of reference analog signal is set, and sets up the magnitude of voltage mapping table, described magnitude of voltage mapping table is preserved the corresponding relation of each angle and magnitude of voltage, and described magnitude of voltage is the magnitude of voltage d of described reference analog signal
i
A2: the voltage of periodic sampling simulating signal, and according to described magnitude of voltage e
iCalculate corresponding angle;
A3: search the magnitude of voltage mapping table according to described angle, obtain corresponding voltage value d
i
Obtain the magnitude of voltage d of described reference analog signal
iSpecific implementation comprise: A1: the amplitude c of reference analog signal is set, and sampling period T is set;
A2: determine initial voltage value d
0
A3:, obtain magnitude of voltage e according to described sampling period T real-time sampling simulating signal
i
A4: according to d
i=c/ π * T+d
(i-1)The magnitude of voltage d in this cycle of calculating
i
Determine initial voltage value d in the steps A 2
0Finish by following steps:
The sampled analog voltage of signals, and according to described magnitude of voltage e
iCalculate corresponding angle;
According to described angle calculation initial voltage value d
0
Obtain the magnitude of voltage d of described reference analog signal
iSpecific implementation comprise: the maximum voltage value of simulating signal and the voltage section between the minimum voltage value are divided equally into the N1 section, and N1 is a natural number; The maximum voltage value of reference analog signal and the voltage section between the minimum voltage value are divided equally into the N1 section; Fixed cycle sampled analog voltage of signals value e
i, determine the section of this magnitude of voltage correspondence; Find the magnitude of voltage d in this section corresponding reference simulating signal
i
The invention also discloses a kind of demodulating equipment of B sign indicating number, comprise A/D converter, clock source, signal generator and comparer, wherein:
A/D converter, its input end in order to according to predefined period of time T sampled analog signal, obtains the magnitude of voltage e in this cycle in order to receive simulating signal
i
Clock source: connect A/D converter and signal generator, be used to provide clock signal;
Signal generator: connect A/D converter, produce the reference voltage level d of this cycle reference analog signal in order to amplitude c according to predefined period of time T and reference analog signal
i, described reference analog signal and described simulating signal frequency homophase and different amplitude together, and satisfy b1＜c＜b2, c is the amplitude of reference analog signal, and b1 is the amplitude by a narrow margin of described simulating signal, and b2 is the high-amplitude amplitude of described simulating signal;
Comparer: connect A/D converter and signal generator, relatively the e in each cycle
iAnd d
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B sign indicating number DC digital signal.
This device also comprises: the gain controller that is connected with A/D converter, and in order to the voltage automatic gain of the simulating signal that will receive operating voltage range to A/D converter.
Described clock source, signal generator and comparer are realized by programmable logic device (PLD).
The invention also discloses a kind of demodulating equipment of B sign indicating number, comprise A/D converter, clock source, storage unit, computing unit and comparer, wherein:
A/D converter, its input end in order to according to predefined period of time T sampled analog signal, obtains the magnitude of voltage e in this cycle in order to receive simulating signal
i
Clock source: connect A/D converter and comparer, be used to provide clock signal;
Storage unit, in order to storage voltage value mapping table, described magnitude of voltage mapping table is preserved the corresponding relation of each angle and magnitude of voltage, and described magnitude of voltage is the magnitude of voltage d of reference analog signal
i
Computing unit: connect A/D converter, in order to according to magnitude of voltage e
iCalculate angle, search according to described angle that the magnitude of voltage mapping table obtains and the magnitude of voltage d in this cycle of output
i
Comparer: connect A/D converter and computing unit, relatively the e in each cycle
iAnd d
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B sign indicating number DC digital signal.
This device also comprises the gain controller that is connected with A/D converter, in order to the voltage automatic gain of the simulating signal that will the receive operating voltage range to A/D converter.
Clock source, storage unit, computing unit and comparer are realized by programmable logic device (PLD).
Compared with prior art, the present invention has the following advantages:
The present invention is by producing and the reference analog signal of the simulating signal that receives (being B (AC) signal) with frequency homophase and different amplitudes, relatively in the size of the reference voltage level d of the sample voltage value e of synchronization analog signals and this reference analog signal, export high level or low level then.Because little when a certain threshold value when the sampling period, sample B (AC) sign indicating number from by a narrow margin to high-amplitude, from high-amplitude to by a narrow margin quadrature zero crossing, demodulate B (DC) yard thus more accurately, so that satisfy the synchronous requirement of split-second precision.
Description of drawings
Fig. 1 is the synoptic diagram of three kinds of symbol widths of B sign indicating number;
Fig. 2 is the B sign indicating number synoptic diagram of a time frame;
Fig. 3 is a kind of modulator approach synoptic diagram;
Fig. 4 is a kind of existing demodulation principle structural representation;
Fig. 5 is a kind of synoptic diagram of demodulation;
Fig. 6 is that the principle of the demodulation method of B sign indicating number of the present invention realizes synoptic diagram;
Fig. 7 is a kind of demodulation enforcement figure based on Fig. 6;
Fig. 8 is the structural representation of the demodulating equipment of a kind of B of realization sign indicating number demodulation;
Fig. 9 is the structural representation of TLC5510A chip;
Figure 10 is the process flow diagram based on the demodulation method of above-mentioned demodulating equipment;
Figure 11 is the another kind of implementation structure figure of B sign indicating number demodulating equipment;
Figure 12 is the process flow diagram based on the demodulation method of above-mentioned demodulating equipment.
Embodiment
Below in conjunction with accompanying drawing, specify the present invention.
See also Fig. 6, its principle for the demodulation method of B sign indicating number of the present invention realizes synoptic diagram.Because existing modulator approach is that B (DC) sign indicating number is modulated into by a narrow margin B (AC) sign indicating number with high-amplitude, therefore separating timing in principle, receiver only need detect B (AC) sign indicating number that receives from by a narrow margin to high-amplitude, can accurately detect from high-amplitude to by a narrow margin quadrature zero crossing and to obtain the correct time signal.For this reason, core of the present invention is:
(1) produces and the reference analog signal (see in Fig. 6 dotted line simulating signal) of the simulating signal that receives (being B (AC) signal) with frequency homophase and different amplitudes, and satisfy b1＜c＜b2, c is the amplitude of reference analog signal, b1 is the amplitude by a narrow margin of described simulating signal, and b2 is the high-amplitude amplitude of described simulating signal;
(2) the sample voltage value e in comparison each predefined sampling period of simulating signal
iMagnitude of voltage d with same sampling period internal reference simulating signal
i, if | e
i|＞| d
i|, then export high level, otherwise, output low level, with output B (DC) digital signal, wherein i is the current period number.
Wherein, B (AC) sign indicating number is the sinusoidal signal of frequency 1KHZ, and the sampling period T that the present invention need set is at least N/one in the cycle of this sinusoidal signal, such as, T=1/16* (1KHZ).Sampling period, T was more little, and the precision of acquisition is high more.
See also Fig. 7, curve B among the figure
1The amplitude of IRIG-B AC signal b1 is V in the presentation graphs 6
0Waveform; Curve B
2The amplitude of IRIG-B AC signal b1 is V in the presentation graphs 6
0/ 3 waveform; B
3The amplitude of IRIG-B AC signal b1 is V in the presentation graphs 6
0/ 6 waveform; B
0The waveform of the artificial IRIG-B AC signal c that sets up in the presentation graphs 6.Illustrate: Y among Fig. 7
1, Y
0, Y
3, Y
2It is respectively curve B
1, B
0, B
3, B
2The respective amplitude value of t0 at a time.
Because the positive half cycle and the negative half period of sine wave-shaped signal are symmetric relations, therefore only analyze the demodulation principle of positive half cycle here.
The IRIG-B AC signal can be expressed as:
Y=Bsin2000 π t, wherein the B value is V
0, V
0/ 3, V
0/ 6, t is a time value.
When the modulation ratio of IRIG-B AC signal was 1: 3, the time delay of output depended on the data width in the demodulation.Data width is big more, and the time delay of output is more little.Y
1, Y
0, Y
2Be expressed as respectively:
Y
1＝B
1sin2000πt＝V
0sin2000πt
Y
0＝B
0sin2000πt＝V
0/2sin2000πt
Y
2＝B
2sin2000πt＝V
0/3sin2000πt
Result relatively is decided by Y
1-Y
0, Y
0-Y
2Value:
Y
1-Y
0＝B
1sin2000πt-B
0sin2000πt＝V
0sin2000πt-V
0/2sin2000πt＝V
0/2sin2000πt
Y
0-Y
2＝B
0sin2000πt-B
2sin2000πt＝V
0/2sin2000πt-V
0/3sin2000πt＝V
0/6sin2000πt
So, when data width is 8, Y
1-Y
0, Y
0-Y
2Value all be greater than the minimum value of the data that 8 bit data width can represent because what discuss now is positive half cycle, so Y
1-Y
0, Y
0-Y
2Value all be greater than V
0/ 2
7=V
0/ 128.That is:
Y
1-Y
0＝V
0/2sin2000πt＞V
0/128，Y
0-Y
2＝V
0/6sin2000πt＞V
0/128
Two top inequality are set up simultaneously, can obtain t＞7.46 * 10
-6Second, i.e. t＞7.46 microseconds.Derive as can be known, when data width is the N position,
So during N=12, t＞466 nanoseconds.
In sum, new method for designing can be reduced to several microseconds even littler by tens microseconds of classic method with the time delay of classic method, can satisfy the synchronous requirement of split-second precision thus.
See also Fig. 8, it is a kind of structural representation of realizing the demodulating equipment of B sign indicating number demodulation.It comprises A/D converter 22, clock source 25, signal generator 23 and comparer 24, wherein:
A/D converter 22, its input end in order to according to predefined period of time T sampled analog signal, obtains the magnitude of voltage e in this cycle in order to receive simulating signal
iB (AC) voltage of signals amplitude is between 0.5-10V.Because the operating voltage range that the A/D converter 22 of different model is suitable for is different, therefore, when if the operating voltage of the A/D converter 22 that adopts also drops on this scope, then the input end of A/D converter 22 can be directly in order to receive simulating signal, otherwise A/D converter 22 needs external gain controller 21 that the voltage amplitude of B (AC) is adjusted in the operating voltage range of A/D converter 22.Gain controller 21 can adopt the gain circuitry as AGC, gain amplifier etc.Thus, this gain controller 21 is not just given unnecessary details at this for existing known technology.
Clock source 25: connect A/D converter 22, signal generator 23 and comparer 24, be used to the clock signal that provides unified.This clock source 25 should be a high frequency clock source, and the cycle of the clock signal of its generation can be identical with the predefined sampling period, also can be N/one times of this sampling period T, and wherein N is a natural number.
Signal generator 23: connect A/D converter 22, produce the reference voltage level d of the reference analog signal in this sampling period in order to amplitude c according to predefined period of time T and reference analog signal
iSignal generator is according to d
i=c/ π * T+d
(i-1)The magnitude of voltage d in this cycle of calculating
i, such as: d
1=c/ π * T+d
0, initial voltage value d
0Finish by following steps: (1) sampled analog voltage of signals, and according to the corresponding angle of magnitude of voltage e calculating; (2) according to described angle calculation initial voltage value d
0In fact, signal generator 23 can be finished by programmable logic device (PLD) (as FPGA).
Comparer 23: connect A/D converter and signal generator, relatively the e in each cycle
iAnd d
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B (DC) digital signal.
Clock source 25, signal generator 23 and comparer 24 can be realized by a programmable logic device (PLD) (such as FPGA).Clock signal is provided for A/D converter 22 by FPGA, FPGA can produce corresponding clock by crystal oscillator, is the clock frequency of 500khz such as frequency is provided.
A/D converter of the present invention can adopt TLC5510A (as shown in Figure 9), and FPGA can adopt Xilinx (match SEL) spartanIIE of company series xc2s400e.Wherein the frequency provided by FPGA is provided is the clock signal of 500hz to A/D converter, sample voltage value e
iBe that 8 routes by D1-D8 export FPGA to.
See also Figure 10, it is the process flow diagram based on the demodulation method of above-mentioned demodulating equipment.It comprises:
S110: the amplitude c of reference analog signal is set in FPGA, and sampling period T is set;
S120: determine initial voltage value d
0
A/D converter 22 receives B (AC) signal, under the control of the clock signal that FPGA provides, and A/D converter 22 first magnitude of voltage of sampling e
0
Behind the A/D converter sampled analog signal, described sampled value is directly inputted among the FPGA; In FPGA, will export behind the reference analog voltage of this sampling numerical value by this corresponding sampled value of cordic algorithm calculating.
FPGA is according to the magnitude of voltage e that receives
0And the range value of B (AC) signal, calculate this magnitude of voltage e
0Corresponding angle can be calculated initial voltage value d according to this angle
0
The S130:A/D converter obtains the magnitude of voltage e in each sampling period according to sampling period T sampled analog signal
i, and with e
iExport FPGA to;
S140:FPGA receives e
i, according to d
i=c/ π * T+d
(i-1)Calculate the magnitude of voltage d in this sampling period
i
S150:FPGA is the sample voltage value e of simulating signal relatively
iMagnitude of voltage d with same sampling period internal reference simulating signal
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B (DC) digital signal.
Whenever the A/D converter sampling obtains a magnitude of voltage e
i, FPGA produces corresponding reference magnitude of voltage d
i, be exportable corresponding digital digital signal after relatively.Usually, consider the time-delay when A/D converter etc. carries out data processing, obtain proofreading and correct behind the delay time of whole demodulating process by modes such as emulation in advance.Owing to can know its delay time according to different A/D converter chips, so the technician also can carry out the signal after the demodulation correction of this delay time.
Can certainly be: at first A/D converter be divided equally into the N1 section with the maximum voltage value of simulating signal and the voltage section between the minimum voltage value, and N1 is a natural number; Then, the maximum voltage value of reference analog signal and the voltage section between the minimum voltage value are divided equally into the N1 section; Subsequently, sampled analog voltage of signals value e in each sampling period T
i, determine the section of this magnitude of voltage correspondence; At last, find magnitude of voltage d in this section corresponding reference simulating signal
i, be the reference voltage level d in this sampling period T
iSuch as:
The minimum value of Vref (B) expression analog voltage range in the last table, the maximal value of Vref (T) expression analog voltage range.Transfer principle: it is 256 sections that A/D converter inside is divided the voltage section between these two magnitudes of voltage equally, judges that the sampled value voltage swing that receives the A/D converter transmission is in which section of voltage section, the digital quantity that output is corresponding.When input voltage is higher than Vref (T), when being output as " 11111111 " and being lower than Vref (B), be output as " 00000000 ".
Accordingly, maximum voltage value and the voltage section between the minimum voltage value with reference analog signal is divided equally into 256 sections, sampled analog voltage of signals value e in each sampling period T
i, determine the section of this magnitude of voltage correspondence; Find the magnitude of voltage d in this section corresponding reference simulating signal thus
i
The present invention also discloses the demodulating equipment of another kind of B sign indicating number.See also Figure 11, it is the another kind of implementation structure figure of B sign indicating number demodulating equipment.It comprises A/D converter 21, clock source 25, storage unit 32, computing unit 33 and comparer 14, wherein:
A/D converter, its input end in order to according to predefined period of time T sampled analog signal, obtains the magnitude of voltage e in this cycle in order to receive simulating signal
iB (AC) voltage of signals amplitude is between 0.5-10V.Because the operating voltage range that the A/D converter 22 of different model is suitable for is different, therefore, when if the operating voltage of the A/D converter 22 that adopts also drops on this scope, then the input end of A/D converter 22 can be directly in order to receive simulating signal, otherwise A/D converter 22 needs external gain controller 21 that the voltage amplitude of B (AC) is adjusted in the operating voltage range of A/D converter 22.Gain controller 21 can adopt the gain circuitry as AGC, gain amplifier etc.Thus, this gain controller 21 is not just given unnecessary details at this for existing known technology.
Clock source 25: connect A/D converter 22, computing unit 31 and comparer 24, be used to the clock signal that provides unified.This clock source 25 should be a high frequency clock source, and the cycle of the clock signal of its generation can be identical with the predefined sampling period, also can be N/one times of this sampling period T, and wherein N is a natural number.
Storage unit 32 is in order to storage voltage value mapping table.Preserve each angle corresponding reference magnitude of voltage in this magnitude of voltage mapping table.
Computing unit 31: connect A/D converter 21, in order to according to magnitude of voltage e
iCalculate angle, search according to described angle that the magnitude of voltage mapping table obtains and the magnitude of voltage d in this cycle of output
iStorage unit 31 and computing unit 32 can be realized with a programmable logic device (PLD).
Comparer 24: connect A/D converter and computing unit, relatively the e in each cycle
iAnd d
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B (DC) digital signal.
Clock source 25, storage unit 32, computing unit 31 and comparer 24 can pass through programmable logic device (PLD) (such as a, fpga chip) to be realized.
See also Figure 12, it is the process flow diagram based on the demodulation method of above-mentioned demodulating equipment.It comprises:
S210: the amplitude c of reference analog signal is set in FPGA, and sampling period T is set;
S220: set up and preserve the voltage mapping table, the voltage mapping table is stored in the storage unit after can being set by the technician;
The S230:A/D converter is at each sampling period sampled analog voltage of signals e
i
S240:FPGA is earlier according to magnitude of voltage e
iCalculate corresponding angle; Search the magnitude of voltage mapping table according to described angle then, obtain corresponding voltage value d
i
S250:FPGA is the sample voltage value e of simulating signal relatively
iMagnitude of voltage d with same sampling period internal reference simulating signal
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B (DC) digital signal.
B (DC) digital signal according to output demodulates the corresponding time according to the structure of B sign indicating number and the regulation of following time signal.
Being defined as of described temporal information:
Second: the 1st～4,6～8 code elements.A position of using 4 code elements to represent second uses 3 code elements to represent ten of second to use 7 code elements altogether;
Divide: the 10th～13,15～17 code elements.Use 4 code elements to represent a position of branch, use 3 code elements to represent ten of branch to use 7 code elements altogether;
The time: the 20th～23,25,26 code elements.A position of using 4 code elements to represent hour, ten of using 2 code elements to represent hour use 6 code elements altogether;
My god: the 30th～33,35～38,40,41 code elements.Be decided to be the 1st day the January 1 in every year, the totally 365 days whole year (leap year is 366 days).Each uses 4 each code element to represent a position of fate and ten to use 2 code elements to represent hundred of fate to use 10 code elements altogether.
Time of day: the 80th～88,90～97 code elements.Use 17 code elements altogether.
More than disclosed only be several specific embodiment of the present invention, but the present invention is not limited thereto, any those skilled in the art can think variation, all should drop in protection scope of the present invention.
Claims (11)
1, a kind of demodulation method of B sign indicating number is used for receiver the B sign indicating number interchange simulating signal that receives is demodulated to B sign indicating number DC digital signal, it is characterized in that, comprising:
(1) produce and the reference analog signal of described simulating signal with frequency homophase and different amplitudes, and satisfy b1＜c＜b2, c is the amplitude of reference analog signal, and b1 is the amplitude by a narrow margin of described simulating signal, and b2 is the high-amplitude amplitude of described simulating signal;
(2) the sample voltage value e in comparison each predefined sampling period of simulating signal
iMagnitude of voltage d with same sampling period internal reference simulating signal
i, if | e
i|＞| d
i|, then export high level, otherwise, output low level, with output B sign indicating number DC digital signal, wherein i is the current period number.
2, B sign indicating number demodulation method as claimed in claim 1 is characterized in that, obtains the magnitude of voltage d of described reference analog signal
iSpecific implementation comprise:
A1: the amplitude c of reference analog signal is set, and sets up the magnitude of voltage mapping table, described magnitude of voltage mapping table is preserved the corresponding relation of each angle and magnitude of voltage, and described magnitude of voltage is the magnitude of voltage d of described reference analog signal
i
A2: the voltage of periodic sampling simulating signal, and according to described magnitude of voltage e
iCalculate corresponding angle;
A3: search the magnitude of voltage mapping table according to described angle, obtain corresponding voltage value d
i
3, B sign indicating number demodulation method as claimed in claim 1 is characterized in that, obtains the magnitude of voltage d of described reference analog signal
iSpecific implementation comprise:
A1: the amplitude c of reference analog signal is set, and sampling period T is set;
A2: determine initial voltage value d
0
A3:, obtain magnitude of voltage e according to described sampling period T real-time sampling simulating signal
i
A4: according to d
i=c/ π * T+d
(i-1)The magnitude of voltage d in this cycle of calculating
i
4, B sign indicating number demodulation method as claimed in claim 3 is characterized in that, determines initial voltage value d in the steps A 2
0Finish by following steps:
The sampled analog voltage of signals, and according to described magnitude of voltage e
iCalculate corresponding angle;
According to described angle calculation initial voltage value d
0
5, B sign indicating number demodulation method as claimed in claim 1 is characterized in that, obtains the magnitude of voltage d of described reference analog signal
iSpecific implementation comprise:
The maximum voltage value of simulating signal and the voltage section between the minimum voltage value are divided equally into the N1 section, and N1 is a natural number;
The maximum voltage value of reference analog signal and the voltage section between the minimum voltage value are divided equally into the N1 section;
Fixed cycle sampled analog voltage of signals value e
i, determine the section of this magnitude of voltage correspondence;
Find the magnitude of voltage d in this section corresponding reference simulating signal
i
6, a kind of demodulating equipment of B sign indicating number is characterized in that, comprises A/D converter, clock source, signal generator and comparer, wherein:
A/D converter, its input end in order to according to predefined period of time T sampled analog signal, obtains the magnitude of voltage e in this cycle in order to receive simulating signal
i
Clock source: connect A/D converter and signal generator, be used to provide clock signal;
Signal generator: connect A/D converter, produce the reference voltage level d of this cycle reference analog signal in order to amplitude c according to predefined period of time T and reference analog signal
i, described reference analog signal and described simulating signal frequency homophase and different amplitude together, and satisfy b1＜c＜b2, c is the amplitude of reference analog signal, and b1 is the amplitude by a narrow margin of described simulating signal, and b2 is the high-amplitude amplitude of described simulating signal;
Comparer: connect A/D converter and signal generator, relatively the e in each cycle
iAnd d
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B sign indicating number DC digital signal.
7, the demodulating equipment of B sign indicating number as claimed in claim 6 is characterized in that, also comprises: the gain controller that is connected with A/D converter, and in order to the voltage automatic gain of the simulating signal that will receive operating voltage range to A/D converter.
As the demodulating equipment of claim 6 or 7 described B sign indicating numbers, it is characterized in that 8, described clock source, signal generator and comparer are realized by programmable logic device (PLD).
9, a kind of demodulating equipment of B sign indicating number is characterized in that, comprises A/D converter, clock source, storage unit, computing unit and comparer, wherein:
A/D converter, its input end in order to according to predefined period of time T sampled analog signal, obtains the magnitude of voltage e in this cycle in order to receive simulating signal
i
Clock source: connect A/D converter and comparer, be used to provide clock signal;
Storage unit, in order to storage voltage value mapping table, described magnitude of voltage mapping table is preserved the corresponding relation of each angle and magnitude of voltage, and described magnitude of voltage is the magnitude of voltage d of reference analog signal
i
Computing unit: connect A/D converter, in order to according to magnitude of voltage e
iCalculate angle, search according to described angle that the magnitude of voltage mapping table obtains and the magnitude of voltage d in this cycle of output
i
Comparer: connect A/D converter and computing unit, relatively the e in each cycle
iAnd d
i, if | e
i|＞| d
i|, then export high level, otherwise output low level is with output B sign indicating number DC digital signal.
10, the demodulating equipment of B sign indicating number as claimed in claim 9 is characterized in that, also comprises: the gain controller that is connected with A/D converter, and in order to the voltage automatic gain of the simulating signal that will receive operating voltage range to A/D converter.
As the demodulating equipment of claim 9 or 10 described B sign indicating numbers, it is characterized in that 11, clock source, storage unit, computing unit and comparer are realized by programmable logic device (PLD).
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| CN101957593B (en) * | 2008-06-12 | 2011-11-16 | 湖北省电力试验研究院 | Time information detection method of output signal of satellite synchronization time service device |
| CN101871976B (en) * | 2009-04-24 | 2012-06-20 | 郑州威科姆科技股份有限公司 | Power clock detecting device |
| CN102023566B (en) * | 2010-10-13 | 2011-12-14 | 上海爱瑞科技发展有限公司 | Method for controlling and producing AC code of IRIG-B as time synchronization standard by FPGA (field programmable gata array) |
| CN102420609B (en) * | 2011-11-22 | 2014-05-28 | 北京遥测技术研究所 | Novel IRIG (Inter Range Instrumentation Group)-B alternating current code intelligent decoding method |
| CN104991440B (en) * | 2015-07-14 | 2017-03-01 | 中北大学 | High accuracy IRIG B（AC）Code demodulation method and device |
| CN113341687B (en) * | 2021-06-24 | 2022-12-09 | 中国船舶重工集团公司第七0七研究所 | High-precision self-correcting IRIG-B (AC) code modulation device and method |
| CN115657448B (en) * | 2022-12-09 | 2023-03-28 | 电信科学技术第五研究所有限公司 | Frequency offset analysis method for clock discipline |
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