CN108055257A - A kind of FPGA auxiliary high-performance calculation methods and FPGA - Google Patents
A kind of FPGA auxiliary high-performance calculation methods and FPGA Download PDFInfo
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- CN108055257A CN108055257A CN201711294774.XA CN201711294774A CN108055257A CN 108055257 A CN108055257 A CN 108055257A CN 201711294774 A CN201711294774 A CN 201711294774A CN 108055257 A CN108055257 A CN 108055257A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/28—Timers or timing mechanisms used in protocols
Abstract
The invention discloses a kind of FPGA auxiliary high-performance calculation methods and FPGA, this method to include：FPGA to from school when source obtain original time data extract and parse, obtain school when temporal information；According to temporal information during school and reference time information, calculated using algorithm during default school and obtain correcting delay signal, and correcting delay signal is sent to correction device using data/address bus；Wherein, reference time information is that the temporal information of generation is corresponded to according to system clock；The present invention by using the calibration source in such as IRIG B codes source as clock source, network delay and standard Network Time Protocol when avoiding NTP software schools in mode existing time error in itself；Clock alignment is carried out using the characteristics of FPGA parallel processings and using algorithm during school, time error caused by avoiding serial arithmetic mode improves the time precision of clock alignment, so as to further meet the demand of industrial automation scheme.
Description
Technical field
The present invention relates to industrial automation, more particularly to a kind of FPGA auxiliary high-performance calculation methods and FPGA.
Background technology
With the development of modern society's science and technology, accurate temporal information is generally required in industrial automation to meet work
The demand of skill and related work.
When in the prior art, usually using NTP (Network Time Protocol, Network Time Protocol) software school
Mode is used as time source by the collecting computer time, synchronous into row clock by processor, is then handed down to use device.
It is effective theoretically to see existing calibration method, but problem is that temporal information is handed down to processor by computer by network
It will there are network delays；The computing mode of processor is serial mode, and a week is often depending on to the development of relevant work
The workload of phase, so will result in processor into be often not on during the work of row clock synchronization agreement when segmentum intercalaris
Point, but it is advanced or lag behind timing node, cause time error；And standard Network Time Protocol inherently there are Millisecond when
Between error, so will result in clock alignment error.Therefore, the time error for how solving existing calibration method big is asked
Topic improves the time precision of clock alignment, is urgent problem now.
The content of the invention
The object of the present invention is to provide a kind of FPGA auxiliary high-performance calculation methods and FPGA, to utilize FPGA (Field-
Programmable Gate Array, field programmable gate array) parallel processing the characteristics of carry out clock alignment, during solution
Between error it is excessive the problem of, improve the time precision of clock alignment.
In order to solve the above technical problems, the present invention provides a kind of FPGA auxiliary high-performance calculation method, including：
FPGA to from school when source obtain original time data extract and parse, obtain school when temporal information；
According to temporal information during the school and reference time information, believe when calculating using algorithm during default school and obtain school
Number, and the correcting delay signal is sent to correction device using data/address bus；Wherein, the reference time information is according to system
Clock corresponds to the temporal information of generation.
Optionally, the FPGA to from school when source obtain original time data extract and parse, obtain school constantly
Between information, including：
Using predetermined physical interface from the school when source obtain the corresponding level signal of the original time data；
The level signal is converted into the original time data, and from the original time extracting data school when it is former
Beginning time data；Wherein, when original time data is are calibrated required original in the original time data during school
Between data；
Original time data parse during to the school, temporal information when obtaining the school.
Optionally, source is specially IRIG-B codes source during the school.
Optionally, it is described according to temporal information during the school and reference time information, it is calculated using algorithm during default school
Correcting delay signal is obtained, and the correcting delay signal is sent to correction device using data/address bus, including：
According to temporal information during the school and reference time information, the algorithm during school and default punctual algorithm meter are utilized
It calculates and obtains the correcting delay signal and punctual signal；
The correcting delay signal is sent to the correction device using the data/address bus, and the punctual signal is sent
To time keeping device.
Optionally, it is described according to temporal information during the school and reference time information, using algorithm during the school and preset
Punctual algorithm calculate before obtaining the correcting delay signal and punctual signal, further include：
It is corresponded to according to the system clock and generates the reference time information.
In addition, the present invention also provides a kind of FPGA, including：
Acquisition module, for from school when source obtain original time data extract and parse, obtain school when the time
Information；
Algoritic module, for according to temporal information during the school and reference time information, utilizing algorithm meter during default school
It calculates and obtains correcting delay signal, and the correcting delay signal is sent to correction device using data/address bus；Wherein, the reference time letter
It ceases to correspond to the temporal information of generation according to system clock.
Optionally, the acquisition module, including：
Receiving submodule, for using predetermined physical interface from the school when to obtain the original time data corresponding in source
Level signal；
Extracting sub-module, for the level signal to be converted into the original time data, and from the original time
Original time data during extracting data school；Wherein, original time data are to be carried out in the original time data during school
Required original time data during school；
Analyzing sub-module, original time data parse during for the school, temporal information when obtaining the school.
Optionally, the receiving submodule is specifically used for using described in the predetermined physical interface from IRIG-B codes source acquisition
Level signal.
Optionally, the algoritic module, including：
Algorithm submodule, for according to temporal information during the school and reference time information, using algorithm during the school and
Default punctual algorithm, which calculates, obtains the correcting delay signal and punctual signal；
Output sub-module, for the correcting delay signal to be sent to the correction device using the data/address bus, and will
The punctual signal is sent to time keeping device.
Optionally, the algoritic module, further includes：
With reference to submodule, the reference time information is generated for being corresponded to according to the system clock.
A kind of FPGA auxiliary high-performance calculation method provided by the present invention, including：FPGA to from school when source obtain original
Beginning time data is extracted and parsed, temporal information when obtaining school；According to temporal information during school and reference time information, utilize
Algorithm, which calculates, during default school obtains correcting delay signal, and correcting delay signal is sent to correction device using data/address bus；Wherein, join
It is that the temporal information of generation is corresponded to according to system clock to examine temporal information；
As it can be seen that the calibration source of the invention by using such as IRIG-B codes source as clock source, avoids NTP softwares school when side
Network delay and standard Network Time Protocol in formula existing time error in itself；Using the characteristics of FPGA parallel processings and using
Algorithm carries out clock alignment during school, and time error caused by avoiding serial arithmetic mode makes time precision can reach Microsecond grade,
It solves the problems, such as that time error is excessive, improves the time precision of clock alignment, so as to further meet industrial automation
The demand of scheme.In addition, the present invention also provides a kind of FPGA, equally with above-mentioned advantageous effect.
Description of the drawings
It in order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
A kind of flow chart for FPGA auxiliary high-performance calculation methods that Fig. 1 is provided by the embodiment of the present invention；
The structural representation of FPGA in a kind of FPGA auxiliary high-performance calculation methods that Fig. 2 is provided by the embodiment of the present invention
Figure；
A kind of structure chart for FPGA that Fig. 3 is provided by the embodiment of the present invention.
Specific embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, the technical solution in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
All other embodiments obtained without making creative work belong to the scope of protection of the invention.
It please refers to Fig.1, a kind of flow for FPGA auxiliary high-performance calculation methods that Fig. 1 is provided by the embodiment of the present invention
Figure.This method can include：
Step 101：FPGA to from school when source obtain original time data extract and parse, obtain school when the time believe
Breath.
Wherein, in this step FPGA from school when source obtain original time data, can from school when source directly acquire
The data of temporal information can be parsed；Or to from school when the source level signal that directly acquires convert after, obtain
The data that can parse temporal information, when source is IRIG-B code sources such as when school, FPGA can be using such as RS485 interfaces
Peripheral hardware physical interface receives the corresponding level signal of original time data from IRIG-B codes source, then level signal is converted to original
Time data.It, can be by designer according to practical scene for the specific acquisition modes and particular content of original time data
It voluntarily sets, is such as configured according to the type of the calibration source of selection correspondence, the present embodiment does not do this any with user demand
Limitation.
Specifically, RS485 interfaces are a kind of communication interface based on serial ports, using differential signal negative logic ,+2V~+6V
It represents " 0 ", -6V~-2V represents " 1 ".IRIG-B codes are in IRIG (Inter Range Instrumentation Group) code
A kind of most common timing code form, IRIG codes are a kind of time standard that the U.S. target range commandant committee formulates.
It is understood that since there are many temporal information species that can be parsed in original time data, clock is included
Such as other kinds of temporal information of leap year information outside prover time information needed for calibration is to reduce FPGA to original time number
According to required time and workload is carried out, can first classify to the original time data of acquisition, extraction prover time letter
Original time data when ceasing corresponding school, then when original time data carry out parsing and obtain the calibration needed for clock alignment during to school
Between information, as long as can obtain using during school algorithm calculate correcting delay signal needed for prover time information, the present embodiment to this not
Do any restrictions.
Specifically, as shown in Fig. 2, RS485 interface modules utilize RS485 interfaces (predetermined physical interface) from IRIG-B codes source
(source during school) obtains the corresponding level signal of original time data；Level signal is converted into original time number by data processing module
According to, and from original time extracting data school when original time data；Wherein, original time data are original time data during school
In required original time data are calibrated；Original time data parse when time resolution module is to school, when obtaining B codes
Between information (temporal information during school).
Step 102：According to temporal information during school and reference time information, using when algorithm calculating obtains school during default school
Signal, and correcting delay signal is sent to correction device using data/address bus；Wherein, reference time information is according to system clock pair
The temporal information that should be generated.
Wherein, as shown in Fig. 2, this step can be believed for the algoritic module in FPGA with temporal information during school and reference time
Breath input is calculated using algorithm during school and obtains correcting delay signal, by signal output during data/address bus high-ranking officers to correction device, is realized
To the time calibration of correction device.The particular content of algorithm during for pre-set school, can be by designer according to practicality
Scene and user demand are voluntarily set, and correction device is obtained as long as can be calculated according to temporal information during school and reference time information
Required correcting delay signal, realizes clock alignment function, and the present embodiment does not do this any restrictions.
Preferably, the method that the present embodiment is provided can not only realize clock alignment function, can also realize punctual work(
Energy.That is, this step can be specially according to temporal information during school and reference time information, using algorithm during school and preset
Punctual algorithm calculate and obtain correcting delay signal and punctual signal；Correcting delay signal is sent to correction device using data/address bus, and
Punctual signal is sent to time keeping device.Wherein, temporal information can include the school obtained to the parsing of original time data during school
When algorithm needed for temporal information and the temporal information needed for punctual algorithm.
It is understood that correction device and time keeping device can be respectively to need to carry out clock alignment and be kept
When device.It for the specific choice of correction device and time keeping device, can voluntarily be set, correction device and kept by designer
When device can be same device, as the device needs to carry out simultaneously clock alignment and punctual.The present embodiment does not do this any
Limitation.
Specifically, the step of FPGA corresponds to generation reference time information according to system clock before this step.
In the present embodiment, the embodiment of the present invention, as clock source, is avoided by using the calibration source in such as IRIG-B codes source
Network delay and standard Network Time Protocol during NTP software schools in mode existing time error in itself；Located parallel using FPGA
The characteristics of reason, simultaneously carries out clock alignment using algorithm during school, and time error caused by avoiding serial arithmetic mode makes the time smart
Degree can reach Microsecond grade, solves the problems, such as that time error is excessive, improves the time precision of clock alignment, so as to further full
The foot demand of industrial automation scheme.
It please refers to Fig.3, a kind of structure chart for FPGA that Fig. 3 is provided by the embodiment of the present invention.The FPGA can include：
Acquisition module 100, for from school when source obtain original time data extract and parse, obtain school constantly
Between information；
Algoritic module 200, for according to temporal information during school and reference time information, being calculated using algorithm during default school
Correcting delay signal is obtained, and correcting delay signal is sent to correction device using data/address bus；Wherein, reference time information is according to being
Clock of uniting corresponds to the temporal information of generation.
Optionally, acquisition module 100 can include：
Receiving submodule, for using predetermined physical interface from school when source obtain the corresponding level of original time data and believe
Number；
Extracting sub-module, for level signal to be converted into original time data, and from original time extracting data school
When original time data；Wherein, original time data are that required original time number is calibrated in original time data during school
According to；
Analyzing sub-module, original time data parse during for school, temporal information when obtaining school.
Optionally, receiving submodule is specifically used for obtaining level signal from IRIG-B codes source using predetermined physical interface.
Specifically, as shown in Fig. 2, RS485 interface modules (receiving submodule) utilize RS485 interfaces (predetermined physical interface)
The corresponding level signal of original time data is obtained from IRIG-B codes source (source during school)；Data processing module (extracting sub-module) will
Level signal is converted into original time data, and from original time extracting data school when original time data；Wherein, it is former during school
Beginning time data is that required original time data are calibrated in original time data；Time resolution module (analyzing sub-module)
Original time data parse during to school, obtain B codes temporal information (temporal information during school).
Optionally, algoritic module 200 can include：
Algorithm submodule for according to temporal information during school and reference time information, using algorithm during school and default is kept
When algorithm calculate and obtain correcting delay signal and punctual signal；
Output sub-module for correcting delay signal to be sent to correction device using data/address bus, and punctual signal is sent
To time keeping device.
Optionally, algoritic module 200 can also include：
With reference to submodule, for corresponding to generation reference time information according to system clock.
In the present embodiment, the embodiment of the present invention, as clock source, is avoided by using the calibration source in such as IRIG-B codes source
Network delay and standard Network Time Protocol during NTP software schools in mode existing time error in itself；Located parallel using FPGA
The characteristics of reason, simultaneously carries out clock alignment using algorithm during school, and time error caused by avoiding serial arithmetic mode makes the time smart
Degree can reach Microsecond grade, solves the problems, such as that time error is excessive, improves the time precision of clock alignment, so as to further full
The foot demand of industrial automation scheme.
Each embodiment is described by the way of progressive in specification, the highlights of each of the examples are with other realities
Apply the difference of example, just to refer each other for identical similar portion between each embodiment.For FPGA disclosed in embodiment
Speech, since it is corresponded to the methods disclosed in the examples, so description is fairly simple, related part is referring to method part illustration
.
Professional further appreciates that, with reference to each exemplary unit of the embodiments described herein description
And algorithm steps, can be realized with the combination of electronic hardware, computer software or the two, in order to clearly demonstrate hardware and
The interchangeability of software generally describes each exemplary composition and step according to function in the above description.These
Function is performed actually with hardware or software mode, specific application and design constraint depending on technical solution.Specialty
Technical staff can realize described function to each specific application using distinct methods, but this realization should not
Think beyond the scope of this invention.
It can directly be held with reference to the step of method or algorithm that the embodiments described herein describes with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
High-performance calculation method and FPGA is aided in be described in detail FPGA provided by the present invention above.Herein
It applies specific case to be set forth the principle of the present invention and embodiment, the explanation of above example is only intended to help
Understand the method and its core concept of the present invention.It should be pointed out that it for those skilled in the art, is not taking off
On the premise of from the principle of the invention, can also to the present invention, some improvement and modification can also be carried out, these improvement and modification also fall into this
In invention scope of the claims.
Claims (10)
1. a kind of FPGA aids in high-performance calculation method, which is characterized in that including：
FPGA to from school when source obtain original time data extract and parse, obtain school when temporal information；
According to temporal information during the school and reference time information, calculated using algorithm during default school and obtain correcting delay signal, and
The correcting delay signal is sent to correction device using data/address bus；Wherein, the reference time information is according to system clock
The temporal information of corresponding generation.
2. FPGA according to claim 1 aids in high-performance calculation method, which is characterized in that the FPGA to from school when source
The original time data of acquisition are extracted and parsed, temporal information when obtaining school, including：
Using predetermined physical interface from the school when source obtain the corresponding level signal of the original time data；
The level signal is converted into the original time data, and from the original time extracting data school when it is original when
Between data；Wherein, original time data are that required original time number is calibrated in the original time data during school
According to；
Original time data parse during to the school, temporal information when obtaining the school.
3. FPGA according to claim 2 aids in high-performance calculation method, which is characterized in that source is specially during the school
IRIG-B codes source.
4. FPGA according to any one of claims 1 to 3 aids in high-performance calculation method, which is characterized in that the basis
Temporal information and reference time information during the school are calculated using algorithm during default school and obtain correcting delay signal, and utilizes data
The correcting delay signal is sent to correction device by bus, including：
According to temporal information during the school and reference time information, obtained using algorithm during the school and default punctual algorithm calculating
Take the correcting delay signal and punctual signal；
The correcting delay signal is sent to the correction device using the data/address bus, and the punctual signal is sent to and is kept
When device.
5. FPGA according to claim 4 aids in high-performance calculation method, which is characterized in that it is described according to the school constantly
Between information and reference time information, calculated using algorithm during the school and default punctual algorithm and obtain the correcting delay signal and keep
When signal before, further include：
It is corresponded to according to the system clock and generates the reference time information.
6. a kind of FPGA, which is characterized in that including：
Acquisition module, for from school when source obtain original time data extract and parse, obtain school when temporal information；
Algoritic module, for according to temporal information during the school and reference time information, being obtained using algorithm calculating during default school
Correcting delay signal is taken, and the correcting delay signal is sent to correction device using data/address bus；Wherein, the reference time information is
The temporal information of generation is corresponded to according to system clock.
7. FPGA according to claim 6, which is characterized in that the acquisition module, including：
Receiving submodule, for using predetermined physical interface from the school when source obtain the corresponding level of the original time data
Signal；
Extracting sub-module, for the level signal to be converted into the original time data, and from the original time data
Original time data during middle extraction school；Wherein, original time data are to be calibrated in the original time data during school
Required original time data；
Analyzing sub-module, original time data parse during for the school, temporal information when obtaining the school.
8. FPGA according to claim 7, which is characterized in that the receiving submodule is specifically used for utilizing the default object
It manages interface and obtains the level signal from IRIG-B codes source.
9. according to claim 6 to 8 any one of them FPGA, which is characterized in that the algoritic module, including：
Algorithm submodule, for according to temporal information during the school and reference time information, using algorithm during the school and presetting
Punctual algorithm calculate and obtain the correcting delay signal and punctual signal；
Output sub-module, for the correcting delay signal to be sent to the correction device using the data/address bus, and by described in
Punctual signal is sent to time keeping device.
10. FPGA according to claim 9, which is characterized in that the algoritic module further includes：
With reference to submodule, the reference time information is generated for being corresponded to according to the system clock.
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Application publication date: 20180518 |
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