CN100580608C - Low power reference voltage circuit - Google Patents
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- CN100580608C CN100580608C CN200610126346A CN200610126346A CN100580608C CN 100580608 C CN100580608 C CN 100580608C CN 200610126346 A CN200610126346 A CN 200610126346A CN 200610126346 A CN200610126346 A CN 200610126346A CN 100580608 C CN100580608 C CN 100580608C
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Abstract
The invention comprises: an energy gap reference circuit used for providing a first reference voltage and a data memory used for saving a numerical value according to the first reference voltage; a D/A converter coupled to the data memory and used for providing a second reference voltage according to the numeric value; an output switching unit used for responding a control signal and providing a first reference voltage and a second reference voltage for an output node.
Description
Technical field
The present invention relates to a kind of circuit and method, particularly relate to a kind of low power reference voltage circuit and method with the effect that can reduce power consumption in order to the generation reference voltage.
Background technology
Generally, must be in a stable status, and can avoid, and overall circuit performance is caused negative influence because the variation of temperature and power supply supply makes it produce any variation as employed reference voltage in the memory circuitry.Therefore, in integrated circuit, the energy gap reference voltage generator all can be utilized to produce an internal reference voltage usually.
The principle of work that produces the energy gap reference voltage with sketch under prior art quite similar.The energy gap reference voltage generator is for being used in reference circuits in the integrated circuit widely, and it has an output voltage that is about 1.25V usually, and this output voltage is near the theoretical value of the silicon bandgap of absolute zero.On first resistance, be utilize two voltage differences between the same size diode produce one with the electric current of absolute temperature proportional (PTAT), this electric current is used to produce a PTAT voltage on second resistance, the voltage of diode also can put on second resistance.If the ratio between first resistance and second resistance is selected appropriate, can being fallen by payment of diode voltage then with the interdependent first order influence of temperature and with the voltage of absolute temperature proportional (PTAT), so, then last output voltage is approximately 1.25V; And for general integrated circuit, the variation of its working temperature will make output voltage change the degree of several millivolts (millivolt).
U.S. bulletin patent US6788131 and US5200273 all mention the enforcement circuit of energy gap circuit, this with it as the reference data.
In simple terms, have the weighted sum of the voltage output voltage of positive temperature coefficient (PTC), output voltage can not changed along with temperature by the voltage with negative temperature coefficient (be cross-over connection connect voltage on the face) and one in PN.Yet, wherein,, the energy gap reference voltage generator must be continued to open or activation, so can increase the power consumption of integrated circuit for providing reference voltage to integrated circuit.Therefore, active demand is a kind of has low power reference voltage and produces circuit and method.
Because the shortcoming of said integrated circuit, a kind of low power reference voltage circuit of the present invention's research and development can reach the effect that reduces power consumption.
Summary of the invention
Fundamental purpose of the present invention provides a kind of low power reference voltage circuit, can reach the effect that reduces power consumption.
For achieving the above object, the invention provides a kind of circuit that produces reference voltage, include an energy gap reference circuit, in order to one first reference voltage and a data storage to be provided, and this data storage is to should first reference voltage and store a digital value; And a digital analog converter, be coupled to this data storage, and to should digital value and one second reference voltage is provided.This circuit also includes the output switch unit of at least one controlling signal of a response, in order to an output node is provided this first reference voltage or this second reference voltage.
Also a kind of low power reference voltage of the present invention produces circuit, includes: an energy gap reference circuit, and this energy gap reference circuit provides one first reference voltage according to a controlling signal; One analog-digital converter is coupled to the output terminal of this energy gap reference circuit, and to providing a digital value by first reference voltage; One data buffer is coupled to the output terminal of this analog-digital converter, and stores a digital value; One digital analog converter is coupled to this data storage, and to should digital value providing one second reference voltage; And one output switch unit, this output switch unit includes first switch that couples with the output terminal of this energy gap reference circuit and one and second switch that couples of the output terminal of this digital analog converter, wherein, this first, second switch is to should controlling signal being passed to the output node that this low power reference voltage produces circuit with this first reference voltage when this energy gap reference circuit activation, and behind this energy gap reference circuit anergy this second reference voltage is passed to this output node.
The present invention also provides a kind of generation reference voltage method, comprises the following step: utilize an energy gap reference circuit to produce one first reference voltage; Convert this first reference voltage to a digital signal; This digital signal is converted into one second reference voltage; When a very first time, this first reference voltage is passed to an output node;
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 produces the circuit diagram of circuit for low power reference voltage of the present invention.
Fig. 2 is the sequential chart of various controlling signal among Fig. 1.
Fig. 3 is for providing the enforcement circuit diagram of various controlling signal among Fig. 1.
Fig. 4 is the sequential chart of various controlling signal among Fig. 3.
Fig. 5 is for providing the enforcement circuit diagram of initial signal INI among Fig. 3.
Fig. 6 is the sequential chart of various controlling signal among Fig. 5.
The reference numeral explanation
10 energy gap reference circuits, 100 circuit
110 latch cicuits, 112 first rejection gates
114 first delay cells, 116 second delay cells
118 phase inverters, 120 second rejection gates
12 analog-digital converters, 14 buffers
16 digital analog converters, 18 phase inverters
20 output switch units, 200 circuit
201 resistor assemblies, 202 phase inverters
The M1-M7 transistor
Embodiment
Fig. 1 is embodiments of the invention figure, and as shown in the figure: it is in the operating period of its part energy gap reference circuit 10 to be closed that low power reference voltage of the present invention produces circuit 50, to save power.
Low power reference voltage produces circuit 50 and includes a well-known energy gap reference circuit 10, and the detailed circuit of this energy gap reference circuit 10 is not the technical characterictic of institute of the present invention desire protection.The detailed circuit of energy gap reference circuit 10 with and principle of operation and prior art very similar, and in foregoing " background technology ", description has been arranged, so repeat no more in this.No matter the detailed circuit of elder generation's energy gap reference circuit 10, the output terminal of energy gap reference circuit 10 provide one first temperature and/or the stable reference voltage Vref 1 of power supply supply.Energy gap reference circuit 10 is controlled by energy gap activation/anergy control signal ENBGN, and promptly when the ENBGN signal was high level, energy gap reference circuit 10 was in the state of anergy (closing); And when the ENBGN signal is low level, 10 states that are in activation (unlatching) of energy gap reference circuit, and in its output terminal output voltage V ref1.And when the ENADN signal was high level, analog-digital converter (ADC) 12 was in the state of anergy (cutting out); And when the ENADN signal is low level, 12 states that are in activation (unlatching) of analog-digital converter (ADC) then.
First reference voltage Vref 1 is provided to an analog-digital converter (ADC) 12, in order to first reference voltage Vref 1 is converted into a digital signal.The design and the prior art of most of analog-digital converter (ADC) are very similar, so repeat no more in this.The acuity of conversion or resolution are that the demand tolerance limit according to generating circuit from reference voltage 50 is selected, and is well-known, increases the complexity that resolution will increase single unit system.In one embodiment, analog-digital converter (ADC) 12 is one or four bit pads.
The numeral output of analog-digital converter (ADC) 12 is provided to a data storage, and promptly data buffer 14, in order to store this numeral output.The numeral output of analog-digital converter (ADC) 12 is latched in buffer 14 according to a controlling signal LATCH, the signal that is latched can transfer to a digital analog converter (DAC) 16, and the digital numerical value that latchs in digital analog converter (DAC) the 16 corresponding buffers 14 and export one the simulation second reference voltage Vref 2.As in energy gap reference circuit 50, digital analog converter (DAC) 16 in fact also can not followed the change of temperature and power supply supply voltage and changed.For instance, if the analog output voltage of digital analog converter (DAC) 16 produces by a bleeder mechanism that is connected in stable supply voltage VDD, then it just can not followed temperature and power supply and supplying the change of voltage and change.Suppose that second reference voltage Vref 2 equals VDD*{[R1* (1+aT)]/[R2* (1+aT)] }, wherein R1 and R2 are the resistance value in the bleeder mechanism, " a " is a temperature coefficient, " T " is temperature, because the resistance value of R1 and R2 can be selected, therefore the magnitude of voltage of second reference voltage Vref 2 approximates VDD* (R1/R2), and is not subjected to the influence of temperature change.After during primary power draws high, supply voltage VDD is essentially a fixed value.
Generating circuit from reference voltage 50 includes an output switch unit 20, in order to provide one in fact with the irrelevant output reference voltage Vref-out of temperature and operating voltage fluctuation.In addition, when the ENBGN signal was low level, output reference voltage Vref-out equaled first reference voltage Vref 1; And when the ENBGN signal was high level, output reference voltage Vref-out equaled second reference voltage Vref 2.
As for output switch unit 20, it is essentially one 2 pairs 1 switchs, and when energy gap reference circuit 10 activations (unlatching), it is passed to output node 22 with first reference voltage Vref 1; (during energy gap reference circuit 10 anergies (closing), it is passed to output node 22 with second reference voltage Vref 2 when energy gap reference circuit 10 no longer includes the output running.Output switch unit 20 includes two groups of complementary metal oxide semiconductor (CMOS)s (CMOS) transfer gate of being made up of four metal-oxide semiconductor (MOS)s (MOS) transistor M1-M4.Transistor M1, M2 are in parallel, and its each first link all is coupled to one with the output terminal of digital analog converter (DAC) 16, and respectively second link all is coupled to one with the output node 22 of generating circuit from reference voltage 50.The gate terminal of nmos pass transistor M1 is connected with controlling signal ENBGN, and the gate terminal of PMOS transistor M2 is connected with controlling signal/ENBGN via a phase inverter 18.Therefore, when controlling signal ENBGN is in high level, second reference voltage is passed to output node 22 as the transistor M1, the M2 that are switch.Though the switch among the figure is shown as the CMOS switch, but the switch of other kind can also be used in the present invention, as the similar device or the like of independently NMOS or PMOS device, a pair of NMOS or PMOS device or other, in order to optimal reception controlling signal ENBGN or/ENBGN.
Transistor M3, M4 are in parallel, and its each first link all is coupled to one with the output terminal (i.e. first reference voltage Vref 1) of energy gap reference circuit 10, and respectively second link all is coupled to one with the output node 22 of generating circuit from reference voltage 50.The gate terminal of nmos pass transistor M3 is connected with controlling signal/ENBGN, and PMOS transistor M4 gate terminal is connected with controlling signal ENBGN.Therefore, being used as is that transistor M3, the M4 of switch is passed to output node 22 with first reference voltage when controlling signal ENBGN is in low level.
Fig. 2 is each the controlling signal sequential chart in Fig. 1 generating circuit from reference voltage 50, as shown in the figure: when time during in T0, generating circuit from reference voltage 50 promptly is unlocked, and is well-known, and power supply supply voltage VDD can just can reach a stable level (stable state) behind length; When the time is between T0 and T1, power supply supply voltage VDD can promote a burning voltage level so far, during this period, controlling signal ENBGN and ENADN are low level, and output node 22 couples with the energy gap reference circuit 10 of opening (activation) via two CMOS transistor M3, M4.When time during in T1, power supply supply voltage VDD can reach a burning voltage level.When the time was between T1 and T2, power supply supply voltage VDD promptly was in a burning voltage level, and controlling signal ENBGN and ENADN still are in low level, and 12 of energy gap reference circuit 10 and analog-digital converters (ADC) can be opened (activation).First reference voltage Vref 1 that is produced via energy gap reference circuit 10 can be transferred to the combination of transistor switch M3, M4, and transistor M3, M4 be unlatching, and first reference voltage Vref 1 is passed to output node 22.
When time during in T2, promptly along with power supply supply voltage VDD stable after, first reference voltage Vref 1 also reaches the time point of a burning voltage level, and controlling signal LATCH can become high level, and control buffer 14 latchs the output data storage of analog-digital converter (ADC) 12 in it.The data that are stored in the buffer 14 are transferred to a digital analog converter (DAC) 16 subsequently to convert an aanalogvoltage to, i.e. second reference voltage Vref 2.When time during in T3, controlling signal LATCH can become low level, and controlling signal ENBGN and ENADN are transformed into high level.Thus, energy gap reference circuit 10 and analog-digital converter (ADC) 12 promptly can cut out (anergy), and transistor M3, M4 can be closed simultaneously, makes 22 formation of energy gap reference circuit 10 and output node open circuit.Yet transistor M1, M2 can be unlocked this moment, in order to second reference voltage Vref 2 is passed to output node 22.Clearly,, indicate among Fig. 2 that sequence characteristics is all identical at that time, so only use a controlling signal wherein also can reach identical control purpose although controlling signal ENBGN and ENADN are two different signals.Control analog-digital converter (ADC) 12 and energy gap reference circuit 10 no matter whether utilize identical or different controlling signal, controlling signal all should meet following condition: controlling signal ENBGN must remain low level, till obtaining second reference voltage Vref 2; And controlling signal ENADN only needs to remain on low level, till buffer 14 is lived the output data latch of analog-digital converter (ADC) 12.
As previously mentioned, can learn that energy gap reference circuit 10 promptly can be closed (anergy) when the time is after T3.Although energy gap reference circuit 10 is in the state of closing (anergy), generating circuit from reference voltage 50 can produce an output voltage V ref-out, promptly temperature independent second (energy gap) reference voltage Vref 2 in output node 22.Second reference voltage Vref 2 equals first reference voltage Vref 1 in fact, and its accuracy is determined by some controllable parameter, as the accuracy of analog-digital converter (ADC) 12 samplings and the accuracy of digital analog converter (DAC) 16 conversions.After time T 3, the power consumption of output switch unit 20 and digital analog converter (DAC) 16 can be less than the power consumption of energy gap reference circuit 10.Therefore, compare with existing generating circuit from reference voltage 10, generating circuit from reference voltage 50 of the present invention is a low-power energy gap reference voltage generator.
Under special applications and design, time T 0 to T1 (power supply supply voltage VDD can promote a burning voltage level so far during) generally is about hundreds of microseconds between some milliseconds; Time T 1 to T2 must be set at one section time enough, can make energy gap reference circuit 10 that stable first reference voltage Vref 1 is provided and 12 pairs first reference voltage Vref 1 of analog-digital converter (ADC) are taken a sample.Have a plurality of detecting devices in many circuit are equal, whether reached stable state in order to judge power supply supply voltage.For instance, DRAM (dynamic RAM) controller just can provide a plurality of periodic renewals (refresh) instruction after detecting power supply supply voltage and having reached stable state.Operating in all chips that power supply supply voltage reached stable state all can produce some instruction signals and represent that power supply supply voltage has reached stable state, these circuit all can utilize generating circuit from reference voltage 50 of the present invention that reference voltage is provided, and utilize some internal control signals or its controlling signal of deriving to control generating circuit from reference voltage 50 of the present invention.
Fig. 3 is for providing the enforcement circuit diagram of various controlling signal among Fig. 1, as shown in the figure: circuit 100 includes an output circuit, this output circuit has the transistor of pair of series, promptly supply between voltage VDD and second voltage node (ground connection), and be coupled to nmos pass transistor M5 and the PMOS transistor M6 of node A in being disposed at power supply.Circuit 100 also includes a latch cicuit 110 that is coupled to node A, and this latch cicuit 110 has a pair of phase inverter that couples alternately.Node A is coupled to one the one NOR (or non-) door, 112 and first delay cell 114.First delay cell 114 can be any assembly that is designed to provide a fixed delay, as a series of phase inverter.The output of first delay cell 114 is as the input of one the 2nd NOR (or non-) door, 120 and second delay cell 116, and the output of second delay cell 116 is as the input of a NCR (or non-) door 112, and via the input of a phase inverter 118 as the 2nd NOR (or non-) door 120.The 2nd NOR (or non-) door 120 will be exported controlling signal LATCH, and a NOR (or non-) door 112 will be exported controlling signal ENBGN.
Second delay cell, 116 usefulness decide the pulse width of controlling signal LATCH, and first delay cell, 114 usefulness decide controlling signal LATCH when to start.The total delay time that adds of first delay cell 114 and second delay cell 116 is set at a time enough is provided, make analog-digital converter (ADC) 12 and digital analog converter (DAC) 16 finish the operation of itself, and when decision controlling signal ENBGN start.
The gate terminal of PMOS transistor M5 receives an initial signal INI, and the gate terminal of nmos pass transistor M6 receives one and upgrades signal Refresh_CMD.Fig. 4 is the sequential chart of various controlling signal among Fig. 3, and as shown in the figure: when initial signal INI was low level, node A was a high level; And as initial signal INI and when upgrading signal Refresh_CMD and being high level, node A then is a low level.
When power supply supply voltage stablize, renewal signal Refresh_CMD was used for update cycle of flip-flop storage unit by the DRAM circuit.Therefore, this renewal signal Refresh_CMD can be used to indicate power supply supply voltage whether to reach stable.When time during in T0, power supply supply voltage VDD is about to begin to rise to the action of a steady state (SS), initial signal INI and upgrade signal Refresh_CMD and then remain on low level.As initial signal INI and when upgrading signal Refresh_CMD and being low level, PMOS transistor M5 is unlocked and nmos pass transistor M6 is closed, and transfers to node A and supply voltage VDD with power supply.Before time T 1, initial signal INI becomes high level, in order to transistor M5 is closed.110 numerical value with node A of latch cicuit (having reached the degree of power supply supply voltage VDD) are taken a sample, and preserve this numerical value till having other to trigger.When time during in T1, power supply supply voltage VDD promptly reaches the level of steady state (SS), and subsequently, when the time was between T1 and T2, one first was upgraded signal Refresh_CMD and promptly produced (surplus time T x) by the DRAM circuit.This first upgrades signal Refresh_CMD nmos pass transistor M6 is opened, and when time T x with node A ground connection.When this first renewal signal Refresh_CMD finishes, nmos pass transistor M6 will close, but latch cicuit 110 can make node A remain on the level of ground connection.This low level signal can transfer to the first input end of a NOR (or non-) door 112, and through first delay cell 114 and second delay cell 116 add total delay (D1+D2) after, transfer to second input end of a NOR (or non-) 112 again.The time that adds total delay (D1+D2) equals the time of time T x to T3, and D1 time delay of first delay cell 114 can determine the start-up time of controlling signal LATCH, and D2 time delay of second delay cell 116 can determine the time span of controlling signal LATCH.
Fig. 5 is for providing the circuit diagram of initial signal INI, Fig. 6 is the sequential chart of various controlling signal among Fig. 5, as shown in the figure: circuit 200 includes a PMOS transistor M7 who is coupled between power supply supply voltage VDD and node Vn, and gate terminal and its drain electrode end of PMOS transistor M7 are coupled to node Vn; One resistor assembly 201 is coupled between node Vn and the ground; And a pair of series connection phase inverter 202 that initial signal INI is provided and is coupled to node Vn.If do not use phase inverter 202, then initial signal INI equals the voltage of node Vn, i.e. VDD-Vth (M7).Phase inverter 202 usefulness are so that initial signal INI is promoted to power supply supply voltage VDD (promptly when the voltage of node Vn during greater than Vth (phase inverter 202), initial signal INI is promoted to the degree that power supply is supplied voltage VDD).In Fig. 6, when the time was T0, power supply supply voltage VDD began to promote, and reached steady state (SS) during for T1 in the time, and PMOS transistor M7 is unlocked in the time is T0 during the Ty, and electric current will begin to flow through transistor M7 and resistor assembly 201.The voltage follow power supply of node Vn supply voltage VDD and reach the level of a VDD-Vth (M7).The initial voltage INI of output all maintains low level at (promptly when the voltage of node Vn high before make phase inverter 202 judgements it reaches the degree of level " 1 ") before the time T y.When the time was after T1, power supply supply voltage VDD arrived steady state (SS), and initial signal INI can remain in the level of logical one.
According to the above, a kind of implementation method that produces reference voltage comprises the following step:
(i) open an energy gap reference circuit and export a reference voltage (Vref1) to output node from the energy gap reference circuit;
Wait for that (ii) power supply supply voltage VDD arrives a steady state (SS);
(iii) convert reference voltage (Vref1) to digital signal;
(iv) digital signal is latched and converts thereof into is an analog reference voltage (Vref2);
(v) the energy gap reference circuit is closed and reference voltage (Vref2) is coupled to output node; And
(vi) output voltage is maintained the level of reference voltage (Vref2).
Generating circuit from reference voltage 50 can be used in multiple application, uses the reference voltage that is essentially certain value as needs, and this reference voltage is all to be in the application that can not change along with temperature and power supply supply voltage.For instance, generating circuit from reference voltage 50 can provide a reference voltage by the adjuster of chip internal; In other embodiments, generating circuit from reference voltage 50 also can provide reference voltage to dram chip.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; those skilled in the art can do some changes and retouching under the premise without departing from the spirit and scope of the present invention, so protection scope of the present invention is as the criterion with claim of the present invention.
Claims (10)
1, a kind of low power reference voltage produces circuit, includes:
One energy gap reference circuit, this energy gap reference circuit provides one first reference voltage;
One data storage, this data storage is to should first reference voltage and store a digital value;
One digital analog converter is coupled to this data storage, and to should digital value providing one second reference voltage; And
One output switch unit corresponding at least one controlling signal, one of them is passed to an output node to this output switch unit with this first reference voltage and this second reference voltage according to this controlling signal,
Wherein, this controlling signal is one to make the signal of activation of described energy gap reference circuit or anergy, can make this energy gap reference circuit through between a first phase and anergy, and this output node back between this first phase couples with this second reference voltage.
2. the low power reference voltage according to claim 1 produces circuit, can further comprise one and be coupled to the output terminal of this energy gap reference circuit and the analog-digital converter between this data storage.
3. the low power reference voltage according to claim 2 produces circuit, and wherein, this data storage comprises a data buffer that is connected with another controlling signal.
4. produce circuit according to the low power reference voltage of claim 1, wherein, this output switch unit comprises first and second switch that is connected in this controlling signal, and this controlling signal is one to make the signal of activation of described energy gap reference circuit or anergy.
5. the low power reference voltage according to claim 4 produces circuit, wherein, this first switch is passed to this output node with this first reference voltage when this energy gap reference circuit activation, this second switch is passed to this output node with this second reference voltage when this energy gap reference circuit anergy.
6. a low power reference voltage produces circuit, includes:
One energy gap reference circuit, this energy gap reference circuit provides one first reference voltage according to a controlling signal;
One analog-digital converter is coupled to the output terminal of this energy gap reference circuit, and to providing a digital value by first reference voltage;
One data buffer is coupled to the output terminal of this analog-digital converter, and stores a digital value;
One digital analog converter is coupled to this data storage, and to should digital value providing one second reference voltage; And
One output switch unit, this output switch unit includes first switch that couples with the output terminal of this energy gap reference circuit and one and second switch that couples of the output terminal of this digital analog converter, wherein, this first, second switch is to should controlling signal being passed to the output node that this low power reference voltage produces circuit with this first reference voltage when this energy gap reference circuit activation, and behind this energy gap reference circuit anergy this second reference voltage is passed to this output node.
7. the low power reference voltage according to claim 6 produces circuit, wherein, this energy gap reference circuit operates under the power supply supply voltage, this power supply supply voltage is in reach stable state after a very first time, wherein, this data buffer will be fastened pinning from the digital value that this analog-digital converter is exported when this very first time.
8. one kind produces the reference voltage method, comprises the following step:
Utilize an energy gap reference circuit to produce one first reference voltage;
Convert this first reference voltage to a digital signal;
This digital signal is converted into one second reference voltage;
When a very first time, this first reference voltage is passed to an output node;
And after this very first time, make this energy gap reference circuit produce anergy and also this second reference voltage is passed to this output node.
9. generation reference voltage method according to Claim 8, wherein, the step that this digital signal converts this second reference voltage to comprises the step that the digital signal that this digital signal is stored and will store transfers to a digital analog converter.
10. generation reference voltage method according to Claim 8, wherein, this is changed this first reference voltage step and comprises the step that this first reference voltage is transferred to an analog-digital converter.
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| CN200610126346A CN100580608C (en) | 2006-08-30 | 2006-08-30 | Low power reference voltage circuit |
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| CN200610126346A CN100580608C (en) | 2006-08-30 | 2006-08-30 | Low power reference voltage circuit |
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| CN100580608C true CN100580608C (en) | 2010-01-13 |
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| CN107342676B (en) * | 2017-07-26 | 2019-03-12 | 成都市易冲半导体有限公司 | A kind of method and system of control power bridge output |
| CN110070815B (en) * | 2018-01-22 | 2022-08-12 | 矽创电子股份有限公司 | Reference voltage generator for display device |
| CN108153365B (en) * | 2018-02-02 | 2024-03-26 | 深圳市天微电子股份有限公司 | High-matching high-precision voltage difference generating circuit |
| TWI749555B (en) * | 2019-05-16 | 2021-12-11 | 矽創電子股份有限公司 | Reference voltage generating circuit |
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