CN100578599C - Shifting register and level controller thereof - Google Patents
Shifting register and level controller thereof Download PDFInfo
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- CN100578599C CN100578599C CN200710102139A CN200710102139A CN100578599C CN 100578599 C CN100578599 C CN 100578599C CN 200710102139 A CN200710102139 A CN 200710102139A CN 200710102139 A CN200710102139 A CN 200710102139A CN 100578599 C CN100578599 C CN 100578599C
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Abstract
The invention relates to a shift register provided with a multilevel shift register unit. Each level shift register unit comprises a first level increasing unit and a first level decreasing unit, a first driving unit and a level controller. The first level increasing unit and the decreasing unit and the driving unit are respectively used for leading a scanning signal to be equal to a first time-sequence signal and a first voltage and to be communicated with the first level increasing unit. The level controller comprises an input unit, a charge storing unit, a second level increasing unit and a second level decreasing unit. The input unit is used for controlling a first control signal on a knot to be equal to the first voltage. The charge storing unit is used for storing the voltage of time-sequence signal corresponding to the knot. The second level increasing and the second level decreasing units are respectively used for controlling a second control signal to be equal to the first control signal and the first voltage to respectively communicate with and cut off the first level decreasing unit.
Description
Technical field
The present invention relates to a kind of shift register (Shift Register), particularly relates to a kind of shift register that carries out the level controller of level control operation via the charge storage capacity of electric capacity that has.
Background technology
In the epoch now that development in science and technology is maked rapid progress, LCD has been widely used in electronics and has shown on the product, as TV, computer screen, mobile computer, mobile phone or personal digital assistant etc.LCD comprises data driver (Data Driver), scanner driver (Scan Driver) and display panels, wherein has pel array in the display panels, and scanner driver is in order to pixel column corresponding in the on-pixel array in regular turn, be sent to pixel with pixel data, and then demonstrate the image that desire shows data driver output.
Technology now is many to realize out the driver that scans of pixel column corresponding in the on-pixel array in regular turn with shift register (Shift Register), and designs level controller 100 in the shift register cell circuit at different levels with the transistor that two length breadth ratios (W/L Ratio) differ greatly.As shown in Figure 1, wherein the length breadth ratio of transistor T 5 ' is about ten times of length breadth ratio of transistor T 4 ', and transistor T 4 ' biased be diode (Diode).So, level controller 100 can produce the output signal Vg anti-phase each other with it in response to input signal Vs.
Yet, because the length breadth ratio of transistor T 4 ' is less, need bear when its conducting so that transistor T 5 ' produces electric current greatly.So, will make transistor T 4 ' produce corrupted, cause shift register cell generation misoperation and make the life-span of LCD shorter.Therefore how designing the level controller and the shift register of long service life, is one of direction of being endeavoured of industry with the serviceable life that promotes LCD and image quality thereof.
Summary of the invention
The invention relates to a kind of shift register (Shift Register), it can improve short shortcoming of traditional shift register life-span effectively, and it is longer to have serviceable life in fact, and can make the advantage of long and display frame better quality in serviceable life of the LCD of using it.
A kind of shift register is proposed according to the present invention, comprise the multi-stage shift register unit, shift register cells at different levels scan signal in order to produce, and shift register cell at different levels comprises that the first level lift unit, first level drag down unit, first driver element and level controller.The first level lift unit equals the first sequential signal in order to the gated sweep signal, and first level drags down the unit and equals first voltage in order to the gated sweep signal.First driver element provides first controlling signal to come the conducting first level lift unit in order to the rising edge (Rising Edge) in response to input signal.Level controller comprises that input block, electric charge storage unit, the second level lift unit and second level drag down the unit.Input block comes the 3rd controlling signal on the Control Node to equal first voltage in response to the rising edge of first controlling signal.The two ends of electric charge storage unit are coupled to node respectively and receive one second sequential signal, and it is in order to store the voltage of sequential signal with respect to node.The second level lift unit is controlled second controlling signal in response to the rising edge of the 3rd controlling signal and is equaled the 3rd controlling signal in fact and drag down the unit with conducting first level.Second level drags down cell response and controls second controlling signal in the rising edge of the 3rd controlling signal and equal first voltage to drag down the unit by first level.Wherein, input signal is the scanning signal of the previous stage shift register cell output of each shift register cell.
Propose a kind of level controller according to the present invention, comprise that input block, electric charge storage unit, level lift unit and level drag down the unit.Input block comes the controlling signal on the Control Node to equal first voltage in order to the rising edge in response to input signal.The two ends of electric charge storage unit are coupled to node respectively and receive the sequential signal, and it is in order to store the voltage of sequential signal with respect to node.The level lift unit provides first signal to output terminal in order to the rising edge in response to controlling signal, and first signal is in fact near controlling signal.Level drags down the unit and comes the output signal on the control output end to equal first voltage in order to the rising edge in response to input signal.
For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
Description of drawings
Fig. 1 shows the circuit diagram according to traditional shift register cell.
Fig. 2 shows the calcspar according to the shift register of first embodiment of the invention.
Fig. 3 shows the detailed circuit diagram of first embodiment of the shift register cell S (n) of Fig. 2.
4A shows the related signal sequential chart of shift register cell S (n) among Fig. 3.
4B shows the signal analogous diagram of controlling signal Vc2 (n) and Vc3 (n) among Fig. 3.
Fig. 5 shows the detailed circuit diagram of second embodiment of the shift register cell of Fig. 2.
Fig. 6 shows the detailed circuit diagram of the 3rd embodiment of the shift register cell of Fig. 2.
Fig. 7 shows the detailed circuit diagram of the 4th embodiment of the shift register cell of Fig. 2.
Fig. 8 shows the detailed circuit diagram of the 5th embodiment of the shift register cell of Fig. 2.
Fig. 9 shows the detailed circuit diagram of the 6th embodiment of the shift register cell of Fig. 2.
Figure 10 shows the detailed circuit diagram of the 7th embodiment of the shift register cell of Fig. 2.
Figure 11 shows the detailed circuit diagram of the 8th embodiment of the shift register cell of Fig. 2.
Figure 12 shows the detailed circuit diagram of the 9th embodiment of the shift register cell of Fig. 2.
Figure 13 shows the calcspar according to the shift register of second embodiment of the invention.
Figure 14 shows the detailed circuit diagram of first implementation method of the shift register cell of Figure 13.
Figure 15 shows the detailed circuit diagram of second embodiment of the shift register cell of Figure 13.
Figure 16 shows the detailed circuit diagram of the 3rd embodiment of the shift register cell of Figure 13.
Figure 17 shows the detailed circuit diagram of the 4th embodiment of the shift register cell of Figure 13.
Figure 18 shows the detailed circuit diagram of the 5th embodiment of the shift register cell of Figure 13.
Figure 19 shows the detailed circuit diagram of the 6th embodiment of the shift register cell of Figure 13.
Figure 20 shows the detailed circuit diagram of the 7th embodiment of the shift register cell of Figure 13.
Figure 21 shows the detailed circuit diagram of the 8th embodiment of the shift register cell of Figure 13.
Figure 22 shows the detailed circuit diagram of the 9th embodiment of the shift register cell of Figure 13.
Figure 23 shows the detailed circuit diagram of the tenth embodiment of the shift register cell of Figure 13.
Figure 24 shows the detailed circuit diagram of the tenth embodiment of the shift register cell of Fig. 2.
Figure 25 shows the detailed circuit diagram of the 11 embodiment of the shift register cell of Fig. 2.
Figure 26 shows the detailed circuit diagram of the 12 embodiment of the shift register cell of Fig. 2.
Figure 27 shows the detailed circuit diagram of the 13 embodiment of the shift register cell of Fig. 2.
Figure 28 shows the detailed circuit diagram of the 11 embodiment of the shift register cell of Figure 13.
Figure 29 shows the detailed circuit diagram of the 12 embodiment of the shift register cell of Figure 13.
Figure 30 shows the detailed circuit diagram of the 13 embodiment of the shift register cell of Figure 13.
The reference numeral explanation
100,204: level controller
T4 ', T5 ', T1～T12, T3 ', T6 ': transistor
10,20: shift register
S (1)～S (m), S1 (n)～S13 (n), U (1)～U (m), U1 (n)～U13 (n): shift register cell
202: driver element
206: the level lift unit
208: level drags down the unit
C: electric capacity
NT1～NT3: node
Embodiment
First embodiment
Please refer to Fig. 2, it shows the calcspar according to the shift register of first embodiment of the invention.Shift register 10 comprises m shift register cell S (1)～S (m) that is one another in series and connects, and it for example has equal structure.In the present embodiment, shift register cell S (1)～S (m) comprises input end IN, output terminal OUT, control end RT, node NT1, sequential end C and sequential end CB.The input end IN of shift register cell S (1) receives start signal STV, and the input end IN of shift register cell S (2)～S (m) receives scanning signal Vo (1)～Vo (m-1) that the output terminal OUT of previous stage shift register is exported in regular turn.
The activation time of the sequential signal that wantonly two adjacent sequential end C receive among shift register cell S (1)～S (m) staggers mutually, the activation time of the sequential signal that sequential end CB receives also staggers mutually, and the activation time of the sequential signal that the sequential end C of the sequential end CB of n level shift register cell S (n) and n+1 level shift register cell S (n+1) receives also staggers mutually, and n is a natural number.Present embodiment receives sequential signal CLK and CLKB respectively with the sequential end C and the CB of odd level shift register cell among shift register cell S (1)～S (m), and the sequential end C of even level shift register cell and CB receives sequential signal CLKB respectively and CLK is that example explains wherein.In the present embodiment, sequential signal CLKB and the sequential signal CLK of this moment are anti-phase signal for example for staggering the activation time of the activation time of sequential signal CLKB and sequential signal CLK.
The control end RT of shift register cell S (1)～S (m-1) receives the voltage signal of node NT1 of shift register cell S (2)～S (m) respectively with as controlling signal Vc1 (1)～Vc1 (m-1).Next, be that the numerous embodiments that example is enumerated the shift register cell S (n) of present embodiment explains with n level shift register cell S (n) among shift register cell S (1)～S (m).
First embodiment
Please refer to Fig. 3, it shows the detailed circuit diagram of first embodiment of the shift register cell S (n) of Fig. 2.The shift register cell S1 (n) of this enforcement comprises that driver element 202, level controller 204, level lift unit 206 and level drag down unit 208.This implementation method drags down unit 208 with level lift unit 206, level and driver element 202 comprises that respectively transistor T 1, T2, T3 and T4～T6 are that example explains, and transistor T 1～T6 for example be N type thin film transistor (TFT) (Thin FilmTransistor, TFT).
The grid of transistor T 1 (Gate) is coupled to node NT1, and to receive controlling signal Vc1 (n), drain electrode (Drain) receives sequential signal CLK, and source electrode (Source) is coupled to output terminal OUT.Transistor T 1 comes gated sweep signal Vo (n) to equal sequential signal CLK in response to controlling signal Vc1 (n).The grid of transistor T 2 is coupled to node NT2 to receive controlling signal Vc2 (n), and drain electrode is coupled to output terminal OUT, and source electrode receives voltage VSS.The grid of transistor T 3 receives the controlling signal Vc1 (n+1) of n+1 level shift register cell S1 (n+1), and drain electrode is coupled to output terminal, and source electrode receives voltage VSS.Transistor T 2 and T3 come gated sweep signal Vo (n) to equal voltage VSS in response to controlling signal Vc2 (n) and Vc1 (n+1) respectively.The voltage VSS of present embodiment for example is the minimum voltage of shift register 10.
The grid of transistor T 4 receives the scanning signal Vo (n-1) that n-1 level shift register cell S1 (n-1) exports with drain electrode, and source electrode is coupled to node NT1.Transistor T 4 is controlled the high level of controlling signal Vc1 (n) approaching scanning signal Vo (n-1) with turn-on transistor T1 in response to the rising edge (Rising Edge) of scanning signal Vo (n-1).The high level of scanning signal Vo (n-1) for example equals the level of voltage VDD, and it for example is the ceiling voltage of shift register 10.
The grid of transistor T 5 and T6 receives the controlling signal Vc1 (n+1) of controlling signal Vc2 (n) and n+1 level shift register cell S1 (n+1) respectively, and drain electrode is coupled to node NT1, and the source electrode of transistor T 5 and T6 receives voltage VSS and sequential signal CLK respectively.Transistor T 5 and T6 control controlling signal Vc1 (n) in response to the rising edge of controlling signal Vc2 (n) and controlling signal Vc1 (n+1) respectively and equal voltage VSS, with "off" transistor T1.
One end of capacitor C is coupled to node NT3, and the other end receives sequential signal CLK, and capacitor C is in order to store the voltage of sequential signal CLK with respect to node NT3.The grid of transistor T 8 receives controlling signal Vc3 (n), and drain electrode receives sequential signal CLK, and source electrode is coupled to node NT2.Transistor T 8 is in response to the rising edge control controlling signal Vc2 (n) of controlling signal Vc3 (n), and the voltage level of Vc2 this moment (n) drags down unit 208 near the voltage level of controlling signal Vc3 (n) with conduction level.The grid of transistor T 9 receives controlling signal Vc1 (n), and drain electrode is coupled to node NT2, and source electrode receives voltage VSS.Transistor T 9 equals voltage VSS in order to control controlling signal Vc2 (n) in response to the rising edge of controlling signal Vc1 (n), drags down unit 208 with cut-off level.
Please refer to Fig. 4 A, it shows the related signal sequential chart of shift register cell S1 (n) among Fig. 3.Output signal Vo (n-1) equals voltage VDD with sequential signal CLKB in period of time T P1, and sequential signal CLK and controlling signal Vc1 (n+1) equal voltage VSS.This moment, transistor T 3 and T5 and T6 ended, and transistor T 4 conductings also make transistor T 1 conducting, made scanning signal Vo (n) equal sequential signal CLK voltage VSS.Transistor T 4 makes controlling signal Vc1 (n) equal Vc1 (n)=VDD-Vth1, with turn-on transistor T7 and T9, makes controlling signal Vc2 (n) and Vc3 (n) be equal to voltage VSS, with "off" transistor T2.This moment, the cross-pressure at capacitor C two ends equalled zero in fact.Vth1 is the critical voltage of transistor T 1.
Output signal Vo (n-1) and sequential signal CLKB equal voltage VSS in period of time T P2, and controlling signal Vc1 (n+1) and sequential signal CLK are near voltage VDD.This moment, transistor T 4～T6 ended, and making node NT1 is suspension joint (Floating).Sequential signal CLK equals voltage VDD by voltage VSS lifting in period of time T P2, this significantly change in voltage will make voltage signal Vc1 (n) further promote a difference voltage Δ V because of raising effect (Boot-Strapping), make voltage signal Vc1 (n) equal Vc1 (n)=VDD-Vth1+ Δ V.In this enforcement structure, difference voltage Δ V equals:
Wherein Cgs is the endophyte electric capacity of transistor T 1, and the equivalent capacity that Cp1 sees for node NT1.This moment, controlling signal Vc2 (n), Vc3 (n) and Vc1 (n+1) were equal to voltage VSS, and with "off" transistor T8, T2 and T3, and transistor T 1 makes scanning signal Vo (n) rapid charge to voltage VDD.This moment capacitor C two ends cross-pressure poor near voltage VDD and VSS.
In period of time T P3, controlling signal Vc1 (n+1) and sequential signal CLKB are near voltage VDD, and output signal Vo (n-1) and sequential signal CLK equal voltage VSS.Transistor T 6 conductings this moment, so that controlling signal Vc1 (n) equals voltage VSS, and "off" transistor T1, T7 and T9.And the falling edge of sequential signal CLK will make capacitor C discharge, and the level that makes controlling signal Vc3 (n) after forming surging in fact near the level of sequential signal CLK, that is be voltage VSS, transistor T 8 is ended.The cross-pressure at capacitor C two ends is near zero volt at this moment.This moment, node NT2 was essentially suspension joint, and controlling signal Vc2 (n) equals voltage VSS, with "off" transistor T2.
In sequential period T P4, sequential signal CLK is near voltage VDD, and controlling signal Vc1 (n+1), output signal Vo (n-1) and sequential signal CLKB equal voltage VSS.Transistor T 1, T4, T7 and T9 end constantly at this moment, and transistor T 3, T6 end for transferring to.And the rising edge of sequential signal CLK also will make controlling signal Vc3 (n) in fact near the level of sequential signal CLK, that is be voltage VDD, with turn-on transistor T8, make controlling signal Vc2 (n) in fact near controlling signal Vc3 (n), that is near voltage VDD.So, transistor T 2 conductings are so that scanning signal Vo (n) equals voltage VSS.
Please refer to Fig. 4 B, it shows the signal analogous diagram of controlling signal Vc2 (n) and Vc3 (n) among Fig. 3.In Fig. 3 B, the length breadth ratio of transistor T 7～T9 (W/L Ratio) for example equals 50/5, and capacitor C for example equals 0.5 micromicrofarad (Pico Farad).By above narration as can be known, the shift register cell S1 (n) of present embodiment can make scanning signal Vo (n) equal voltage VSS via level controller 204 produces high level in sequential period T P4 controlling signal Vc2 (n) turn-on transistor T4, reaches the operation of shift register cell S1 (n).Because the level controller 204 of present embodiment provides with it each other in fact reverse controlling signal Vc2 (n) with the interaction of sequential signal CLK is next in response to controlling signal Vc1 (n) via the operation that discharges and recharges of capacitor C.So, the level controller 204 of the present embodiment level controller 100 that can improve effectively in traditional shift register cell does not cause transistor T 4 ' to bear the problem of too high electric current corrupted because of the size of transistor T 4 ' and T5 ' matches.
Controlling signal Vc2 in the present embodiment (n) equals voltage VDD in the time cycle beyond sequential period T P1～TP3 constantly, come gated sweep signal Vo (n) to equal voltage VSS with turn-on transistor T2, be subjected to the scanning motion of scanner driver that noise causes using the shift register device 10 of present embodiment and make a mistake to avoid scanning signal Vo (n).Yet long-time conducting will make the easy stress effect of critical voltage (Stress Effect) of transistor T 2 and promote and generation misoperation (Malfunction).Transistor T 3 in the present embodiment more can drag down scanning signal Vo (n) to voltage VSS when transistor T 2 produces misoperation, make a mistake with the level of avoiding scanning signal Vo (n).
Be provided with level controller in the shift register of present embodiment, its operation that discharges and recharges via electric capacity provides and its reverse in fact each other controlling signal in response to controlling signal with the interaction of sequential signal is next.So, the level controller of present embodiment and shift register can improve transistor in the level controller effectively easily because of do not match corrupted, traditional shift register of circuit is easy to generate misoperation and uses its LCD short shortcoming in serviceable life, and size coupling and transistor are difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it each other and have transistor in fact.
Second embodiment
Please refer to Fig. 5, it shows the detailed circuit diagram of second embodiment of the shift register cell of Fig. 2.Shift register cell S1 (n) difference in the shift register cell S2 (n) of present embodiment and first embodiment is that the drain electrode of capacitor C and transistor T 8 is to receive sequential signal CLKB.Because sequential signal CLKB and CLK be for anti-phase in fact, that is be that the phase place 180 of the backward in fact sequential signal CLK of phase place (Phase) of sequential signal CLKB is spent.So, the waveform delay half period of the corresponding controlling signal of the waveform of the controlling signal Vc3 of present embodiment (n) and Vc2 (n) in first embodiment.
So, the level controller 204 of present embodiment also has transistor in fact size coupling and transistor is difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it each other.
The 3rd embodiment
Please refer to Fig. 6, it shows the detailed circuit diagram of the 3rd embodiment of the shift register cell of Fig. 2.Shift register cell S1 (n) difference in the shift register cell S3 (n) of present embodiment and first embodiment is that level drags down unit 208 and also comprises transistor T 10, grid receives sequential signal CLKB, drain electrode is coupled to output terminal OUT, and source electrode receives voltage VSS.Transistor T 10 equal conductings in sequential period T P1 and TP3 are so that scanning signal Vo (n) equals voltage VSS.So, the level of present embodiment drags down unit 208 also can drag down scanning signal Vo (n) via transistor T 10 in sequential period T P1 and TP3, guaranteeing that scanning signal Vo (n) remains on low level in sequential period T P1 and TP2, and avoid it to be subjected to the circuit noise influence and promote and be high level.So, the shift register cell S3 (n) of present embodiment except have transistor each other size coupling and transistor be difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it, also have and can reduce that scanning signal Vo (n) is subjected to the influence of circuit noise and advantage that level errors takes place.
The 4th embodiment
Please refer to Fig. 7, it shows the detailed circuit diagram of the 4th embodiment of the shift register cell of Fig. 2.The shift register cell S4 (n) of present embodiment is the embodiment of deriving of the shift register S3 (n) in the 3rd embodiment, and its difference is that the drain electrode of the transistor T 8 in the 3rd embodiment and the sequential signal CLK that capacitor C receives change to sequential signal CLKB.So, the operation of the shift register cell S4 (n) of present embodiment can be analogized according to the narration in second embodiment and obtained.
The 5th embodiment
Please refer to Fig. 8, it shows the detailed circuit diagram of the 5th embodiment of the shift register cell of Fig. 2.Shift register S3 (n) difference in the shift register cell S5 (n) of present embodiment and the 3rd embodiment is that driver element 202 also has transistor T 11, grid receives sequential signal CLKB, drain electrode is coupled to node NT1, and source electrode receives scanning signal Vo (n-1).Transistor T 11 conductings in sequential period T P3 are so that controlling signal Vc1 (n) equals voltage VSS.So, driver element corresponding in the driver element 202 of present embodiment and the 3rd embodiment has close in fact operation, equals voltage VSS to make controlling signal Vc1 (n) in sequential period T P3.
So, the level controller 204 of present embodiment also has transistor in fact size coupling and transistor is difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it each other.
The 6th embodiment
Please refer to Fig. 9, it shows the detailed circuit diagram of the 6th embodiment of the shift register cell of Fig. 2.The shift register cell S6 (n) of present embodiment is the embodiment of deriving of the shift register S5 (n) in the 5th embodiment, and its difference is that the drain electrode of the transistor T 8 in the 5th embodiment and the sequential signal CLK that capacitor C receives change to sequential signal CLKB.So, the operation of the shift register cell S6 (n) of present embodiment can be analogized according to the narration in second embodiment and obtained.
The 7th embodiment
Please refer to Figure 10, it shows the detailed circuit diagram of the 7th embodiment of the shift register cell of Fig. 2.Shift register cell S1 (n) difference in the shift register cell S7 (n) of present embodiment and first embodiment is that the grid of transistor T 8 and drain electrode couple mutually, to receive controlling signal Vc3 (n), wherein the highest the and minimum level of sequential signal CLK equals voltage VDD and VSS respectively.So, the transistor T 8 of present embodiment has close in fact operation with the middle corresponding transistor of the shift register cell S1 (n) in first embodiment, make controlling signal Vc2 (n) equal voltage VDD in order to high level conducting, and end in response to the low level of controlling signal Vc3 (n) in response to controlling signal Vc3 (n).
So, the level controller 204 of present embodiment also has transistor in fact size coupling and transistor is difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it each other.
The 8th embodiment
Please refer to Figure 11, it shows the detailed circuit diagram of the 8th embodiment of the shift register cell of Fig. 2.Shift register cell S2 (n) difference in the shift register cell S8 (n) of present embodiment and second embodiment is that the grid of transistor T 8 and drain electrode couple mutually, to receive controlling signal Vc3 (n), wherein the highest the and minimum level of sequential signal CLKB equals voltage VDD and VSS respectively.So, according to the 3rd embodiment in like manner can push away in transistor T 8 and second embodiment of present embodiment corresponding transistor have close in fact operation.
So, the level controller 204 of present embodiment also has transistor in fact size coupling and transistor is difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it each other.
The 9th embodiment
Please refer to Figure 12, it shows the detailed circuit diagram of the 9th embodiment of the shift register cell of Fig. 2.Shift register cell S1 (n) difference in the shift register cell S9 (n) of present embodiment and the 7th embodiment is also to comprise in the driver element 202 transistor T 11, it is in order to conducting in sequential period T P3, so that controlling signal Vc1 (n) equals voltage VSS.So, the operation of the shift register cell S9 (n) of present embodiment can be analogized according to the narration in the 5th embodiment and obtained.
Second embodiment
Please refer to Figure 13, it shows the calcspar according to the shift register of second embodiment of the invention.Shift register 10 differences of the shift register 20 of present embodiment and first embodiment are that the control end RT of shift register cell U (1)～U (m-2) wherein receives the voltage signal of node NT1 of shift register cell U (3)～U (m) respectively with as controlling signal Vc1 (1)～Vc1 (m-2).Next, be that the numerous embodiments that example is enumerated the shift register cell U (n) of present embodiment explains with n level shift register cell U (n) among shift register cell U (1)～U (m).
First embodiment
Please refer to Figure 14, it shows the detailed circuit diagram of first implementation method of the shift register cell of Figure 13.The shift register cell U1 (n) of present embodiment is that with shift register cell S1 (n) difference of first implementation method of first embodiment it comprises transistor T 3 ' and T6 ', and replaces transistor T 3 and the T6 of shift register cell S1 (n) respectively with transistor T 3 ' and T6 '.
The drain electrode of transistor T 3 ' and T6 ' is coupled to node NT1 and output terminal OUT respectively, and grid all receives the controlling signal Vc1 (n+2) of n+2 level shift register cell U (n+2), and source electrode all receives voltage VSS.So, according to the signal waveform figure of Fig. 4 A as can be known, transistor T 3 ' and T6 ' conducting in sequential period T P3 and TP4 makes controlling signal Vc1 (n) and scanning signal Vo (n) equal voltage VSS respectively.The shift register cell U (n) of present embodiment and the shift register cell S1 (n) of first implementation method of first embodiment have close in fact operation, also can control controlling signal Vc1 (n) and equal voltage VSS with scanning signal Vo (n) in sequential period T P4.So, the level controller 204 of present embodiment also has transistor in fact size coupling and transistor is difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it each other.
Second to the 6th embodiment
Please refer to the 15th～Figure 19, its show respectively Fig. 9 shift register cell second, third, the detailed circuit diagram of the 4th, the 5th and the 6th embodiment.Shift register cell U2 (n), U3 (n), U4 (n), U5 (n) and U6 (n) are respectively among first embodiment embodiment of deriving of shift register cell corresponding in second to the 6th embodiment, and it replaces transistor T 3 and the T6 in the corresponding embodiment among first embodiment with transistor T 3 ' and T6 ' respectively.So, the operation of shift register cell U2 (n), U3 (n), U4 (n), U5 (n) and U6 (n) can be analogized according to the narration in first embodiment and obtained.
The 7th embodiment
Please refer to Figure 20, it shows the detailed circuit diagram of the 7th embodiment of the shift register cell of Fig. 9.Shift register cell U3 (n) difference in the shift register cell U7 (n) of present embodiment and the 3rd embodiment is that the level controller 204 of shift register cell U7 (n) also comprises transistor T 12, drain electrode is coupled to node NT2, grid receives the scanning signal Vo (n-1) of n-1 level shift register cell U7 (n-1), and source electrode receives voltage VSS.In sequential period T P1, scanning signal Vo (n-1) equals voltage VDD and equals voltage VSS with the turn-on transistor T12 controlling signal Vc2 (n) that begins.So, among the level controller 204 of present embodiment and first embodiment among the shift register S1 (n) of first embodiment corresponding level controller have close in fact operation, equal voltage VSS in order in sequential period T P1, to make controlling signal Vc2 (n).
So, the level controller 204 of present embodiment also has transistor in fact size coupling and transistor is difficult for the advantage that corrupted, shift register cell are difficult for that misoperation takes place and make long and display frame better quality in LCD serviceable life of using it each other.
The the 8th to the tenth embodiment
Please refer to Figure 21～23, it shows the detailed circuit diagram according to the 8th, the 9th and the tenth embodiment of the shift register of Fig. 9 respectively.The shift register cell U8 (n) of the 8th to the tenth embodiment, U9 (n) and U10 (n) are respectively the embodiment of deriving of the shift register cell of correspondence in the 4th to the 6th embodiment, its level controller 204 all has transistor T 12, and it is used to, and beginning controlling signal Vc2 (n) equals voltage VSS among the sequential period T P1.In addition, respectively with transistor T 3 and T6 in transistor T 3 ' and the corresponding embodiment of T6 ' replacement.So, the operation of shift register cell U8 (n), U9 (n) and U10 (n) can be analogized according to the narration in the 4th to the 6th embodiment and obtained.
Though in the 7th to the tenth embodiment, be that example is done explanation only to drag down the embodiment that transistor T 12 is set in the circuit that has transistor T 6 ' and T3 ' in the unit 208 respectively at driver element 202 and level, so, drag down in the circuit embodiment that has transistor T 6 and T3 in the unit 208 respectively in driver element 202 and level and also transistor T 12 can be set, shown in Figure 24～27.Its operation can be analogized according to the narration in the 3rd to the 6th embodiment among first embodiment and obtained.
The 11 to the 13 embodiment
Please refer to Figure 28～30, it shows the detailed circuit diagram of the 11, the 12 and the 13 embodiment of the shift register cell of Fig. 9 respectively.Shift register cell U11 (n), U12 (n) and U13 (n) are respectively among first embodiment embodiment of deriving of shift register cell corresponding in the 7th to the 9th embodiment, and it replaces transistor T 3 and the T6 in the corresponding embodiment among first embodiment with transistor T 3 ' and T6 ' respectively.So, the operation of shift register cell U11 (n), U12 (n) and U13 (n) can be analogized according to the narration in first embodiment and obtained.
Though only comprise that with shift register cell S (n) circuit structure of transistor T 1～T9 or transistor T 1～T10 is that example explains in the above-described embodiments, so, the circuit structure that driver element in the shift register cell in the embodiment of the invention, level controller, level lift unit, level drag down the unit is not limited to the structure of the shift register cell in the above embodiment of the present invention, and more can carry out some other changes.
In sum, though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.The technician of the technical field of the invention can be used for a variety of modifications and variations under the premise without departing from the spirit and scope of the present invention.Therefore, protection scope of the present invention is as the criterion with claim of the present invention.
Claims (20)
1. a shift register comprises the multi-stage shift register unit, and shift register cells at different levels are in order to produce a scanning signal, and shift register cells at different levels comprise:
One first level lift unit equals one first sequential signal in order to control this scanning signal in response to the high level of one first controlling signal;
One first level drags down the unit, equals one first voltage in order to control this scanning signal in response to the high level of one second controlling signal;
One first driver element provides this first controlling signal to come this first level lift unit of conducting in order to the rising edge in response to an input signal; And
One level controller receives this first controlling signal and exports this second controlling signal in an output terminal according to this, and this level controller comprises:
One input block, one the 3rd controlling signal of controlling on the first node in response to the rising edge of this first controlling signal equals this first voltage;
One electric charge storage unit, an end is coupled to this first node, and the other end receives one second sequential signal, and this electric charge storage unit is in order to store the voltage of this sequential signal with respect to this first node;
One second level lift unit is controlled this second controlling signal in response to the rising edge of the 3rd controlling signal and is equaled the 3rd controlling signal in fact and drag down the unit with this first level of conducting; And
One second level drags down the unit, controls this second controlling signal in response to the rising edge of this first controlling signal and equals this first voltage to drag down the unit by this first level;
Wherein, this input signal is the scanning signal of the previous stage shift register cell output of each shift register cell.
2. shift register as claimed in claim 1, wherein this input block comprises a first transistor, and grid receives this this first controlling signal, and drain electrode is coupled to this first node, and source electrode receives this first voltage.
3. shift register as claimed in claim 1, wherein this second level lift unit comprises a transistor seconds, and grid receives the 3rd controlling signal, and drain electrode receives this second sequential signal, and source electrode is coupled to this output terminal.
4. shift register as claimed in claim 1, wherein this second level lift unit comprises one the 3rd transistor, and grid and drain electrode receive the 3rd controlling signal, and source electrode is coupled to this output terminal.
5. shift register as claimed in claim 1, wherein this second level drags down the unit and comprises one the 4th transistor, and grid receives this first controlling signal, and drain electrode is coupled to this output terminal, and source electrode receives this first voltage.
6. shift register as claimed in claim 5, wherein this second level drags down the unit and also comprises one the 5th transistor, and grid receives this input signal, and drain electrode is coupled to this output terminal, and source electrode receives this first voltage.
7. shift register as claimed in claim 1, wherein this second sequential signal equals this first sequential signal.
8. shift register as claimed in claim 1, wherein this second sequential signal and this first sequential signal are reverse each other.
9. shift register as claimed in claim 1, wherein this first level lift unit comprises one the 6th transistor, grid receives this first controlling signal, and first drain/source receives this first sequential signal, and second drain/source is coupled to the output terminal of shift register cells at different levels.
10. shift register as claimed in claim 1, wherein this first level drags down the unit and comprises one the 7th transistor, and grid receives this second controlling signal, and drain electrode is coupled to the output terminal of shift register cells at different levels, and source electrode receives this first voltage.
11. shift register as claimed in claim 10, wherein first level of n level shift register cell drags down the unit and also comprises one the 8th transistor, grid receives first controlling signal of n+1 level shift register cell, drain electrode is coupled to the output terminal of this n level shift register cell, source electrode receives this first sequential signal, and n is a natural number.
12. shift register as claimed in claim 10, wherein first level of this n level shift register cell drags down the unit and also comprises one the 9th transistor, grid receives first controlling signal of n+2 level shift register cell, drain electrode is coupled to the output terminal of this n level shift register cell, source electrode receives this first voltage, and n is a natural number.
13. shift register as claimed in claim 1, wherein this first driver element comprises:
The tenth transistor, grid receives this input signal with drain electrode, and source electrode and this first level lift unit are coupled to a Section Point.
14. shift register as claimed in claim 13, wherein first driver element of n level shift register cell also comprises:
The 11 transistor, grid receives first controlling signal of n+1 level shift register cell, and drain electrode is coupled to this Section Point, and source electrode receives this first sequential signal, and n is a natural number.
15. shift register as claimed in claim 13, wherein first driver element of n level shift register cell also comprises:
The tenth two-transistor, grid receives first controlling signal of n+2 level shift register cell, and drain electrode is coupled to this Section Point, and source electrode receives this first voltage, and n is a natural number.
16. a level controller comprises:
One input block equals one first voltage in order to a controlling signal of controlling in response to the rising edge of an input signal on the node;
One electric charge storage unit, an end is coupled to this node, and the other end receives a sequential signal, and this electric charge storage unit is in order to store the voltage of this sequential signal with respect to this node;
One level lift unit provides sequential signal to an output terminal in order to the rising edge in response to this controlling signal, to export an output signal; And
One level drags down the unit, equals this first voltage in order to control this output signal in response to the rising edge of this input signal.
17. level controller as claimed in claim 16, wherein this input block comprises a first transistor, and grid receives this input signal, and drain electrode is coupled to this node, and source electrode receives this first voltage.
18. level controller as claimed in claim 16, wherein this level lift unit comprises a transistor seconds, and grid receives this controlling signal, and drain electrode receives this sequential signal, and source electrode is coupled to this output terminal.
19. level controller as claimed in claim 16, wherein this level lift unit comprises one the 3rd transistor, and grid and drain electrode receive this controlling signal, and source electrode is coupled to this output terminal.
20. level controller as claimed in claim 16, wherein this level drags down the unit and comprises one the 4th transistor, and grid receives this input signal, and drain electrode is coupled to this output terminal, and source electrode receives this first voltage.
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| CN200710102139A CN100578599C (en) | 2007-04-29 | 2007-04-29 | Shifting register and level controller thereof |
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| CN200710102139A CN100578599C (en) | 2007-04-29 | 2007-04-29 | Shifting register and level controller thereof |
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| CN101908381B (en) * | 2009-06-04 | 2013-02-06 | 胜华科技股份有限公司 | Shift register |
| CN101609719B (en) * | 2009-07-22 | 2011-12-28 | 友达光电股份有限公司 | Shift register of display device |
| CN102654969B (en) * | 2011-12-31 | 2013-07-24 | 京东方科技集团股份有限公司 | Shift register unit, shift register circuit, array substrate and display device |
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