CN100576169C - A kind of method and system of execution command - Google Patents
A kind of method and system of execution command Download PDFInfo
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- CN100576169C CN100576169C CN200710130521A CN200710130521A CN100576169C CN 100576169 C CN100576169 C CN 100576169C CN 200710130521 A CN200710130521 A CN 200710130521A CN 200710130521 A CN200710130521 A CN 200710130521A CN 100576169 C CN100576169 C CN 100576169C
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Abstract
The invention discloses a kind of method of execution command, the corresponding relation of index and register coding is set in indexed registers in advance, this method comprises: read the instruction relevant with index, obtain the corresponding index of this instruction, and in the corresponding relation of indexed registers, read the register coding of this index correspondence; Carry out this instruction based on the corresponding register of this register coding then.The invention also discloses a kind of system of execution command, comprise steering logic and indexed registers.Use the present invention to realize the flexible configuration and the application of CPU register, broken through the restriction that the implicit fixedly general-purpose register content of revising correspondence caused when execution was instructed in spinoff, thereby can carry out the adjustment of application binaries interface (ABI) comprehensively the register use; And save the space encoder of instruction, perhaps increase the addressing range of instruction.
Description
Technical field
The present invention relates to computer technology, be specifically related to a kind of method and system of execution command.
Background technology
Mostly be similar in existing central processing unit (CPU, the Central Processing Unit) instruction pop/push on (pop/push), the instruction fetch of frame pointer register ( / swp! ) and shift and connect such spinoffs such as (bl, branch and link) and instruct.Though this class instruction does not contain some register information when encoding, saved the space encoder of instruction, but continuous execution for cpu instruction, the implicit respectively content of having used stack pointer register (sp), frame pointer register (fp) and link register general-purpose registers such as (lr), the execution result of instruction can revise the implicit register of these instructions of above-mentioned instruction.For example, the hidden register of pop/push correspondence is the sp register, when carrying out the pop/push instruction, refers in order normally to carry out next pop/push, not only can be in the storehouse that sp points to access data, also can imply the value of revising in the sp register.The bl instruction can carry out next bar instruction of jump instruction, and the implicit address that next bar is instructed is deposited among the lr, thereby has been destroyed the content in original lr register for when carrying out link order.
Therefore, though do not comprise register information in the spinoff instruction, saved the space encoder of instruction, but, the execution of these instructions but can be revised the content of general-purpose register, effectively utilize register and use flexibly instruction thereby limited the CPU register allocation algorithm, for the upgrading of instruction and architecture has caused difficulty.
Summary of the invention
In view of this, the invention provides a kind of method of execution command, the CPU register is effectively utilized flexibly.
The invention provides a kind of system of execution command, the CPU register is effectively utilized flexibly.
For achieving the above object, technical scheme of the present invention is achieved in that
A kind of method of execution command, the corresponding relation of index and register coding is set in indexed registers in advance, this method comprises: read the instruction relevant with index, and after obtaining the corresponding index of described instruction, from the corresponding relation of indexed registers, read the register coding of this index correspondence; Carry out described instruction based on the corresponding register of this register coding.
Preferably, the described corresponding relation that index and register coding is set in indexed registers is in advance realized by the instruction that execution is provided with the corresponding relation of index and register coding.
Further, before the described corresponding relation that index and register coding is set in indexed registers, this method also comprises: the instruction of implicit index is set, makes the instruction of described implicit index corresponding with an index; Correspondingly, described read the instruction relevant and obtain the corresponding index of and instruction with index be: read the instruction of implicit index, obtain and the corresponding index of instruction that should imply index.
Preferably, the described instruction that implicit index is set realizes by the instruction of the described implicit index of curing in steering logic and the corresponding relation of an index.
The instruction of described implicit index is corresponding one by one with index.
The described step that the corresponding relation of index and register coding is set in indexed registers is in advance carried out when system start-up; Perhaps carrying out after the system start-up and before carrying out at least one instruction relevant with index; Perhaps after system start-up, repeatedly carry out.
The step that reads the register coding of this index correspondence in the described corresponding relation from indexed registers is merged to decoding stage or execution phase.
Perhaps in the one-level pipeline flowing water that increases newly, carry out the step of the register coding that reads this index correspondence in the described corresponding relation from indexed registers.
Wherein, described instruction is the instruction that comprises index.
Before the described corresponding relation that index and register coding is set in indexed registers in advance, this method further comprises: the index in the application binaries interface (ABI, Application Binary Interface) in the defined instruction uses agreement.
A kind of system of execution command comprises steering logic and indexed registers, and described steering logic is used in advance being provided with in indexed registers the corresponding relation of index and register coding; Read the instruction relevant, obtain the corresponding index of this instruction, from the corresponding relation of indexed registers, read the register coding of this index correspondence, and carry out described instruction based on the corresponding register of this register coding with index; Described indexed registers is used to store the corresponding relation of index and register coding.
Wherein, described instruction is the instruction that comprises index.
Instruction and a fixed indices that described steering logic has been solidified at least one implicit index concern that one to one described steering logic also is used to read the instruction of implicit index, obtain the index of the instruction correspondence of this implicit index.
Compared with prior art, technical scheme provided by the present invention, the corresponding relation of index and register coding is set in indexed registers in advance, read the instruction relevant with index, and obtain the corresponding index of this instruction, from the corresponding relation of indexed registers, read the register coding of this index correspondence, then, carry out this instruction based on the corresponding register of this register coding.Thereby realized the indirect correlation of instruction and register by index, therefore, can amended corresponding relation be set by the register coding of software modification index correspondence when the content of indexed registers is set, realize the flexible configuration and the application of CPU register.
Simultaneously, when carrying out the spinoff instruction, relevant by index with the register of index indication, thereby make the implicit register of revising the index indication when spinoff instruction is carried out, avoided the implicit fixedly content of general-purpose register of revising of spinoff instruction, discharged fixedly general-purpose register, can flexible Application CPU register.
Because technical scheme provided by the invention has discharged fixedly general-purpose register, and flexible configuration and application have been realized to the CPU register, thereby make when architecture is upgraded, can arbitrarily increase the instruction of using each register, make that the adjustment of ABI is comprehensive more, flexible.
Corresponding by index with register, index of reference in instruction and indirectly relevant with register, thus the index that can utilize less figure place is relevant with register than label greatly, has saved the space encoder of register in instructing, increase the figure place of counting immediately, thereby increased addressing range; Or under the situation that the numerical digit number is constant immediately, reduced instruction code length.
Description of drawings
Fig. 1 is the data path figure that carries out the bl instruction in the embodiment of the invention one;
Fig. 2 is the method flow diagram of execution command in the embodiment of the invention one;
Fig. 3 is the data path figure that carries out the instruction of access number in the embodiment of the invention two;
Fig. 4 is the method flow diagram of execution command in the embodiment of the invention two.
Embodiment
The present invention is described in detail below in conjunction with drawings and the specific embodiments.
The method of execution command provided by the invention, the corresponding relation of index and register coding is set in indexed registers in advance, after reading the instruction relevant, obtain the corresponding index of this instruction, and in the corresponding relation of indexed registers, read the register coding of this index correspondence with index; Carry out this instruction based on the register of this register coding indication then.
Below with the implementation of two embodiment explanation instruction relevant with index, realize the process of example one for the instruction execution of implicit index, embodiment two is the implementation that comprises the instruction of index.
Embodiment one:
Present embodiment describes the instruction for implicit index in the cpu instruction in detail, i.e. spinoff instruction, the situation of configuration register.
The system of the execution command in the embodiment of the invention one comprises steering logic and indexed registers.
Wherein, steering logic is used in advance being provided with in indexed registers the corresponding relation of index and register coding; From order register, read the spinoff instruction, obtain the corresponding index of this spinoff instruction, in the corresponding relation of indexed registers, read the register coding of this index correspondence then, and the register read-write control that obtains of binding analysis instruction, carry out this instruction based on the corresponding register of this register coding.
Indexed registers is used to store the corresponding relation of index and register coding.
Fig. 1 is the data path figure that carries out the bl instruction in the embodiment of the invention one.As shown in Figure 1, steering logic reads the bl instruction from order register, obtains the corresponding index of this instruction, read and write under the control of control at the register that steering logic produces according to this index, read indexed registers, obtain the coding of the implicit register of revising of this instruction, for example register 1; This instruction is carried out in the register read-write control that obtains of this instruction of binding analysis then; Simultaneously, because the implicit address with next bar instruction of this instruction deposits in the lr register in the prior art, when carrying out this instruction in the present embodiment, with the implicit register 1 of revising the corresponding index correspondence of this instruction, promptly read the instruction address in the PC register, with this address add 4 obtain the address of next bar instruction after, deposit in the register of index correspondence of this instruction correspondence, be register 1 in the present embodiment.As seen, the embodiment of the invention is relevant with index with the spinoff instruction, the implicit content of revising the register of index correspondence, thus discharged the implicit register of revising of spinoff instruction in the prior art, make this register can do other use.
Fig. 2 is the method flow diagram of execution command in the embodiment of the invention one.This method may further comprise the steps:
When step 201:CPU started, steering logic was provided with the corresponding relation of index and register coding in indexed registers.
In this step, steering logic reads the instruction of configuration specified register, the corresponding relation of configuration index and register coding in indexed registers.In the practical application, this step also can be carried out before CPU starts the back and carrying out at least one instruction relevant with index, perhaps after starting, repeatedly carries out CPU, as long as those skilled in the art expect avoiding the CPU register to use chaotic problem easily, just can utilize this programme to use the CPU register flexibly, can be in the content that reconfigures indexed registers according to specific circumstances in service of system, different situations according to performed instruction are adjusted accordingly to the distribution condition of register, have further increased the dirigibility that register uses undoubtedly.
For example, when CPU started, steering logic read in the instruction that index and register coding corresponding relation are set in the indexed registers, and the corresponding relation of index as shown in table 1 and register coding is set in indexed registers.
| Index | The register coding |
| 0 | 0000，0000 |
| 1 | 0000，0001 |
| 2 | 0000，0010 |
| 3 | 0000，1100 |
The corresponding relation of table 1 index and register coding
As shown in table 1, the register of index 1 correspondence is encoded to 0000,0001, that is to say, the register of this index correspondence is the R1 register.
The corresponding relation of configuration index and register coding also can be realized in such a way in indexed registers: indexed registers is the registers group that a plurality of index related registers are formed, utilize index to be numbered each index related register in the registers group, and in each index related register the storage register corresponding coding with index, thereby realization index and register is corresponding.
Configuration index also can order be provided with the corresponding register coding of each index with the corresponding relation of register coding in indexed registers in indexed registers, for example, in 16 bit registers, first 8 in indexed registers are provided with 0000,0000 expression index 0 is corresponding with register R0, the 2nd 8 be provided with 0000,0010 the expression index 1 corresponding with register R2, or the like.
Step 202: when carrying out the spinoff instruction, steering logic reads this instruction, obtains the corresponding index of this instruction.
Carry out before this step, be provided with the instruction of implicit index, and make this instruction corresponding with an index, for example realize by the instruction of the implicit index of curing in steering logic and the corresponding relation of an index, thereby after making that steering logic reads the spinoff instruction in this step, can obtain the corresponding index of this spinoff instruction.Wherein, the process that the technology of the corresponding relation of the instruction of the implicit index of curing and an index and this step are carried out in steering logic, respectively with the existing corresponding relation that in steering logic, solidifies spinoff instruction and its implicit register coding of revising, and after steering logic reads spinoff instruction, the technology of register coding that obtains the corresponding implicit modification of this spinoff instruction is identical, therefore, do not repeat them here.
For example, table 2 is depicted as the example that the spinoff instruction is relevant with index.
| The spinoff instruction | Index |
| pop/push | 0 |
| lwp！/swp ！ | 1 |
| bl | 2 |
Table 2 spinoff instruction is relevant with index
As shown in table 2, steering logic is relevant with index 0 with the pop/push instruction, lwp! / swp! Relevant with index 1, the bl instruction is relevant with index 2.When steering logic read the pop/push instruction, it was relevant with index 0 directly to obtain this instruction according to the relevant example of table 2.
Step 203: the register of analyzing this instruction acquisition in steering logic is read and write under the control of control, reads the register coding of this index correspondence in the corresponding relation of indexed registers, obtains the register of this index correspondence.
For example, the spinoff instruction that steering logic is read in the step 202 is pop/push, and can obtain the corresponding index of this instruction in step 202 is 0, then when carrying out this step, reading the register coding of index 0 correspondence in indexed registers, is the R0 register thereby obtain the corresponding register of this instruction.
Step 204: under the control of the register read-write control that the steering logic analysis instruction obtains, carry out this instruction, and revise the content of the register of index correspondence.
For example, when carrying out spinoff instruction pop/push, if be the pop instruction, the register read-write control that then the steering logic analysis instruction obtains in this step is to read, and the register that this instruction is carried out is a stack register, therefore, carry out in this step, read the content of stack register stack top, simultaneously, the implicit content of revising the register of relative index correspondence of the execution of this instruction, soon the content modification in the R0 register of index 0 correspondence is the pointer of current stack; If be the push instruction, the register read-write control that then the steering logic analysis instruction obtains in this step is to write, the register that this instruction is carried out is a stack register, therefore, carry out in this step, the parameter that obtains before this instruction is write in the stack register, simultaneously, the implicit content of revising the register of relative index correspondence of the execution of this instruction, soon the content modification in the R0 register of index 0 correspondence is the pointer of current stack.
In this step, the steering logic analysis instruction obtains register read-write control, and is prior art in conjunction with this register read-write control execution command, does not therefore repeat them here.
When carrying out the push/pop instruction in the prior art, the content of implicit modification sp register, and as seen from the above description, in the embodiment of the invention one, the corresponding relation of configuration index and register coding in indexed registers, to instruct relevantly by steering logic, and make the implicit register of revising of spinoff instruction push/pop, change into the pairing register of index that this instruction is correlated with by original sp register with index.Therefore the instruction that has side effects no longer directly is associated with concrete register, but with indexed registers in the index pairing register relevant stored with this instruction be correlated with.Therefore, the implicit register of revising of original spinoff instruction can be used as other register in the present invention, thereby has reached the flexible use of register.
When using next time, if the R0 register is used in other aspect, the instruction of indexed registers then can be set by modification, with the index modification of this register correspondence is corresponding with other register coding, when starting, carries out CPU this instruction, the 0 pairing register coding of index in the indexed registers stored relation is revised as other register coding, and for example the register of R5 register is encoded, thereby has realized the flexible configuration and the application of CPU register.
Simultaneously, after executing instruction in the embodiment of the invention one, employed spinoff instruction do not need to comprise index just can realize implicit relevant with the corresponding register of index, so when can guarantee not take the order number space, the flexible configuration and the application of realization CPU register.
Spinoff instruction and index in the present embodiment are to concern one to one.
Embodiment two:
Present embodiment describe in detail to adopt fixing register to carry out under the situation of instruction of addressing the method and system of execution command as overall base register.
In the present embodiment, the system of execution command comprises steering logic and indexed registers.
Wherein, steering logic is used in advance being provided with in indexed registers the corresponding relation of index and register coding; Read the instruction that comprises index, obtain the corresponding index of this instruction, in the corresponding relation of indexed registers, read the register coding of this index correspondence according to this index, and the register read-write control that obtains of binding analysis instruction, this instruction carried out based on the corresponding register of this register coding.
Indexed registers is used to store the corresponding relation of index and register coding.
Fig. 3 is the data path figure that the embodiment of the invention two is carried out the instruction of access number.As shown in Figure 3, when carrying out memory reference order load, detailed process comprises: read the instruction that comprises index, from this instruction, obtain index, analyze under the control of the register read-write control that this instruction obtains in steering logic then, reading indexed registers, obtain the register coding of this index correspondence, for example is register 1; Under the control of register read-write control, read the content in the register 1 of index correspondence, obtain plot, address offset in the and instruction obtains the address of the storer that will read together again, and from this address reading of data, these data that read are written in the register 2 that comprises in the instruction.When carrying out memory reference order store, read the content in the register 2, be written in the address that the address offset in the plot and instruction of storing in the register according to the index correspondence that is comprised in the instruction calculates.
Fig. 4 is the method flow diagram of execution command in the embodiment of the invention two.As shown in Figure 4, this method may further comprise the steps:
Step 400: index of definition uses agreement in ABI.
Each operating system all can provide ABI for the application program that operates under this system.ABI has comprised the programming agreement that must observe when application program is moved under this system, and comprise a series of system call and use the method for these system calls, and the regulation of using about the operable memory address of program and register.
In this step, to use agreement be the purposes of the index that occurs in the defined instruction to index of definition in ABI, and for example, index 3 is for being used for the index of overall base register.
When step 401:CPU started, steering logic was provided with the corresponding relation of index and register coding in indexed registers.
This step is identical with step 201, does not therefore repeat them here.
Step 402: read the instruction that comprises index, obtain index from this instruction, and under the control of the register read-write control that the steering logic analysis instruction obtains, from the corresponding relation of indexed registers, read the pairing register coding of this index, obtain the pairing register of this index.
Step 403: analyze the register read-write control that this instruction obtains in conjunction with steering logic, based on the register execution command of this index correspondence.
For instance, in the C language, compiler, connector are left the small character segment variable concentratedly usually, making things convenient for access, in execution process instruction by overall base register (gp) this class variable of mode access with the address offset addition.And in the embodiment of the invention two, make index of reference replace gp, when CPU starts, the corresponding relation of index 3 and gp register is set in indexed registers simultaneously.For example, execution command load rl, [3, #immediate], read this instruction after, analyze the index 3 that this instruction obtains wherein overall base register correspondence, the register of index 3 correspondences in indexed registers in the reading command is encoded, and for example is the R3 register.Under the control of the register read-write control that the steering logic analysis instruction obtains, from this register, read plot then, utilize this plot to continue to carry out this instruction again.
And at prior art execution command load rl, when [gp, #immediate], because gp participates in order number, comprise at CPU under the situation of 32 registers, each register needs 5 space encoder, and when the code length of instruction fixedly the time, encoding with respect to register takies the few situation of figure place, the code length of counting (immediate) immediately reduces, the numerical range that makes this count immediately is less, and promptly side-play amount diminishes, thereby makes the addressing space based on gp diminish.And among the present invention, if utilizing the register of index setting is 4, then index is only used 4 and is got final product, that is to say by making index of reference, only need two registers that just can represent originally to take 5 codings, thereby the code length that will count has immediately increased 3, has also just increased the addressing space based on gp.
By the above as can be known, the present invention can use register indirectly by index, thereby makes that the purposes of register is no longer fixing, helps using register by the configuration of software flexible.And under the condition of same-code length, can enlarge addressing range, or under identical addressing range, obtain the code of reduced size, thereby reach the effect of saving space encoder.Therefore, the method in the present embodiment also can be used as a kind of instruction addressing pattern use.
The technical scheme of the flexible Application embodiment of the invention one, it is comprehensive more, flexible also can to make the ABI that carries out when architecture is upgraded adjust.The upgrading of architecture generally is to obtain by the improvement to original architectural instructions, but in order to keep the true(-)running of existing software, usually can not make amendment, and only utilize remaining binary coding space to increase instruction with better function existing instruction and binary coded format.But, if wishing to utilize, the instruction that increases has the register that the spinoff instruction can change, then the increase of this instruction tends to be restricted, and does not also often reach the result of hope after increasing.And in existing architecture, the spinoff instruction exists usually, and it is directly related with fixing general-purpose register, makes that again the use of general-purpose register is limited, and this makes that software ABI can be restricted along with the function of any register purposes of needs adjustment in the traditional architectures.
For example, when in the score system, increasing by 16 bit instructions, because the space encoder restriction, wish that the register coding only takies 3, that is to say that hope only uses the R0-R7 register as operation note, therefore, need be in ABI the purposes of R0-R7 be made as operation note.But under the score system, R0, R2 and R3 register have fixed-purpose, and the R0 register is used for the sp register when carrying out the pop/push instruction, the R2 register be used to carry out lwp! / swp! Lr register when the fp register during instruction, R3 are used to carry out the bl instruction, the stationarity of these three registers has limited the design of software ABI.Thereby make 16 bit instructions that increase to use register R1 and R4-R7, and can not make full use of all represented registers of the instruction space.
When utilizing the technical scheme of present embodiment, only need these spinoff instructions are relevant with the index of indexed registers, and the register that this index correspondence is set in indexed registers is the later register of R7, and is for example that the pop/push instruction is relevant with the R8 register by index, lwp! / swp! Instruction is relevant with the R9 register by index, and the bl instruction is relevant with register R11 by index, like this, originally there were register R0, R2 and the R3 of fixed-purpose just can discharge by configuration, redefine for ABI, thereby removed the spinoff instruction restriction that any use causes to register in original architecture, made little label register be fully used.
In the practical application, the technical scheme that provides in the embodiment of the invention one can be used in combination with the technical scheme that embodiment two provides, the corresponding relation of index and register coding is set in indexed registers when for example CPU starts, utilize the technical scheme of embodiment one, index 0,1,2 is relevant with the spinoff instruction; And in the instruction of plot indexed addressing, make index of reference 3 corresponding with overall base register, thereby when having discharged the implicit fixedly general-purpose register of revising of spinoff instruction, can also abdicate more multidigit and give immediately and count, can represent with an instruction containing the instruction of counting immediately as far as possible; And increase the addressing range of instruction, or save the space encoder of instruction.
In addition, the method of the execution command of describing in the embodiment of the invention one is not limited only to the spinoff instruction, also can be applied to the instruction of other implicit index, for example set in advance the corresponding relation of load instruction and index, and the overall base register or the corresponding index of appointment in the load instruction removed, the load instruction is become the instruction of implicit index, read the instruction of this implicit index by steering logic after, obtain the corresponding index of this instruction, read indexed registers, obtain the overall base register in the load instruction, thereby can use overall base register flexibly, or with other register as overall base register, realize flexible Application to register; Simultaneously,, saved the order number space, perhaps increased the addressing range of counting immediately owing to base register do not occur in the instruction.In this example, can there be the instruction of a plurality of implicit index corresponding with an index, for example the load of implicit index instruction can be corresponding with an index with the store instruction of implying index, i.e. load instruction and store instruction are all corresponding with an overall base register; The instruction that also can be an implicit index is corresponding with a plurality of index, for example corresponding first index of the load of implicit index instruction is the index of overall base register, and second corresponding index is for taking out the index of the register correspondence of depositing after the data from storer.
The present invention is by index indirect referencing register, when realizing CPU register flexible configuration and application, also owing to just can affact the problem that register has brought efficient by index.Owing to add the one-level index search, need the corresponding stage on the hardware to handle, therefore can realize by adding one-level pipeline flowing water, also index search can be merged to the existing some flowing water stage, for example decipher stage or execution phase and realize.
By the above as can be seen, technical scheme provided by the present invention, the spinoff instruction affacts on the pairing register of index by steering logic, changed the implicit fixedly general-purpose register of revising of spinoff instruction of the prior art, thereby make that fixedly general-purpose register discharges, in needs, be defined as the register of other effect, realized flexible configuration and use the CPU register.
Simultaneously, technical scheme provided by the invention does not need existing spinoff instruction is changed, and can guarantee under the situation identical with spinoff order number length in the prior art the implicit register of revising of configuration spinoff instruction; Simultaneously, can also guarantee the compatibility of hardware binary command.And owing to can be cpu instruction flexible configuration register by the content that indexed registers is set, thereby when making things convenient for the ABI rule of compiler personal scheduling, the preceding end instruction of design, adjust the register purposes of any needs, help finding rational ABI rule model.Therefore, both reached when the CPU architecture upgraded, can effectively keep the compatibility of hardware binary command and the conforming effect of software ABI design, reached the ABI rule of end instruction before making things convenient for the compiler personnel by the method scheduling of software again, to find out a kind of effect of rational ABI rule model.
At last, technical scheme provided by the invention, corresponding by index with register, index of reference in instruction and indirect referencing register, making can be according to register operating position and code length limited case, and utilization is relevant with the register of big label than the index of lower-order digit, the space encoder of register in reducing to instruct, thereby, increased addressing range for side-play amount discharges more figure place; Simultaneously, under the constant situation of side-play amount figure place, reduced instruction code length.
Though above-described embodiment has only enumerated load and store instruction application in the present invention, but those skilled in the art should understand that, except that these two instructions, other need use the instruction of CPU register also to be suitable for using the solution of the present invention, reaching above-described effect, or solve above-described problem.
The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1, a kind of method of execution command is characterized in that, the corresponding relation of index and register coding is set in indexed registers in advance, and this method comprises:
Read the instruction relevant, and after obtaining the index corresponding, from the corresponding relation of described indexed registers, read the register coding of this index correspondence with described instruction with index;
Carry out described instruction based on the corresponding register of this register coding.
2, the method for claim 1 is characterized in that, the described corresponding relation that index and register coding are set in indexed registers is realized by the instruction that execution is provided with the corresponding relation of index and register coding.
3, the method for claim 1 is characterized in that, described reading before the instruction relevant with index, and this method further comprises:
The instruction of implicit index is set, makes the instruction of described implicit index corresponding with an index;
Described read the instruction relevant and obtain the corresponding index of and instruction with index be: read the instruction of implicit index, obtain and the corresponding index of instruction that should imply index.
4, method as claimed in claim 3 is characterized in that, the described instruction that implicit index is set realizes by the instruction of the described implicit index of curing in steering logic and the corresponding relation of an index.
As claim 3 or 4 described methods, it is characterized in that 5, the instruction of described implicit index is corresponding one by one with index.
6, the method for claim 1 is characterized in that, the described step that the corresponding relation of index and register coding is set in indexed registers is in advance carried out when system start-up;
Perhaps carrying out after the system start-up and before carrying out at least one instruction relevant with index;
Perhaps after system start-up, repeatedly carry out.
7, the method for claim 1 is characterized in that, the step that reads the register coding of this index correspondence in the described corresponding relation from indexed registers is merged to decoding stage or execution phase.
8, the method for claim 1 is characterized in that, reads the step of the register coding of this index correspondence in the described corresponding relation from indexed registers and carries out in the one-level pipeline flowing water that increases newly.
9, the method for claim 1 is characterized in that, described instruction is the instruction that comprises index.
10, method as claimed in claim 9 is characterized in that, described in indexed registers, be provided with in advance index and register the coding corresponding relation before, this method further comprises:
Index in application binaries interface ABI in the defined instruction uses agreement.
11, a kind of system of execution command is characterized in that, this system comprises steering logic and indexed registers,
Described steering logic is used in advance being provided with in indexed registers the corresponding relation of index and register coding; Read the instruction relevant, obtain the corresponding index of this instruction, from the corresponding relation of indexed registers, read the register coding of this index correspondence, and carry out described instruction based on the corresponding register of this register coding with index;
Described indexed registers is used to store the corresponding relation of index and register coding.
12, system as claimed in claim 11 is characterized in that, described instruction is the instruction that comprises index.
13, system as claimed in claim 11, it is characterized in that, instruction and a fixed indices that described steering logic has been solidified at least one implicit index concern one to one, described steering logic also is used to read the instruction of described implicit index, obtains the index of the instruction correspondence of this implicit index.
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