CN100573878C

CN100573878C - Charge trapping non-volatile memory and method of operation thereof

Info

Publication number: CN100573878C
Application number: CNB2005100829010A
Authority: CN
Inventors: 叶致锴
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2004-07-06
Filing date: 2005-07-05
Publication date: 2009-12-23
Anticipated expiration: 2025-07-05
Also published as: CN1719598A; CN1722445A; CN1719612A; CN1719611B; CN1719611A; CN1722444A; CN1722444B

Abstract

A kind of multiple grid memory cell, this multiple grid memory cell comprise one with semiconductor body on the grid of most arranged in series.Charge storing structure on the semiconductor body comprises two charge-trapping zones, and these two charge-trapping zones are arranged in most grids all or each below of some grids.Also comprise conduction source electrode bias voltage and drain bias extremely near the semiconductor body of first grid in the grid row, and conduct the grid bias Circuits System of several grids at the most with final grid.The multiple grid memory cell comprises a continuous multiple grid channel region, and this multiple grid channel region is arranged in most grid belows of grid row.Between the grid of some or all, this multiple grid memory cell has charge storaging area.

Description

Charge trapping non-volatile memory and method of operation thereof

Technical field

The invention relates to a kind of integrated circuit non-volatile memory device, and particularly relevant for a kind of new memory cell and method of operation thereof.

Background technology

Electrical programmable and erasable non-volatile memory technologies, as have electrically can wiping and the programmable read only memory (electrically erasable andprogrammable read only memory of Charge Storage function, EEPROM) with flash memory (flash memory), used in various modern application.Some memory cell structures are used for as electrically wiping and the programmable read only memory and flash memory.Along with dwindling of integrated circuit size, for the expandability and the simplification of technology, the memory cell structure with charge-trapping dielectric layers receives bigger concern gradually.Memory cell structure with charge-trapping dielectric layers for example comprises only reading memory (nitride read only memory of industrial called after silicon nitride, NROM), silicon-oxide-nitride--oxide-silicon (silicon-oxide-nitride-oxide-silicon, SONOS), metal-oxide-nitride-oxide-silicon (metal-oxide-nitride-oxide-silicon, MONOS) inject nitrogenize electron storage device with sequencing (programming by hot hole injectionnitride electron storage, structure PHINES) with the mat hot electron.These memory cell structure utilizations are caught electric charge and are come storage data (data are data, below all be called data) in the charge-trapping dielectric layers that for example is silicon nitride.When trap negative charge, the threshold voltage voltage of memory cell then can increase.Self charge is caught layer and is removed the threshold voltage voltage that negative electrical charge then reduces memory cell.

Fig. 1 illustrates the section of structure into the charge capturing storage unit of known a kind of SONOS type.Substrate comprises the n as the

electrode

15,16 of source/drain ⁺Doped region, and the p doped channel regions 17 between electrode 15,16.The remainder of memory cell comprises the charge-trapping structure, and the charge-trapping structure comprises and is positioned at dielectric layer of the suprabasil end 14, is positioned at charge-trapping material 13 on the end dielectric layer 14, is positioned at the top dielectric layer 12 on the charge-trapping material 13 and is positioned at grid 11 on the top dielectric layer 12.Typical top dielectric layer comprises that thickness is the silicon dioxide and the silicon oxynitride of 5～10 nanometers (how nanometer is rice, below all be called nanometer), or other similar high dielectric constant materials, for example comprises aluminium oxide (Al ₂O ₃).Dielectric layer of the typical end comprises that thickness is the silicon dioxide and the silicon oxynitride of 3～10 nanometers, or other similar high dielectric constant materials.For this kind of charge-trapping structure, typical charge-trapping material comprises that thickness is the silicon nitride of 3～9 nanometers, or other similar high dielectric constant materials, comprises silicon oxynitride, metal oxide such as aluminium oxide, hafnium oxide (HfO2) or other materials.The charge-trapping material can be charge-trapping material area or the particle that is interrupted, or continuous as shown in the figure rete.

For memory cell,

electrode

15,16 is as source/drain, in bias arrangement, come to memory cell read, sequencing and wiping.The doped region that forms

electrode

15,16 generally comprises the impurity that injects the semiconductor-based end, with the conducting electrode of foundation with channel region 17 opposite conductive form.The diffusion of impurities that the step of implanted dopant make to be injected is to the semiconductor-based end, and can limitation capability dwindling the length of the raceway groove between the

electrode

15,16, or even use photoetching to shrink the minimum dimension that can reach.

Fig. 2 A and Fig. 2 B illustrate to known Fu Lenuohai tunnelling (Fowler-Nordheim tunneling) that the memory cell sequencing is caused during to high threshold voltage state and enter a kind of bias arrangement in the charge-trapping structure from substrate.According to the configuration of known techniques, Fig. 2 A shows grid, source electrode, drain electrode and suprabasil bias voltage Vg, Vs, Vd, Vb, and it has caused the electron tunneling shown in Fig. 2 B.

Fig. 3 illustrates to known that (not-and, NAND) the SONOS type memory cell of type array structure institute arranged in series utilizes a kind of bias arrangement to come the fixed memory cell of sequencing with and not b gate.In Fig. 3, column of memory cells comprises n ⁺ Doped region 20～26, selection grid SLG1 and SLG2 and word line WL ₁～WL ₄ Charge storing structure 27～30 is positioned at word line WL ₁～WL ₄Under, and respectively on the channel region 31～34 between

doped region

21 and 22, doped

region

22 and 23, doped

region

23 and 24, the doped region 24 and 25.Doped region 20,26 is as bit line or respectively as bit line BL ₁With BL ₂Connection.Select grid SLG1 and SLG2 to form to select transistor (transistor is electric crystal, below all be called transistor), doped

region

21 and 22 and doped region 25 and 26 is used for respectively being connected or isolated storage cell columns and and BL ₂For the selected memory cell in the sequencing column of memory cells, as word line WL ₁On memory cell, use a bias arrangement as shown in the figure, its neutrality line BL ₁Not to be couple to ground (injecting the selected memory cell of sequencing), couple exactly to apply current potential Vcc (with the sequencing of the memory cell of forbidding selecting) with FN.In order to couple bit line BL ₁To doped region 21, select grid SLG1 to receive and apply current potential Vcc.Select voltage or the ground connection of grid SLG2 reception 0V, to isolate bit line BL ₂With doped region 25.When substrate ground connection, the word line of selected memory cell is word line WL in this example ₁, receive the high voltage that is about 18V.The word line of Xuan Ding memory cell receives the voltage that is about 10V, and enough feasible other channel region produces counter-rotating, but not enough so that important electric charge ejaculation.As shown in Figure 3, doped region is formed between each channel region.

Therefore, for source/drain, the use of diffusing lines from the semiconductor-based end (diffusion line) has produced a restriction on the size of traditional memory cell.Be used for forming the diffusion of the impurity of diffusing lines, scattering surpasses the zone of being injected, and has increased the size of doped region, and other restrictions that cause memory cell size, comprises the minimum channel length of avoiding puncturing (pounch-through).

The method of using diffusing lines to overcome problem is developed, the method is based on produce conduction counter-rotating zone in substrate, the control electrode of use adjacent charge memory structure in memory cell, the foundation that therefore constantly changes counter-rotating zone is then as source/drain electrodes.Because do not carry out injection technology, the size in counter-rotating zone can be controlled more accurately according to the minimum feature size of technology." 90-nm*node multi-level AG-AND type flash memory with cell size oftre 2F ²/ bit and programming throughput of 10MB/s, " IEDM, 2003, page823-826 and by U.S. Patent Publication No. No.US2004/0084714 that the people proposed such as Ishii.The technology of the improvement grid that the people proposed such as Sasago can be considered as being applied in the extension of so-called separated grid (split gate) technology of various forms of floating grid memory components.Please refer to by the Chang proposition about the separated grid element No. the 5th, 408,115, United States Patent (USP).

Therefore, develop that making simple and the technology of the nonvolatile memory of high-density applications is provided is gratifying.

Summary of the invention

The present invention proposes a kind of integrated circuit memory element with multiple grid (multiple-gate) memory cell.In one embodiment, said elements comprises the semiconductor main body and the grid of most arranged in series on semiconductor body.A charge storing structure on semiconductor body, wherein this charge storing structure is continuous structure, is included in the charge-trapping zone that surpasses in most the grids under the grid.Also be included in the semiconductor body, near the first grid and final grid of column of memory cells, conduct the Circuits System of source electrode/drain bias respectively, and conduct the grid bias Circuits System of several grids at the most to the first region territory and the second electrode region.The multiple grid memory cell comprises one continuously and be positioned at multiple grid channel region under most the grids of column of memory cells, and it is between the first region territory and the second electrode region.In certain embodiments, the charge-trapping zone comprises the specific multiple grid memory cell under all grids that are positioned at column of memory cells, and all grids are as controlling grid with storage data.In other embodiments, all grids in the column of memory cells are not all as controlling grid with storage data.In an example, with storage data, and other grids in the column of memory cells are used for promoting the isolation between the storage area in the memory cell to part of grid pole as the control grid.

In certain embodiments, on the multiple grid memory cell, whole in most the grids in column of memory cells or surpass two regional storage datas under one the grid use two storage areas of using each to control grid and come storage data.

In certain embodiments, the Circuits System of conduction source electrode/drain bias comprises the conductive material of arrangement as bit line, and the Circuits System of conduction grid bias comprises the conductive material of arrangement as word line.For instance, first doped region and second doped region are included in the semiconductor body, and the first grid that is listed as with adjacent memory cells provides electrode zone with final grid.Doped region has the conduction type opposite with semiconductor body, and as source/drain electrodes.The counter-rotating zone of being caused when in other embodiments, utilizing in multiple grid memory cell access storage area provides the first region territory and the second electrode region.In certain embodiments, for example for select transistorized element optionally connect as in first area and the second electrode region at least one doped region or the reversal zone to bit line.

Carry out the operation of memory cell in order to set up bias arrangement, utilize the controller of Circuits System with the Circuits System of conduction grid bias of control conduction source electrode/drain bias, the integrated circuit component with multiple grid memory cell is operated.In an example, in order to set up a high threshold voltage state, utilize controller that bias arrangement is provided, it comprises a sequencing bias arrangement, to cause that electronics injects the charge-trapping zone of tunnelling to the memory cell, this charge-trapping zone is arranged under the selected grid of column of memory cells.In the process of sequencing, apply selected grid bias another control grid to the column of memory cells, or other whole control grids, causing in channel region that fully counter-rotating supports electron tunneling.Comprise at some and to utilize electronics to inject the example that carries out sequencing, provide bias arrangement with controller, it comprises that is wiped a bias arrangement, wipes to cause that electronics ejaculation or hole are injected in the charge storage region, to set up a low threshold voltage state.

In the embodiment of integrated circuit with multiple grid memory cell, the embodiment that comprises two storage areas that utilize each control grid, the Circuits System of controller control conduction source electrode/drain bias is set up a bias arrangement with the Circuits System of conduction grid bias, with the charge-trapping zone storage data under each grid of the grid above that is arranged in column of memory cells.In an example, in order to set up a low threshold voltage state, utilize controller that bias arrangement is provided, it comprises a sequencing bias arrangement, to cause that hot hole injects the charge-trapping zone of tunnelling to the memory cell, this charge-trapping zone is in two selected charge storage region in one of them, and charge storage region is arranged under the selected grid of column of memory cells.Programmed process being arranged in the selected charge storage region under the selected control grid applies another grid that is biased in the column of memory cells, or other whole grids, and causing in channel region fully reverses supports tunneled holes.Comprise at some and to utilize the hole to inject the example that carries out sequencing that provide bias arrangement with controller, it comprises that is wiped a bias arrangement, wipes to cause that electronics is injected in the charge storage region, to set up a high threshold voltage state.In the embodiment of integrated circuit with multiple grid memory cell, the embodiment that comprises two storage areas that utilize each control grid, comprise that in certain embodiments hot hole wipes, according to an erase step, the controller control applies bias arrangement and wipes, this erase step comprises the storage area under the selected grid wiping the column of memory cells that is arranged in the multiple grid memory cell, and does not wipe the storage area under another grid that is arranged in column of memory cells.

In some instances, the controller control applies bias arrangement, it comprises that is read a bias arrangement, read under the bias arrangement at this, selected control grid receives and reads voltage, and the control grid on other storage areas receives voltage and cause counter-rotating in the multiple grid channel region, to support reading of memory zone.

The present invention proposes a kind of method of operation of integrated circuit memory element in addition, and wherein the integrated circuit memory element comprises that aforesaid multiple grid memory cell and the method generally are to control with wafer built-in (on-chip) controller.Method of the present invention is included in the element and applies bias arrangement with reading of data in the zone that is positioned under the selected grid; Apply bias arrangement with the sequencing data in a zone that is positioned under the selected grid; Apply bias arrangement with obliterated data in a zone that is positioned under the selected grid.In the embodiment of this method, the bias arrangement of sequencing comprises:

In the multiple grid channel region, apply substrate bias condition (bias condition) to semiconductor body;

First grid in column of memory cells and final grid one of them near apply the source electrode bias condition to semiconductor body;

Apply the drain bias condition to semiconductor body near in first grid in column of memory cells and the final grid another; And

In column of memory cells, apply most grid bias conditions several grids at the most, wherein these grid bias conditions comprise a sequencing voltage and a reversal voltage, wherein the sequencing voltage on the selected grid in column of memory cells is with respect to the substrate bias condition, enough reduce electron injection current to the charge-trapping zone that is positioned at selected grid below, to set up high threshold voltage state, and the reversal voltage on other grids in column of memory cells enough reduces the counter-rotating in the multiple grid channel region, wherein the multiple grid channel region is positioned at above-mentioned other grids below, and does not have effective electronics to be injected into to be positioned at most charge storaging areas of above-mentioned other grids belows.

In the embodiment of this method, the bias arrangement of wiping comprises:

In the multiple grid channel region, apply the substrate bias condition to semiconductor body;

First grid and final grid apply the source electrode bias condition to semiconductor body near one of them in column of memory cells;

First grid and final grid wherein apply the drain bias condition to semiconductor body near another in column of memory cells; And

In column of memory cells, apply most grid bias conditions several grids at the most, wherein these above-mentioned these grid bias conditions comprise most voltages, these voltages cause that enough electronics penetrates or hole iunjected charge capture region from the charge-trapping zone, to set up low threshold voltage state, wherein the charge-trapping zone is arranged under the above-mentioned grid of column of memory cells.

In another example, the bias arrangement of wiping comprises:

In column of memory cells, apply most grid bias conditions with to being positioned at one or more selected zones, most grids belows, wherein above-mentioned these grid bias conditions comprise most voltages, these voltages cause that enough the hole injection is arranged in the charge-trapping zone of the selected grid below of column of memory cells, and above-mentioned grid bias condition is included in the counter-rotating bias voltage on other grids in the column of memory cells, this reversal voltage enough reduces the counter-rotating in the multiple grid channel region, to set up low threshold voltage state in selected grid, wherein the multiple grid channel region is positioned at above-mentioned other grid belows.

According to the described erase step of the embodiment of the invention, this erase step comprises:

One group of grid in most the grids of desiring in the column of memory cells to wipe is verified this group grid has the grid of surpassing;

Applying most grid bias conditions wipes the first selected grid in above-mentioned that group grid, with the hot hole iunjected charge storage area that causes that source side or gate electrode side one of them or whole band are caused band tunnelling (band-to-bandtunneling), this charge storaging area is positioned at the first selected grid below;

Applying most grid bias conditions wipes the selected grid of the next one in above-mentioned that group grid, with the hot hole iunjected charge storage area that causes that source side or gate electrode side one of them or whole band are caused band tunnelling (band-to-bandtunneling), this charge storaging area is positioned at next selected grid below, and repeats above-mentioned steps all grids in applying extremely above-mentioned that group grid of above-mentioned grid bias condition.

In the embodiment of this method, read with determination data and comprise with the high bias arrangement of representing with low threshold voltage state:

In column of memory cells, apply most grid bias conditions several grids at the most, wherein these grid bias conditions are included on the selected grid in the column of memory cells voltage that reads with respect to the substrate bias condition, this reads the threshold voltage that voltage is higher than low threshold voltage state, and these grid bias conditions are included in the counter-rotating bias voltage on other grids in the column of memory cells, this reversal voltage enough reduces the counter-rotating in the multiple grid channel region, wherein the multiple grid channel region is positioned at above-mentioned other grid belows, and this reversal voltage is higher than the threshold voltage of high threshold voltage state.

The above-mentioned multiple grid memory cell that is arranged in the array comprises most word lines, is coupled to most grids of multiple grid memory cell at least one row; A most bit line with most word line vertical arrangements, and are arranged in delegation or multirow to be connected to the multiple grid memory cell; A majority selection grid are arranged at least one row to connect the bit line in the extremely relevant majority bit line of other multiple grid memory cell, to respond selection grid controlling signal; And a selection wire, at least one row, be coupled to most and select grids, select the grid controlling signal to provide.In addition, most bit lines of controller control, most bit lines and selection wire, in array with conduction source electrode bias voltage and drain bias to multiple gate memory cell, and at least one row the most individual grids of conduction grid bias to the multiple gate memory cell.

In certain embodiments, make the above-mentioned multiple grid memory cell and the array of multiple grid memory cell according to method of the present invention, the method comprises:

Semiconductor body with first conductivity type is provided;

On semiconductor body, form charge storing structure;

Deposition first grid conductor layer on charge storing structure;

Patterning first grid conductor layer is with most first grids on the definition charge storing structure, on continuous multiple grid channel region, this multiple grid channel region is in semiconductor body between the first region territory and the second electrode region with a gap arranged in series for most first grids;

To the sidewall that is less than most first grids, form insulating barrier;

Deposition second grid conductor layer is included between most the first grids on insulating barrier, and isolates most first grids with insulating barrier; Most second grids of definition on semiconductor body, a most first grid and most second grid arranged in series are on continuous multiple grid channel region, this multiple grid channel region is in semiconductor body between the first region territory and the second electrode region, to form the multiple grid memory cell.

In the embodiment of above-mentioned multiple grid memory cell, the insulating barrier on the grid utilization control gate lateral wall in the column of memory cells is separated mutually with small distance, and this manufacture method is with described in before.In continuous multiple grid channel region, this distance for individual other grid, comprises the distance less than 10 nanometers in fact less than the length of grid.

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.

Description of drawings

Fig. 1 illustrates and is known a kind of charge capturing storage unit.

Fig. 2 A and Fig. 2 B illustrate to cause that the FN tunnelling carries out the bias arrangement of sequencing to known charge capturing storage unit.

Fig. 3 illustrates and is known a kind of configuration that is listed as with the charge capturing storage unit of enable nand gate, and with a kind of bias arrangement memory cell selected in the column of memory cells is carried out sequencing.

Fig. 4 illustrates to having the multiple grid memory cell of two control grids.

Fig. 5 illustrates the graphical sysmbol into as shown in Figure 4 multiple grid memory cell.

Fig. 6 illustrates to having the multiple grid memory cell of two control grids, and in column of memory cells sequencing is carried out in the storage area that is positioned at below the selected memory cell with a kind of bias arrangement.

Fig. 7 A to Fig. 7 D illustrates to having the multiple grid memory cell of two control grids, and the storage area that is positioned at below the selected memory cell is read in column of memory cells with individual other bias arrangement.

Fig. 8 illustrates to having the multiple grid memory cell of two control grids, and the storage area that is positioned at below the selected memory cell is wiped in column of memory cells with a kind of bias arrangement.

Fig. 9 illustrates to having the multiple grid memory cell of two control grids, and the storage area that is positioned at below the selected memory cell is wiped in column of memory cells with selectable bias arrangement.

Figure 10 illustrates to having the multiple grid memory cell of N control grid.

Figure 11 illustrates the graphical sysmbol into as shown in Figure 4 multiple grid memory cell.

Figure 12 illustrates to having the multiple grid memory cell of N control grid, and in column of memory cells sequencing is carried out in the storage area that is positioned at below the selected memory cell with a kind of bias arrangement.

Figure 13 illustrates to having the multiple grid memory cell of N control grid, and the storage area that is positioned at below the selected memory cell is read in column of memory cells with a kind of bias arrangement.

Figure 14 illustrates to having the multiple grid memory cell of N control grid, and the storage area that is positioned at below the selected memory cell is wiped in column of memory cells with a kind of bias arrangement.

Figure 15 illustrates to having the multiple grid memory cell of N control grid, and the storage area that is positioned at below the selected memory cell is wiped in column of memory cells with selectable bias arrangement.

Figure 16 illustrates the simplified flow chart of wiping for the bias arrangement that applies Figure 14 and Figure 15.

Figure 17 illustrates to having the multiple grid memory cell of N control grid, in column of memory cells near first grid and the final grid, with Circuits System conduction source pole tension and drain voltage to semiconductor body.

Figure 18 illustrates to having the multiple grid memory cell of N control grid, in column of memory cells near first grid and the final grid, with the selection gridistor.

Figure 19 illustrates to having the multiple grid memory cell of N control grid, with selectable execution mode, in column of memory cells near first grid and the final grid, to selection grid conduction source pole tension and drain voltage to semiconductor body.

Figure 20 illustrates to having the multiple grid memory cell of N control grid, with another selectable execution mode, in column of memory cells near first grid and the final grid, to selection grid conduction source pole tension and drain voltage to semiconductor body.

Figure 21 illustrates to having the multiple grid memory cell of N control grid, with selectable Circuits System, in column of memory cells near first grid and the final grid, to selection grid conduction source pole tension and drain voltage to semiconductor body.

Figure 22 illustrates to having the multiple grid memory cell of N+1 (odd number) control grid, comes storage data with the grid of remembering even number in the hundred million born of the same parents row as the control grid.

Figure 23 illustrates to having the multiple grid memory cell of N+1 (odd number) control grid, comes storage data with the grid of remembering odd number in the hundred million born of the same parents row as the control grid.

Figure 24 A to Figure 24 F illustrates the making flow process into the multiple grid memory cell.

Figure 25 illustrates in the making flow process as the multiple grid memory cell of Figure 24 A to Figure 24 F, passes the step that charge storing structure forms source electrode and drain electrode alloy.

Figure 26 A to Figure 26 D illustrates and is the making flow chart as the multiple grid memory cell of Figure 22 or Figure 23.

It is the calcspar that comprises the integrated circuit of multiple grid memory cell array that Figure 27 illustrates.

Figure 28 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 29 illustrates to having the multiple grid memory cell of two control grids and two storage areas, carries out obliterated data with a kind of bias arrangement under selected control grid, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 30 illustrates to having the multiple grid memory cell of two control grids and two storage areas, carries out obliterated data with selectable bias arrangement under selected control grid, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 31 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the left side bit 1-1 that is positioned at the first control grid below is carried out sequencing with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 32 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the right side bit 1-2 that is positioned at the first control grid below is carried out sequencing with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 33 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the left side bit 2-1 that is positioned at the second control grid below is carried out sequencing with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 34 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the right side bit 2-2 that is positioned at the second control grid below is carried out sequencing with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 35 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the left side bit 1-1 that is positioned at the first control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 36 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the right side bit 1-2 that is positioned at the first control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 37 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the left side bit 2-1 that is positioned at the second control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 38 illustrates to having the multiple grid memory cell of two control grids and two storage areas, and the right side bit 2-2 that is positioned at the second control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 39 illustrates to having the multiple grid memory cell of N control grid and two storage areas, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 40 illustrates to having the multiple grid memory cell of N control grid and two storage areas, wipes with a kind of bias arrangement under selected control grid, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 41 illustrates to having the multiple grid memory cell of N control grid and two storage areas, wipes with selectable bias arrangement under selected control grid, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 42 illustrates to having the multiple grid memory cell of N control grid and two storage areas, and the left side bit that is positioned at selected control grid below is carried out sequencing with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 43 illustrates to having the multiple grid memory cell of N control grid and two storage areas, and the right side bit that is positioned at selected control grid below is carried out sequencing with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 44 illustrates to having the multiple grid memory cell of N control grid and two storage areas, and the left side bit that is positioned at selected control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 45 illustrates to having the multiple grid memory cell of N control grid and two storage areas, and the right side bit that is positioned at selected control grid below is read with a kind of bias arrangement, and wherein above-mentioned storage area and each control grid are got in touch.

Figure 46 illustrates the layout into a section of multiple grid memory cell.

Figure 47 illustrates the first selectable layout into a section of multiple grid memory cell.

Figure 48 illustrates the second selectable layout into a section of multiple grid memory cell.

Figure 49 illustrates the 3rd selectable layout into a section of multiple grid memory cell.

Figure 50 illustrates the 4th selectable layout into a section of multiple grid memory cell.

Figure 51 illustrates the layout into a block of multiple grid memory cell, and this block comprises most sections.

1,103-1～103-N, 501,502,603-1～603-N, 750～756,760～766: control grid

11,50,51,201,209,173-1～173-N+1: grid

12,52,105,605: the top dielectric layer

13: the charge-trapping material

14,54,107,607: end dielectric layer

15,16,55,56,101,102,202,203,205,206,212,213,503,504,601,602: electrode

17,31～34,58: channel region

20～26: doped region

53,106,302,606: electric charge capture layer

57,500: substrate

60,110: electronic signs

70,71,104-1～104-N, 184-1～184-N+1,604-1-1～604-N-1,604-1-2～604-N-2: charge storaging area

73,74,75,77,120,121,125,126,127,128,510,512,514,516,615,616,625,626,635,636,645,646: the reversal zone

76,78,130,131: hot hole

100: substrate

150,151: Circuits System

207,208,214,215: gate dielectric layer

210,211,710～716,720～726, SLG1, SLG2: select grid

250～257: step

301: bottom oxide

303: the top oxide layer

304: polysilicon layer

304X, 306X: gate electrode

307: source electrode

308: drain electrode

340: separator

341～347: the gap

349: source electrode

350: drain electrode

351～356: stack layer

400: memory array

401: column decoder

402, WL ₁～WL ₄: word line

403: row decoder

404, BL ₁, BL ₂, BL _N-3～BL _N+3: bit line

405: bus-bar

406: square

407: the data bus-bar

411: Data In-Line

412: DOL Data Output Line

450: integrated circuit

505,506,511,513,515,517,610-1～610-N, 611-1～611-N, 617,627: symbol

600: semiconductor body

700～706,740～746: the multiple grid memory cell

718,728,748,749,758: contact window

719,769: source electrode line

800: section

802～811: contact hole

I: label

F: characteristic size

SLG3, SLG4: controlling signal

Vg, Vs, Vd, Vb: bias voltage

Embodiment

Below will be described in detail the embodiment of the invention, and simultaneously with reference to Fig. 4 to Figure 51.

As employed, sequencing is meant that a bit then sets the threshold voltage in the memory zone of selecting in a bit ground, be meant the threshold voltage of setting selected memory region or memory district to erased conditions (erase condition) and wipe, it quickflashing (flash) that comprises whole array or partial array is wiped.In an embodiment of the present invention, the write step of data comprises, at first, to the processing of wiping of a selected block, so that the memory district in the block is set to erase threshold voltage, is generally the wherein a kind of of high or low threshold voltage state.Then, the memory district in the block is carried out sequencing handle, be set to the sequencing state, be generally the wherein another kind of of high or low threshold voltage state, and stay memory district not selected in the block at erase status with the memory district that will select.The embodiment of technology described herein comprises that sequencing is meant the threshold voltage that improves the memory district and wipes product and the method that is meant the threshold voltage that reduces the memory district, and sequencing is meant the threshold voltage that reduces the memory district and wipes product and the method that is meant the threshold voltage that improves the memory district.

Fig. 4 illustrates to according to a kind of bigrid memory cell of the present invention, comes sequencing is carried out in selected zone with a kind of bias arrangement.The bigrid memory cell comprise respectively left and right sides electrode district with the n+ doped region channel region 58 in formed electrode 55,56 and left and right sides grid 50,51 and the substrate 57.Connecting the bigrid memory cell to bit line, or other Circuits System are to provide bias voltage as electrode electrode 55,56 for doped region.Channel region 58 is continuous p type zone and in substrate between the electrode 55,56, does not have doped region significantly and isolates the part of the channel region under left and right sides grid 50,51.The charge-trapping structure for example comprise for the top dielectric layer 52 of representative thickness, electric charge capture layer 53 with about 9 nanometers with for example be the end dielectric layer 54 of representative thickness with about 6 nanometers.The charge-trapping structure is formed between the channel region 58 in left and right sides grid 50,51 and the substrate of p type.Electric charge capture layer 53 comprises and for example is the silicon nitride of about 6 nanometer thickness or the layer of material of other structures, and it can be with the charge-conduction that is captured in selected memory cell to not influencing in the zone of other regional threshold voltages in the column of memory cells in fact.In certain embodiments, grid 50,51 comprises n type or p type polysilicon.Other representational grid materials comprise titanium nitride (TiN), platinum (Pt) and other H.D metal or material.Each storage area can store the data of a bit or multidigit unit.For instance, utilize rank, multiprogram threshold voltage position are set up in the zone, can store multidigit unit in each zone.

Fig. 5 illustrates the graphical sysmbol into a kind of gate memory cell, this gate memory cell as shown in Figure 4, wherein source electrode and drain electrode corresponding doped

region electrode

55,56 respectively, and control grid 1 corresponding grid 50, and control grid 2 corresponding grids 51.

Fig. 6 illustrates a kind of bias arrangement of carrying out sequencing for to memory district selected in the bigrid memory cell, and this gate memory cell as shown in Figure 4.According to bias arrangement, utilize substrate 57 ground connection, apply the Vg of about 18V ₁To grid 50, apply about 10V to grid 51, and doped

region electrode

55,56 one of them ground connection, and another also ground connection or suspension joint, cause the FN tunnelling at the charge storing structure that is arranged in below the grid 50 with the zone of electronic signs 60 representatives.

Fig. 7 A to Fig. 7 D illustrates the bias arrangement into reading of data in the bigrid memory cell, and this gate memory cell as shown in Figure 4.In Fig. 7 A to Fig. 7 B, read the data of " bit 1 (bit 1) " of representing the bigrid memory cell by source side or drain side reception 2V, wherein this data storing is being positioned at receiving grid pole tension Vg ₁Grid 50 under charge storaging area 70.In Fig. 7 C to Fig. 7 D, read the data of " bit 2 (bit 2) " of representing the bigrid memory cell by source side or drain side reception 2V, wherein this data storing is being positioned at receiving grid pole tension Vg ₂Grid 51 under charge storaging area 71.

Fig. 7 A illustrates when reading " bit 1 " at charge storaging area 70, applies positive 2V as drain electrode and make the bias arrangement of electrode 55 ground connection as source electrode at electrode 56.The grid voltage Vg that is applied in grid 51 ₂Enough high and make and produce reversal zone 73 in the channel region between the electrode 55,56.Utilization is by grid voltage Vg ₂The reversal zone 73 that produces will be coupled near the zone in the channel region of charge storaging area 70 at the voltage in source electrode or the drain electrode.Memory cell is set the grid voltage Vg that is applied to grid 50 ₁On low threshold voltage, and under the high threshold voltage.In one embodiment, the grid voltage Vg that is applied ₁Be about 2V.Fig. 7 B illustrates to

opposite electrode

55,56 is read identical " bit 1 " to be biased in the charge storaging area 70.

Fig. 7 C illustrates when reading " bit 2 " at charge storaging area 71, applies positive 2V as drain electrode and make the bias arrangement of electrode 55 ground connection as source electrode at electrode 56.The grid voltage Vg that is applied in grid 50 ₁Enough high and make and produce reversal zone 74 in the channel region between the electrode 55,56.Utilization is by grid voltage Vg ₁The reversal zone 74 that produces will be coupled near the zone in the channel region of charge storaging area 71 at the voltage in source electrode or the drain electrode.Memory cell is set the grid voltage Vg that is applied to grid 51 ₂On low threshold voltage, and under the high threshold voltage.In one embodiment, the grid voltage Vg that is applied ₁Be about 2V.Fig. 7 D illustrates to

opposite electrode

55,56 is read identical " bit 2 " to be biased in the charge storaging area 71.

Fig. 8 and Fig. 9 illustrate the bias arrangement that can select for when memory cell is as shown in Figure 4 carried out obliterated data, these two kinds of bias arrangement are operated with each grid one bit in the multiple grid memory cell, and are suitable for using in conjunction with sequencing bias voltage shown in Figure 6.Please refer to Fig. 8, the bias arrangement of wiping of, wiping " bit 1 " in the storage area that is arranged under the control gate utmost point 50 comprises when electrode 55 ground connection and when applying about 5V to electrode 56, applies the grid voltage Vg of pact-5V ₁To grid 50 and the grid voltage Vg that applies about 10V ₂To grid 51.So just, under grid 51, produce reversal zone 75, and produce hot hole 76 in the substrate under grid 50.Hot hole is injected into the storage area of " bit 1 ", replaces electronics and reduces the threshold voltage of the storage area under the grid 50.

Please refer to Fig. 9, the storage area of control grid 50 under being arranged in, the selectable bias arrangement of wiping of wiping " bit 1 " comprises when electrode 56 ground connection and when applying about 5V to electrode 55, applies the grid voltage Vg of pact-5V ₁To grid 50 and the grid voltage Vg that applies about 10V ₂To grid 51.So just, under grid 51, produce reversal zone 77, and produce hot hole 78 in the substrate under grid 50.Hot hole is injected into the storage area of " bit 1 ", replaces electronics and reduces the threshold voltage of the storage area under the grid 50.In certain embodiments,, apply bias arrangement shown in Figure 9 again,, and can wipe " bit 1 " so that the CHARGE DISTRIBUTION in the storage area reaches balance by applying bias arrangement shown in Figure 8 earlier.

Figure 10 illustrates and is one embodiment of the invention, wherein has two grids of surpassing in the multiple grid memory cell, and embodiment shown in Figure 4 is extended to N grid on single continuous channel region in substrate 100.Multiple grid memory cell shown in Figure 10 is included in first electrode 101 and second electrode 102 that forms with flush type diffusion (buried diffusion) in the substrate 100.Most control grid 103-1～103-N are disposed on the charge storing structure, and wherein this charge storing structure comprises top dielectric layer 105, electric charge capture layer 106 and end dielectric layer 107.Charge storaging area 104-1～104-N in the electric charge capture layer 106 is disposed in the substrate in the continuous channel region between electrode 101,102.As shown in the figure, a kind of bias arrangement applies grid voltage Vg ₁～Vg _NTo controlling grid 103-1～103-N, apply source voltage Vs to electrode 101, and apply drain voltage Vd to electrode 102.Certainly, source voltage and drain voltage can be applied to electrode 102 and electrode 101 on the contrary respectively.

Can do selection according to special embodiment in single multiple grid memory cell as shown in figure 10.For instance, N equals 8 in one embodiment.In another embodiment, can be greater than or less than 8.

Figure 11 illustrates the graphical sysmbol into a kind of multiple grid memory cell, this gate memory cell as shown in figure 10, wherein source electrode and drain electrode counter electrode 101,102 respectively, and control grid 1 corresponding grid 103-1, and the corresponding grid 103-N of control grid N.

Figure 12 illustrates a kind of bias arrangement of selected memory district being carried out sequencing in the multiple grid memory cell, and it is described similar to Figure 10.According to bias arrangement,,, apply the Vg of 18V by substrate 100 ground connection when electrode 101,102 one of them ground connection and another also ground connection or suspension joint ₂To grid 103-2, apply about 10V to grid 103-1 and～103-N, the zone with electronic signs 110 expressions in the charge storing structure under grid 103-2 causes the FN tunnelling.

Figure 13 illustrates to read a kind of demonstration bias arrangement of " bit 5 " in charge storaging area 104-5, wherein, the electrode 102 as drain electrode is applied positive 2V, and will be as electrode 101 ground connection of source electrode.Grid voltage Vg ₁～Vg ₄With Vg ₆～Vg _NThe sufficiently high reversal zone 120,121 that in the channel region between electrode 101,102, produces.Grid voltage Vg ₁～Vg ₄With Vg ₆～Vg _NThe reversal zone 120,121 that is produced will be coupled near the zone in the channel region of charge storaging area 104-5 at the voltage in source electrode or the drain electrode.Memory cell is set the grid voltage Vg that is applied to grid 103-5 ₅On low threshold voltage, and under the high threshold voltage.In this example, the grid voltage Vg that is applied ₅Be about 2V.

Figure 14 and Figure 15 illustrate the bias arrangement that can select for when memory cell is as shown in figure 10 carried out obliterated data, these two kinds of bias arrangement are operated with each grid one bit in the multiple grid memory cell, and are suitable for using in conjunction with sequencing bias voltage shown in Figure 12.Please refer to Figure 14, the bias arrangement of wiping of, wiping " bit 3 " in the storage area that is arranged under the control gate utmost point 103-3 comprises when electrode 101 ground connection and when applying about 5V to electrode 102, applies the grid voltage Vg of pact-5V ₃To grid 103-3 and the grid voltage Vg that applies about 10V ₁～Vg ₂With Vg ₄～Vg _NTo grid 103-1～103-2 and 103-4～103-N.So just, under grid 103-1～103-2, produce reversal zone 125,, and produce hot hole 130 in the substrate under grid 103-3 with generation reversal zone 126 under grid 103-4～103-N.Hot hole is injected into the storage area of " bit 3 ", replaces electronics and reduces the threshold voltage of the storage area under the grid 103-3.

Please refer to Figure 15, the storage area of control grid 103-3 under being arranged in, the selectable bias arrangement of wiping of wiping " bit 3 " comprises when electrode 102 ground connection and when applying about 5V to electrode 101, applies the grid voltage Vg of pact-5V ₃To grid 103-3 and the grid voltage Vg that applies about 10V ₁～Vg ₂With Vg ₄～Vg _NTo grid 103-1～103-2 and 103-4～103-N.So just, under grid 103-1 and 103-2, produce reversal zone 127,, and produce hot hole 131 in the substrate under grid 103-3 with generation reversal zone 128 under grid 103-4～103-N.Hot hole is injected into the storage area of " bit 3 ", replaces electronics and reduces the threshold voltage of the storage area under the grid 103-3.

In certain embodiments,, apply bias arrangement shown in Figure 15 again,, and can wipe " bit 3 " or other selected bits so that the CHARGE DISTRIBUTION in the storage area reaches balance by applying bias arrangement shown in Figure 14 earlier.

Figure 16 illustrates to being applicable to that wherein this step is to be used for each bit district is applied bias voltage as the erase step flow chart of Figure 14 and bias arrangement shown in Figure 15, with near the generation hot hole in bit district.At first, step 250 begins the total data in the memory cell is wiped, and this memory cell for example is a memory cell shown in Figure 10.Then, in step 251, set index i=1, wherein the grid 1～N in the index i corresponding stored unit.Then, in step 252, (current bit) applies a bias arrangement to existing bit.This bias arrangement can be as shown in figure 14, as shown in figure 15 or other bias arrangement.Next, in step 253, utilize to test whether i=N judges whether bit districts all in the memory cell is wiped free of.Carry out step 254, increase index i, and in step 251, apply the next bit district of bias arrangement to the memory cell.If i equals N, in step 255, carry out erase verification step.Come, in step 256, the judgement memory cell makes does not pass through erase verification step again.Were it not for by, then restart in this embodiment from step 251.If memory cell is by erase verification, then process ends in step 257.Other embodiment comprise the step of wiping most memory cell in parallel, and memory cell in parallel for example is the memory cell of one group of shared same group of bit line.Its handling process can be wiped after step 252 and before the increase index i each bit district and be tested, and carry out step 252 again when authentication failed, to carry out erase verification and retry step.

Figure 17 illustrates an embodiment into as shown in figure 10 multiple grid memory cell, utilization conducts near grid 103-1 and the 103-N electrode zone with source electrode bias voltage and drain bias, and wherein grid 103-1 and 103-N are arranged in the memory cell grid row of semiconductor body.Circuits System 150,151 can the many forever modes of power be finished, and it comprises the doped region electrode that uses as the electrode among Figure 10 101,102, and utilizes with the contact (contact) of conductor thought material and supply voltage to electrode 101,102.Electrode 101,102 can be regional tie point (local contact point), and it is to be disposed at metal level in the integrated circuit or the internal connection-wire structure (not illustrating) in other retes with connection electrode.Optionally, electrode 101,102 can be delegation's multiple grid shared conductor lines, and be coupled to Circuits System, this Circuits System along above-mentioned multiple grid supply voltage to any one.

Figure 18 illustrates to conducting source electrode bias voltage and drain bias another embodiment to the Circuits System of semiconductor body.In this embodiment, first select gridistor to comprise grid 201, be positioned at the doped region and the doped region that is positioned at electrode 203 of electrode 202.The second selection gridistor comprises grid 209, is positioned at the doped region and the doped region that is positioned at electrode 206 of electrode 205.The doped region that is positioned at electrode 202 and electrode 206 is coupled to overall bit line or other bit line structures, to transmit voltage electrode extremely separately.Bias voltage is coupled to the doped region that is positioned at electrode 203 and electrode 205, puts on control voltage SLG1, the SLG2 of grid 201,209 with response.Gate dielectric layer 207 is disposed on the channel region between the electrode 202,203, and wherein gate dielectric layer 207 for example is the silicon dioxide layer of individual layer.Similarly, gate dielectric layer 208 is disposed on the channel region between the electrode 205,206.

Figure 19 illustrates to conducting source electrode bias voltage and drain bias another embodiment to the Circuits System of semiconductor body.In this embodiment, first select grid 210 and second to select grid 211 to be disposed at respectively on semiconductor body and the gate dielectric layer 214,215.First selects grid 210 and second to select grid 211 to be disposed at relative two ends that the grid between the electrode 212,213 is listed as respectively, and continuous channel region is arranged under the charge storaging area of multiple grid memory cell.The difference of Figure 19 and Figure 18 has been to omit the doped region that is positioned at electrode 203 and electrode 205.By selecting grid 210 and second to select to produce the reversal zone under the grid 211 first, apply bias voltage by the doped region that is positioned at electrode 212 and electrode 213, so that voltage self-electrode 212,213 is conducted to channel region continuous under the charge storaging area that is arranged in the multiple grid memory cell.

Figure 20 illustrates to conducting source electrode bias voltage and drain bias another embodiment to the Circuits System of semiconductor body.The difference of Figure 20 and Figure 19 is that charge storing structure extends to first and selects grid 210 and second to select under the grid 211, and wherein charge storing structure comprises top dielectric layer 105, electric charge capture layer 106 and end dielectric layer 107.

Figure 21 illustrates to conducting source electrode bias voltage and drain bias another embodiment to the Circuits System of semiconductor body.The difference of Figure 20 and Figure 10 is that charge storing structure extends to and is positioned on doped region electrode 101 and the electrode 102 that wherein charge storing structure comprises top dielectric layer 105, electric charge capture layer 106 and end dielectric layer 107.

Figure 22 and Figure 23 illustrate the embodiment of the gate memory cell of attaching most importance to, and wherein just are disposed on the storage area and conduct control grid every a grid, to read or to write data.In these two embodiment, select gate configuration between each control grid.In as Figure 22 and embodiment shown in Figure 23, preferably the row of the grid in the multiple grid memory cell comprise the odd number grid.Therefore, the final grid in the column of memory cells can be considered as grid N+1.In Figure 22, the even number grid is as controlling grid with storage data.The data storing structure can be continuous between all grids, or segmented structure as shown in the figure, comes storage data and only be positioned under the control grid.Therefore, for the sequencing of controlling the multiple grid memory cell with read, when grid 174-1,174-3,174-5～174-N+1 as selecting grid when producing the reversal zone, grid 173-2,173-4,173-6～173-N are disposed at charge storaging area 184-2,184-4,184-6～184-N.

In Figure 23, the odd number grid is as controlling grid with storage data.The data storing structure can be continuous between all grids, or segmented structure as shown in the figure, comes storage data and only be positioned under the control grid.Therefore, for the sequencing of controlling the multiple grid memory cell with read, when grid 174-2,174-4,174-6～174-N as selecting grid when producing the reversal zone, grid 173-1,173-3,173-5～173-N+1 are disposed at charge storaging area 184-1,184-3,184-5～184-N+1.

Figure 24 A to Figure 24 F illustrates the making flow process profile into as shown in figure 10 multiple grid memory cell.At first, please refer to Figure 24 A, the semiconductor-based end 300 is provided, substrate 300 for example is p type silicon base or other semiconductor-based ends.In an embodiment of the present invention, substrate 300 utilizes so-called Mitsui (triple-well) technology to isolate, and wherein substrate 300 comprises the p type zone that is embedded in the n type zone, and n type zone is embedded in the p type zone.Be about to form in the basal region of multiple grid memory cell, forming bottom oxide 301, electric charge capture layer 302 and top oxide layer 303.Above-mentioned rete can utilize the various technology of knowing to form, comprise thermal oxidation method, chemical vapour deposition technique, electricity slurry enhanced chemical vapor deposition method, high density plasma enhanced chemical sedimentation, atomic layer deposition method or other that know with emerging technology.

Then, please refer to Figure 24 B, after forming bottom oxide 301, electric charge capture layer 302 and top oxide layer 303, in suprabasil zone formation one deck polysilicon layer 304 or other conductive gate material of being about to form the multiple grid memory cell.Polysilicon layer 304 can utilize the various technology of knowing to form.

Then, please refer to Figure 24 C, polysilicon layer 304 is carried out pattern etched, to form gate electrode 304X.In certain embodiments, gate electrode 304X, inwardly extends in parallel and crosses the zone that forms memory cell with the direction towards the diagram face as word line structure.

Next, please refer to Figure 24 D, cover most gate electrode 304X, comprise the sidewall that covers gate electrode 304X with insulating barrier 305.The material of insulating barrier 305 is an insulating material, for example is silicon dioxide, silicon nitride or other insulating material.Insulating barrier 305 covers the sidewall of gate electrode 304X, and is isolated with the isolated grid of inserting in the space.In one embodiment, the thickness of the insulating barrier 305 on the gate electrode 304X sidewall is less than 100 nanometers.The characteristic size F that has a minimum in an embodiment, and above-mentioned thickness is preferably less than 0.1F.In general, the thickness of insulating barrier is as much as possible little, in fact less than the length of gate electrode 304X.

Come again, please refer to Figure 24 E, deposit second polysilicon layer, between gate electrode 304X, to form gate electrode 306X.The method that forms second polysilicon layer comprises chemical vapour deposition technique or other technologies, can fill up the space effectively.As shown in the figure, gate electrode 306X has the height identical with gate electrode 304X.In other embodiments, not necessarily has identical height between the electrode.In certain embodiments, the technology of planarization can be used the cmp technology.

As generally known, gate electrode 304X and gate electrode 306X can comprise that with silicide or metal be the top layer of material, to promote conductivity.

Afterwards, please refer to Figure 24 F, the charge storing structure that will have bottom oxide 301, electric charge capture layer 302, top oxide layer 303 and polysilicon layer carries out patterning and etching, to expose the ion implanted region territory in the substrate 300.With n type alloy injecting electrode zone, to form source electrode 307 and drain electrode 308.Via Figure 24 A to Figure 24 F, finish and similar multiple grid memory cell shown in Figure 10.Similarly, structural variation can be finished with the technology of knowing apace.

It is the treatment step of an embodiment that Figure 25 illustrates, and wherein in substrate in the doped region of source electrode 307 and drain electrode 308, bottom oxide 301, electric charge capture layer 302 are not removed with top oxide layer 303.Therefore, implantation step is different with Figure 24 F, and it must pass the material layer that is used for forming the charge-trapping structure.

Figure 26 A to Figure 26 D illustrates to making the flow process profile of multiple grid memory cell as shown in figure 22.At first, identical with Figure 24 A to Figure 24 B, the semiconductor-based end 300, be provided.Be about to form in the basal region of multiple grid memory cell, forming bottom oxide 301, electric charge capture layer 302 and top oxide layer 303.Then, please refer to Figure 26 A, finish the memory cell with storage area, this storage area is arranged in the below of memory cell even number grid.In Figure 26 A to Figure 26 D, the memory cell of the storage area of even number grid below.Structure among Figure 24 B is carried out patterning and etching, but different with Figure 24 C, not with top oxide layer 303 as etch stop layer.Above-mentioned etch process passes the material layer (301,302,303) as charge storaging area, and stays stack layer 351～356, and it comprises the charge storaging area that is positioned at polysilicon control grid utmost point below.In the step of Figure 26, form separator 340 with isolation stack layer 351～356, and one deck gate dielectric layer is provided in gap 341～347.Wherein, the material of separator 340 for example is a silicon dioxide.In the step of Figure 26 C, fill up gap 341～347 with polysilicon.In the step of Figure 26 D, inject source electrode 349 and drain 350 to finish memory cell.

Figure 27 is the simplification calcspar according to the integrated circuit that one embodiment of the invention illustrated.Integrated circuit 450 is included in the memory array 400 that forms with multiple grid, the charge capturing storage unit of these memory array 400 small scopes at semiconductor-based the end.Column decoder (row decoder) 401 is coupled to most word lines 402 of multiple grid memory cell and is coupled to the selection gate line, and arranges along the column direction of memory array 400.Row decoder (column decoder) 403 is coupled to most the bit lines of arranging along the column direction of memory array 400 404, with transfer source pole tension and drain voltage, and remembers multiple grid memory cell reading of data in the array 400 certainly.By on bus-bar 405, providing address (address) to row decoder 403 and column decoder 401.Sensing amplifier in square 406 (sense amplifiers) is coupled to row decoder 403 with data input structure (data-in structure) via data bus-bar 407.From the I/O port on the integrated circuit 450 (input/output port) or inner or outside to integrated circuit 450 and the data of coming, provide data input structure to the square 406 via Data In-Line (data-in line) 411 by other Data Sources.Sensing amplifier from square 406 and the data of coming, the I/O port that is fed on the integrated circuit 450 via DOL Data Output Line (data outline) 412, or it is inner or outside to integrated circuit 450 to be fed to other data purposes.

In this example, the controller control bias arrangement of using bias state machine (bias arrangement state machine) to carry out provides the function of voltage (bias arrangement supply voltage) 408, for example read, sequencing, wipe, erase verification and sequencing verifying voltage.Controller can use the specific purposes logic circuitry of knowing (special-purpose logiccircuitry) to carry out.In another embodiment, controller comprises the processor (processor) of general objects, and it can be carried out on identical integrated circuit, carries out the operation of computer program with control element.In other embodiments, utilize processor, can be used as controller in conjunction with specific purposes logic circuitry and general objects.

Figure 28 illustrates and is one embodiment of the invention, and wherein memory cell has 501,502, and is positioned at each control and has two data storage areas under grid.Memory cell comprises the semiconductor-based end 500, and the semiconductor-based end 500 has the n type electrode 503,504 as the source electrode of memory cell and drain electrode.As shown in the figure, charge storaging area has 4 bits, and wherein bit 1-1 and bit 1-2 are positioned under the control grid 501, and bit 2-1 and bit 2-2 are positioned under the control grid 502.Bias voltage Vg ₁With Vg ₂Be applied to control grid 501,502 respectively.In certain embodiments, each region of data storage under each grid in the memory cell can store and surpass 1 bit.According to electrode in the memory cell as the function of source electrode or the function of drain electrode, apply bias voltage Vs to electrode 503,504 one of them, and bias voltage Vd another to the electrode 503,504.Apply bias voltage Vb to substrate 500.Apply bias arrangement to carry out sequencing in charge storage region, to wipe and reading of data.

Figure 29 and Figure 30 illustrate to being erased at the selectable bias arrangement of the storage area under the specific grid.In the bias arrangement of Figure 29, by the positive grid voltage Vg that applies about 8V ₁To controlling grid 501, apply about 0V to controlling grid 502, and apply pact-10V, generation FN tunnelling (symbol 505 is represented) between the charge-trapping district under substrate 500 and the control grid 501 to source electrode 503, drain electrode 504 and substrate 500.The FN tunnelling makes the threshold voltage of memory cell increase, and has set up high threshold voltage erase status.In the bias arrangement of Figure 30, when source electrode 503 and drain electrode 504 suspension joints, by the negative grid voltage Vg that applies pact-8V ₁ To controlling grid 501, apply about 0V to controlling grid 502, and apply about 10V, at control grid 501 and control generation FN tunnelling (symbol 506 is represented) between the charge-trapping district under the grid 501 to substrate 500.The FN tunnelling makes the threshold voltage of memory cell increase, and has set up high threshold voltage erase status.

Figure 31 to Figure 34 illustrates to injecting based on hot hole, and to two bias arrangement that charge storaging area carries out sequencing under each grid in the memory cell, it is suitable for and will be used in combination with the bias arrangement of wiping among Figure 30 as Figure 29.As shown in figure 31, inject, bit 1-1 sequencing wherein can be controlled grid 501 and received Vg by the hot hole that uses bias arrangement as shown in the figure ₁=-5V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=+5V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 510 in control grid 502 belows, and causes high relatively voltage on control grid 502.In addition, the caused hot hole in contiguous n+ injection region in channel region, with symbol 511 expressions, the iunjected charge memory structure, replacing electronic also reduces the threshold voltage of memory cell in charge storaging area for bit 1-1.Wherein, the n+ injection region is as the usefulness of electrode 503.

Shown in figure 32, inject, bit 1-2 sequencing wherein can be controlled grid 501 and received Vg by the hot hole that uses bias arrangement as shown in the figure ₁=-5V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+5V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 512 in control grid 502 belows, and causes high relatively voltage on control grid 502.In addition, contiguous reversal zone 512 caused hot holes in channel region, with symbol 513 expressions, the iunjected charge memory structure, replacing electronic also reduces the threshold voltage of memory cell in charge storaging area for bit 1-2.

As shown in figure 33, inject, bit 2-1 sequencing wherein can be controlled grid 501 and received Vg by the hot hole that uses bias arrangement as shown in the figure ₁=+10V, control grid 502 receives Vg ₂=-5V, electrode 503 receives Vs=+5V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 514 in control grid 501 belows, and causes high relatively voltage on control grid 501.In addition, contiguous reversal zone 514 caused hot holes in channel region, with symbol 515 expressions, the iunjected charge memory structure, replacing electronic also reduces the threshold voltage of memory cell in charge storaging area for bit 2-1.

As shown in figure 34, inject, bit 2-2 sequencing wherein can be controlled grid 501 and received Vg by the hot hole that uses bias arrangement as shown in the figure ₁=+10V, control grid 502 receives Vg ₂=-5V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+5V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 516 in control grid 501 belows, and causes high relatively voltage on control grid 501.In addition, the caused hot hole in contiguous n+ injection region in channel region, with symbol 517 expressions, the iunjected charge memory structure, replacing electronic also reduces the threshold voltage of memory cell in charge storaging area for bit 2-2.Wherein, the n+ injection region is as the usefulness of electrode 504.

Figure 35 to Figure 38 illustrates to two bias arrangement that charge storaging area reads under each grid in the memory cell, and it is suitable for as wiping bias arrangement and be used in combination as the sequencing bias arrangement among Figure 31 to Figure 34 among Figure 29 and Figure 30.As shown in figure 35, use counter-rotating is as shown in the figure read bias arrangement and can be read bit 1-1, wherein controls grid 501 and receives Vg ₁=2V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+2V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 510 in control grid 502 belows, and causes high relatively voltage on control grid 502.Read bias arrangement for counter-rotating, be stored in the electric charge in the zone of bit 1-1, the threshold value bias voltage of memory cell is fixed.If be wiped free of in the charge storage region of bit 1-1 and set up high threshold voltage state, then do not have current flowing under the bias arrangement reading.Selectively, if set up low threshold voltage state by sequencing, reading the raceway groove that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 1-1.

As shown in figure 36, use counter-rotating is as shown in the figure read bias arrangement and can be read bit 1-2, wherein controls grid 501 and receives Vg ₁=+2V, control grid 502 receives Vg ₂=+10V, electrode 503 receives Vs=+2V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 512 in control grid 502 belows, and causes high relatively voltage on control grid 502.If be wiped free of in the charge storage region of bit 1-2 and set up high threshold voltage state, then do not have current flowing under the bias arrangement reading.Selectively, if set up low threshold voltage state by sequencing, reading the raceway groove that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 1-2.

As shown in figure 37, use counter-rotating is as shown in the figure read bias arrangement and can be read bit 2-1, wherein controls grid 501 and receives Vg ₁=+10V, control grid 502 receives Vg ₂=+2V, electrode 503 receives Vs=0V, and electrode 504 receives Vd=+2V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 514 in control grid 501 belows, and causes high relatively voltage on control grid 501.If be wiped free of in the charge storage region of bit 2-1 and set up high threshold voltage state, then do not have current flowing under the bias arrangement reading.Selectively, if set up low threshold voltage state by sequencing, reading the raceway groove that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 2-1.

As shown in figure 38, use counter-rotating is as shown in the figure read bias arrangement and can be read bit 2-2, wherein controls grid 501 and receives Vg ₁=+10V, control grid 502 receives Vg ₂=+2V, electrode 503 receives Vs=+2V, and electrode 504 receives Vd=0V, and substrate receives Vb=0V.This bias arrangement causes reversal zone 516 in control grid 501 belows, and causes high relatively voltage on control grid 501.If be wiped free of in the charge storage region of bit 2-2 and set up high threshold voltage state, then do not have current flowing under the bias arrangement reading.Selectively, if set up low threshold voltage state by sequencing, reading the raceway groove that then has the current flowing memory cell under the bias arrangement in the charge storage region of bit 2-2.

The memory cell structure of Figure 28 has two grids, and each grid and two storage areas get in touch, and this kind memory cell structure extends the embodiment among Figure 39, and it has N grid, and N is greater than 2.Multiple grid memory cell among Figure 39 is formed in the semiconductor body 600 with p type alloy.N-type electrode 601,602 is as the source electrode and the drain electrode of multiple grid memory cell.Charge storing structure comprises top dielectric layer 605, the electric charge capture layer 606 and end dielectric layer 607 on the continuous channel region between the electrode 601,602.Control grid 603-1～603-N is positioned on charge storing structure and the channel region.According to illustrated embodiment, each control grid 603-1～603-N and two charge storaging areas are got in touch.Therefore, as shown in the figure, charge storaging area 604-1-1,604-1-2 and control grid 603-1 get in touch.Charge storaging area 604-2-1,604-2-2 and control grid 603-2 get in touch.Charge storaging area 604-3-1,604-3-2 and control grid 603-3 get in touch.Charge storaging area 604-4-1,604-4-2 and control grid 603-4 get in touch.Charge storaging area 604-5-1,604-5-2 and control grid 603-5 get in touch.Charge storaging area 604-6-1,604-6-2 and control grid 603-6 get in touch.Charge storaging area 604-(N-1)-1,604-(N-1)-2 and control grid 603-(N-1) contact.Charge storaging area 604-N-1,604-N-2 and control grid 603-N get in touch.Circuits System and memory cell are got in touch provides bias voltage, with sequencing, wipe and read the data that are stored in the charge storaging area.Bias voltage comprises the Vg that is applied to respectively on control grid 603-1～603-N ₁～Vg _NBias voltage comprises Vs that is applied to electrode 601 and the Vd that is applied to electrode 602.At last, bias voltage comprises the Vb that is applied to semiconductor body 600.Semiconductor body 600 is included in the insulation layer among more above-mentioned embodiment, and it is arranged in the big semiconductor-based end.

Figure 40 to Figure 45 illustrate for be used for wiping, sequencing and read in the typical bias arrangement of memory cell.

Figure 40 and Figure 41 illustrate and are alternative bias arrangement.In Figure 40, use positive grid voltage FN tunnelling bias arrangement to wipe and in the multiple grid memory cell, be positioned at the charge storaging area of selecting under the grid.Therefore, according to the bias arrangement among Figure 40, apply the Vg of pact+8V ₁, Vg ₃, Vg ₄, Vg ₆, Vg ( _N-1)With Vg _NAnd the Vg of 0V ₂, Vg ₅Wipe selected control grid 603-1,603-3,603-4,603-6,603-N-1 and 603-N with Vd and the Vb of-10V.This bias arrangement cause electronics from the substrate tunnelling to charge storing structure, as be positioned at shown in symbol 610-1,610-3,610-4,610-6,610-N-1 and the 610-N of selected control grid 603-1,603-3,603-4,603-6,603-N-1 and 603-N below.For the storage area of getting in touch with each selected control grid, electron tunneling makes threshold voltage increase to the erase threshold voltage of target.Not selected control grid 603-2,603-5 receives the grid voltage of about 0V, and it is not enough to cause the enough serious electron tunneling that disturbs the threshold voltage state of before having set up in not selected memory cell.

Figure 41 illustrates and is negative grid voltage FN tunnelling bias arrangement.According to the bias arrangement among Figure 41, apply the Vg of pact-8V ₁, Vg ₃, Vg ₄, Vg ₆, Vg ( _N-1)With Vg _NAnd the Vg of 0V ₂, Vg ₅Wipe selected control grid 603-1,603-3,603-4,603-6,603-N-1 and 603-N with Vd and the Vb of+10V.This bias arrangement causes that electronics is from controlling grid 603-1,603-3,603-4,603-6,603-N-1 and 603-N tunnelling to charge storing structure, shown in symbol 611-1,611-3,611-4,611-6,611-N-1 and 611-N.For the storage area of getting in touch with each selected control grid, electron tunneling makes threshold voltage increase to the target erase threshold voltage.Not selected control grid 603-2,603-5 receives the grid voltage of about 0V, and it is not enough to cause the enough serious electron tunneling that disturbs the threshold voltage state of before having set up in not selected memory cell.

The hot hole that Figure 42 and Figure 43 illustrate to causing for the memory cell among Figure 39 injects, and with band band tunnelling (band-to-band tunnelin) is carried out left side and right side sequencing.Use the bias arrangement among Figure 42 that sequencing is carried out in the storage area in left side, the storage area in this left side for example is the charge storaging area 604-5-1 of grid 603-5 below.According to the bias arrangement among Figure 42, Xuan Ding control grid 603-1～603-4 and 603-6～603-N does not receive for example high voltage of about+10V, and selected control grid 603-5 receives the Vg of pact-5V ₅Electrode 601 receives the Vs of pact+5V, and electrode 602 receives the Vd of about 0V.Similarly, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 615,616, and wherein reversal zone 615,616 couples the channel region of electrode 601,602 to control grid 603-5 below.The band of the hot hole that causes is caused the edge of the reversal zone 615 of band tunnelling below control grid 603-5, and iunjected charge storage area 604-5-1, enough reduce the sequencing state of the threshold voltage of the storage area of getting in touch with selected control grid 603-5, left side to target, this band is to being with tunnelling with symbol 617 expressions.

Figure 43 illustrates the bias arrangement of carrying out sequencing for to the storage area of getting in touch with selected grid, right side.Use the bias arrangement among Figure 43 that sequencing is carried out in the storage area on right side, the storage area on this right side for example is the charge storaging area 604-3-2 of grid 603-3 below.According to the bias arrangement among Figure 43, Xuan Ding control grid 603-1～603-2 and 603-4～603-N does not receive for example high voltage of about+10V, and selected control grid 603-3 receives the Vg of pact-5V ₅Electrode 601 receives the Vs of about 0V, and electrode 602 receives the Vd of pact+5V.Similarly, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 625,626, and wherein reversal zone 625,626 couples the channel region of electrode 601,602 to control grid 603-3 below.The band of the hot hole that causes is caused the edge of the reversal zone 626 of band tunnelling below control grid 603-3, and iunjected charge storage area 604-3-2, enough reduce the sequencing state of the threshold voltage of the storage area of getting in touch with selected control grid 603-3, left side to target, this band is to being with tunnelling with symbol 627 expressions.

Figure 44 and Figure 45 illustrate to reading bias arrangement for the left side of the memory cell of Figure 39 and the counter-rotating on right side.Use the bias arrangement among Figure 44 that the storage area in left side is read, the storage area in this left side for example is the charge storaging area 604-5-1 of control grid 603-5 below.According to the bias arrangement among Figure 44, Xuan Ding control grid 603-1～603-4 and 603-6～603-N does not receive for example high voltage of about+10V, and selected control grid 603-5 receives the Vg of pact+2V ₅Electrode 601 receives the Vs of about 0V, and electrode 602 receives the Vd of pact+2V.Similarly, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 635,636, and wherein reversal zone 635,636 couples the channel region of electrode 601,602 to control grid 603-5 below.If charge storaging area 604-5-1 has high threshold voltage state (wiping), then electric current is locked between the electrode 601,602.Selectively, if charge storaging area 604-5-1 has low threshold voltage state (sequencing), then between electrode 601,602, cause electric current.This electric current can be represented that data storing is in charge storaging area 604-5-1 by detecting.

Use the bias arrangement among Figure 45 that the storage area on right side is read, the storage area on this right side for example is the charge storaging area 604-3-2 of control grid 603-3 below.According to the bias arrangement among Figure 45, Xuan Ding control grid 603-1,603-2 and 603-4～603-N does not receive for example high voltage of about+10V, and selected control grid 603-3 receives the Vg of pact+2V ₅Electrode 601 receives the Vs of pact+2V, and electrode 602 receives the Vd of about 0V.Similarly, substrate receives the Vb of about 0V.High relatively voltage on not selected control grid produces reversal zone 645,646, and wherein reversal zone 645,646 couples the channel region of electrode 601,602 to control grid 603-3 below.If charge storaging area 604-3-2 has high threshold voltage state (wiping), then electric current is locked between the electrode 601,602.Selectively, if charge storaging area 604-3-2 has low threshold voltage state (sequencing), then between electrode 601,602, cause electric current.This electric current can be represented that data storing is in charge storaging area 604-3-2 by detecting.

Figure 46 to Figure 51 illustrates the typical embodiment into the array layout of multiple grid memory, and it uses the symbol among Figure 11.Illustrated array layout can use the embodiment at independent and a plurality of bits of each memory cell of each memory cell, as described above, be included in the embodiment that stores in each storage area of getting in touch with each control grid above a bit.

It is the first layout embodiment that Figure 46 illustrates, and wherein multiple grid memory cell 700～706 has structure shown in Figure 180, and multiple grid memory cell 700～706 is along with bit line BL _N-3～BL _N+3Layout.Be arranged in parallel word line to transmit bias voltage Vg ₁～Vg _NRelevant grid to the multiple gate memory cell.Bit line BL _N-3～BL _N+3Be arranged transmit bias voltage Vs and bias voltage Vd one of them, pass respectively and select the lower electrode of grid 710～716 to multiple gate memory cell 700～706.Select grid 710～716 to be coupled to the bias line that is arranged in parallel with word line, and delivery controlling signal SLG2.In addition, bit line BL _N-3To bit line BL _N+3Arrange and to transmit among bias voltage Vs and the bias voltage Vd another, pass respectively selection grid 720～726 to multiple gate memory cell 700～706 to the top electrode.Select grid 720～726 to be coupled to the bias line that is arranged in parallel with word line, and delivery controlling signal SLG1.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use source electrode or the drain electrode that is coupled to selection grid 710～716 or selection grid 720～726 as contact window 718,728.In illustrated array layout, multiple grid memory cell 706 is respectively by selecting grid 716,726 and bit line BL _N+3, BL _N+2Couple.Multiple grid memory cell 705 is respectively by selecting grid 715,725 and bit line BL _N+1, BL _N+2Couple.Multiple grid memory cell 704 is respectively by selecting grid 714,724 and bit line BL _N+1, BL _NCouple.Multiple grid memory cell 703 is respectively by selecting grid 713,723 and bit line BL _N-1, BL _NCouple.Multiple grid memory cell 702 is respectively by selecting grid 712,722 and bit line BL _N-1, BL _N-2Couple.Multiple grid memory cell 701 is respectively by selecting grid 711,721 and bit line BL _N-3, BL _N-2Couple.Multiple grid memory cell 700 is respectively by selecting grid 710,720 and bit line BL _N-3, BL _N-4(not illustrating) couples.In the embodiment of Figure 46, the multiple grid memory cell is arranged in parallel, and selects grids to come being connected of multiple grid memory cell independent in the array of controls and bit line with two.The source electrode of two adjacent stored parallel unit is coupled in together, and is coupled to independent bit line.Similarly, the drain electrode of two adjacent stored parallel unit is coupled in together, and is coupled to independent bit line.

Figure 47 illustrates and is selectable layout embodiment, and wherein multiple grid memory cell 700～706 has structure shown in Figure 180, and multiple grid memory cell 700～706 is along with bit line BL _N-3To bit line BL _N+3Layout.Be arranged in parallel word line to transmit bias voltage Vg ₁～Vg _NRelevant grid to the multiple gate memory cell.Bit line BL _N-3～BL _N+3Be arranged transmit bias voltage Vs and bias voltage Vd one of them, pass respectively and select the upper electrode of grid 720～726 to multiple gate memory cell 700～706.In addition, the horizontal source electrode line 719 that forms with the doped region that buries or metal level is arranged and transmits bias voltage Vs, passes respectively and selects the lower electrode of grid 710～716 to multiple gate memory cell 700～706.Select grid 710～716 to be coupled to the bias line that is arranged in parallel with word line, and delivery controlling signal SLG2.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use the drain electrode that is coupled to selection grid 720～726 as contact window 728.In illustrated array layout, multiple grid memory cell 706 is respectively by selecting grid 716,726 and bit line BL _N+3, source electrode line 719 couples.Multiple grid memory cell 705 by select grid 725 respectively with bit line BL _N+2, source electrode line 719 couples.Multiple grid memory cell 704 by select grid 724 respectively with bit line BL _N+1, source electrode line 719 couples.Multiple grid memory cell 703 by select grid 723 respectively with bit line BL _N, source electrode line 719 couples.Multiple grid memory cell 702 is respectively by selecting grid 722 and bit line BL _N-1, source electrode line 719 couples.Multiple grid memory cell 701 is respectively by selecting grid 721 and bit line BL _N-2, source electrode line 719 couples.Multiple grid memory cell 700 is respectively by selecting grid 720 and bit line BL _N-3, source electrode line 719 couples.In the embodiment of Figure 47, the source electrode of whole stored parallel unit is coupled in together in this district, and is coupled to the horizontal source electrode line vertical with bit line direction.The drain electrode of each multiple grid memory cell is coupled to independent bit line, and not shared with contiguous bit line.

Figure 48 illustrates and is another layout embodiment, and it is similar to the layout among Figure 46.Arrange and select grid 720～726 and 710～716, by once only there being a multiple grid memory cell to be connected to a bit lines, so that decoding function to be provided.Specifically, select the gate electrode of grid 721,723 and 725 to be coupled to controlling signal SLG1, and select the gate electrode of grid 720,722,724 and 726 to be coupled to controlling signal SLG2.Similarly, select the gate electrode of grid 711,713 and 715 to be coupled to controlling signal SLG4, and select the gate electrode of grid 710,712,714 and 716 to be coupled to controlling signal SLG3.In addition configuration is all described similar to Figure 46.In the embodiment of Figure 48, select grid to control the independent multiple grid memory cell of being connected to of bit line by two.The source electrode of two adjacent stored parallel unit is coupled in together, and is coupled to independent bit line.Similarly, the drain electrode of two adjacent stored parallel unit is coupled in together, and is coupled to independent bit line.Selecting grid is to be used for controlling contiguous stored parallel unit can not be connected to shared bit line at one time.

It is the 3rd layout embodiment that Figure 49 illustrates, and wherein multiple grid memory cell 740～746 has structure shown in Figure 20, and multiple grid memory cell 740～746 is along with bit line BL _N-3To bit line BL _N+3Layout.Be arranged in parallel word line to transmit bias voltage Vg ₁～Vg _NRelevant grid to the multiple gate memory cell.Bit line BL _N-3～BL _N+3Be arranged and transmit bias voltage Vs and one of them upper electrode of bias voltage Vd respectively to multiple gate memory cell 740～746.

Top control grid 750～756 in the multiple grid memory cell is coupled to the bias line that is arranged in parallel with word line, and delivery controlling signal SLG1.In addition, bit line BL _N-3～BL _N+3Arrange transmit respectively among bias voltage Vs and the bias voltage Vd another extremely multiple gate memory cell 740～746 to lower electrode.Bottom control grid 760～766 is coupled to the bias line that is arranged in parallel with word line, and delivery controlling signal SLG2.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use source electrode or the drain electrode that is coupled to selection grid 710～716 or selection grid 720～726 as contact window 748,749.In illustrated array layout, multiple grid memory cell 746 is coupled to bit line BL respectively _N+3, BL _N+2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 746 control grid and bottom control grid.Multiple grid memory cell 745 is coupled to bit line BL respectively _N+1, BL _N+2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 745 control grid and bottom control grid.Multiple grid memory cell 744 is coupled to bit line BL respectively _N+1, BL _N, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 744 control grid and bottom control grid.Multiple grid memory cell 743 is coupled to bit line BL respectively _N-1, BL _N, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 743 control grid and bottom control grid.Multiple grid memory cell 742 is coupled to bit line BL respectively _N-1, BL _N-2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 742 control grid and bottom control grid.Multiple grid memory cell 741 is coupled to bit line BL respectively _N-3, BL _N-2, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 741 control grid and bottom control grid.Multiple grid memory cell 740 is coupled to bit line BL respectively _N-3, BL _N-4(not illustrating) is to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 740 control grid and bottom control grid.Operate top control grid and bottom control grid in each memory cell and keep the storage area got in touch with it, allow top control grid in each memory cell and bottom to control grid and can replace as the selection grid 710～716 and 720～726 in the array implement example of Figure 46 in low threshold voltage state.In the embodiment of Figure 49, the multiple grid memory cell is arranged in parallel, and selects grids to come being connected of multiple grid memory cell independent in the array of controls and bit line with two.The source electrode of two adjacent stored parallel unit is coupled in together, and is coupled to independent bit line.Similarly, the drain electrode of two adjacent stored parallel unit is coupled in together, and is coupled to independent bit line.

It is the 4th layout embodiment that Figure 50 illustrates, and wherein multiple grid memory cell 740～746 has structure shown in Figure 20, and multiple grid memory cell 740～746 is along with bit line BL _N-3～BL _N+3Layout.Be arranged in parallel word line to transmit bias voltage Vg ₁～Vg _NRelevant grid to the multiple gate memory cell.Bit line BL _N-3～BL _N+3Be arranged and transmit the upper electrode of bias voltage Vd respectively to multiple gate memory cell 740～746.Top control grid 750～756 in the multiple grid memory cell is coupled to the bias line that is arranged in parallel with word line, and delivery controlling signal SLG1.In addition, the horizontal source electrode line 769 that forms with the doped region that buries or metal level is arranged and transmits the lower electrode of bias voltage Vs to multiple gate memory cell 740～746.Bottom control grid 760～766 is coupled to the bias line that is arranged in parallel with word line, and delivery controlling signal SLG2.Bit line BL _N-3～BL _N+3Generally on integrated circuit, use metal level to implement, and use the drain electrode that is coupled to the multiple grid memory cell as contact window 758.In illustrated array layout, multiple grid memory cell 746 is coupled to bit line BL respectively _N+3With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 746 control grid and bottom control grid.Multiple grid memory cell 745 is coupled to bit line BL respectively _N+2With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 745 control grid and bottom control grid.Multiple grid memory cell 744 is coupled to bit line BL respectively _N+1With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 744 control grid and bottom control grid.Multiple grid memory cell 743 is coupled to bit line BL respectively _NWith source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 743 control grid and bottom control grid.Multiple grid memory cell 742 is coupled to bit line BL respectively _N-1With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 742 control grid and bottom control grid.Multiple grid memory cell 741 is coupled to bit line BL respectively _N-2With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 741 control grid and bottom control grid.Multiple grid memory cell 740 is coupled to bit line BL respectively _N-3With source electrode line 769, to respond signal SLG1, the SLG2 on the top of multiple grid memory cell 740 control grid and bottom control grid.Operate top control grid and bottom control grid in each memory cell and keep the storage area got in touch with it, allow top control grid in each memory cell and bottom to control grid and can replace as the selection grid 710～716 and 720～726 in the array implement example of Figure 47 in low threshold voltage state.In the embodiment of Figure 50, the source electrode of whole stored parallel unit is coupled in together in this district, and is coupled to the horizontal source electrode line vertical with bit line direction.The drain electrode of each multiple grid memory cell is coupled to independent bit line, and not shared with contiguous bit line.

Figure 51 illustrates the layout into memory block, and this memory block comprises a plurality of sections of multiple grid memory cell, and these sections are similar to the section among Figure 46.This kind layout also can be utilized the section structure at Figure 47 to Figure 50.In Figure 51, show first section 800 and second section 801.Between first section 800 and these two sections of the shared position of second section 801 in contact hole 802,803,804 and 805.First section 800 and the position shared contact hole 806,807 and 808 of section thereon, this two section has identical layout.Similarly, second section 801 and the position shared contact hole 809,810 and 811 of section thereon, this two section has identical layout.Repeat above-mentioned section forming a memory block, and repeat these blocks on integrated circuit, to form a big array.In alternate embodiments, first section 800 and second section 801 can dispose in the mirror image mode around shared contact hole.Array can utilize in highdensity memory component as shown in figure 27, and this array comprises most memory blocks shown in Figure 51.

In the embodiment of Figure 46 to Figure 48 and Figure 51, though each select grid between a multiple grid memory cell is only arranged, other embodiment be included in each select grid between surpass a multiple grid memory cell.Similarly, Figure 48 and Figure 49 illustrate being connected between the contact hole of bit line or being connected between the contact hole of the bit line in the horizontal source electrode line, have the array of independent multiple grid memory cell in column of memory cells.In other embodiments, a plurality of multiple grid memory cell can be arranged in column of memory cells, upper gate with column of memory cells middle and upper part multiple grid memory cell is selected grid as top, and selects grid with the bottom grid of column of memory cells middle and lower part multiple grid memory cell as the bottom.

The highdensity memory that above-described technology provides each memory cell can store a plurality of bits, single making made between it can use.In addition, sequencing can utilize low-power to carry out with the operation of wiping.

Though the present invention discloses as above with embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims

1, a kind of integrated circuit memory element is characterized in that it comprises:

The semiconductor main body;

A most grid, arranged in series are isolated those adjacent grids with most insulating elements on this semiconductor body, those grids form grid row, and those grids comprise a first grid and the final grid in these grid row;

One charge storing structure is disposed on this semiconductor body, and wherein this charge storing structure is continuous structure, and this charge storing structure comprises most charge-trapping zones, and those charge-trapping zones are arranged in these grid row and surpass those grids below;

One first Circuits System is in being listed as in order to conduction source electrode bias voltage and drain bias to this grid near this first grid and near this semiconductor body this final grid;

One second circuit system is in order to conduct grid bias to those grids;

Wherein this semiconductor body comprises a continuous multiple grid channel region, and this multiple grid channel region is arranged under those grids of this grid row, and this multiple grid channel region have n type conductivity and p type conductivity one of them; And

One controller is controlled this first Circuits System and this second circuit system, and to set up most bias arrangement, with storage data in two charge-trapping zones, wherein this two charge-trappings zone is arranged in each these grid row above those grids below.

2, integrated circuit memory element according to claim 1 is characterized in that wherein said charge-trapping zone is positioned at all those grid belows.

3, integrated circuit memory element according to claim 1 it is characterized in that wherein said first Circuits System comprises one first electric conducting material that is arranged as bit line, and this second circuit system comprises one second electric conducting material that is arranged as word line.

4, integrated circuit memory element according to claim 1, it is characterized in that wherein said first Circuits System comprise one first electric conducting material that is arranged as bit line, be arranged in this first grid of contiguous these grid row of this semiconductor body a first region territory, be arranged in a second electrode region of this final grid of contiguous these grid row of this semiconductor body, wherein this first region territory and this second electrode region have n type conductivity and p type conductivity one of them; And an element, be suitable for selectivity connect this first region territory and this second electrode district at least one of them to bit line.

5, integrated circuit memory element according to claim 1, it is characterized in that wherein said first Circuits System comprise one first electric conducting material that is arranged as bit line, be arranged in this first grid of contiguous these grid row of this semiconductor body a first region territory, be arranged in a second electrode region of this final grid of contiguous these grid row of this semiconductor body, wherein this first region territory and this second electrode region have n type conductivity and p type conductivity one of them.

6, integrated circuit memory element according to claim 1, it is characterized in that wherein said first Circuits System comprises a bit line, this bit line comprises an additional gate, this first grid of contiguous these grid row and being positioned on this multiple grid channel region, after through selection, this additional gate is coupled to a decoding circuit system and this multiple grid channel region is coupled to this bit line.

7, integrated circuit memory element according to claim 1, it is characterized in that wherein said first Circuits System comprises one first bit line and one second bit line, this first bit line and this second bit line comprise this first grid of contiguous these grid row and are positioned at this final grid of one first additional gate and contiguous these grid row on this multiple grid channel region and are positioned at one second additional gate on this multiple grid channel region, after through selection, this first additional gate and this second additional gate are coupled to the decoding circuit system and this multiple grid channel region are coupled to this first bit line and this second bit line.

8, integrated circuit memory element according to claim 1, it is characterized in that wherein said charge storing structure comprises piles up dielectric layer, and this piles up dielectric layer and comprises: end dielectric layer, charge-trapping dielectric layers and top dielectric layer.

9, integrated circuit memory element according to claim 1, it is characterized in that wherein said charge storing structure comprises piles up dielectric layer, this piles up dielectric layer and comprises: end dielectric layer, charge-trapping dielectric layers and top dielectric layer, and wherein this charge-trapping dielectric layers is made up of silicon nitride.

10, integrated circuit memory element according to claim 1 is characterized in that wherein said grid row comprise above two grids, and this charge storing structure comprises that this grid is positioned at most charge-trapping zones that surpass under two those grids in being listed as.

11, integrated circuit memory element according to claim 1, it is characterized in that wherein said controller implements a sequencing step, an erase step and a read step, wherein this sequencing step comprises and sets up a low threshold voltage state, and this erase step comprises and sets up a high threshold voltage state.

12, a kind of integrated circuit memory element is characterized in that it comprises:

The semiconductor main body;

A most word line extend through this semiconductor body;

A most bit line pass this semiconductor body with those word line vertical arrangements;

One decoding circuit system is positioned on this semiconductor body, and this decoding circuit system is coupled to those word lines and those bit lines;

An array comprises most multiple grid storage elements, and this array is coupled to those word lines and those bit lines, and wherein those multiple grid storage elements comprise respectively:

A most grid are arranged in the grid row, and those grids are coupled to the word line in those word lines respectively, and wherein most individual grids comprise a first grid and the final grid in these grid row, and isolate those adjacent grids in these grid row with insulating component;

One charge storing structure is positioned on this semiconductor body, and wherein this charge storing structure is continuous structure, and this charge storing structure comprises most charge-trapping zones, is arranged in these grid row and surpasses under those grids; And

One multiple grid channel region, this multiple grid channel region be continuous and be arranged under those grids of these grid row, wherein this multiple grid channel region have n type conductivity and p type conductivity one of them;

An one source pole electrode and a drain electrode are arranged near this first grid and this final grid of this grid row, and this source electrode and this drain electrode one of them one of is coupled in those bit lines bit line at least; And

One controller, control one first Circuits System and a second circuit system, to set up most bias arrangement, with storage data in two charge-trapping zones, wherein this two charge-trappings zone is arranged in each these grid row above those grids below, for being arranged in two storage areas that each these grid row surpasses those grids below, this controller is arranged to control a sequencing step, one erase step and a read step, wherein this first Circuits System is in order to conduction source electrode bias voltage and drain bias, and this second circuit system is in order to the conduction grid bias.

13, integrated circuit memory element according to claim 12 is characterized in that wherein said charge-trapping zone is positioned at all those grid belows.

14, integrated circuit memory element according to claim 12, it is characterized in that wherein said source electrode comprises a first region, this first grid in semiconductor body in contiguous these grid row, and this drain electrode comprises one second electrode district, this final grid in semiconductor body in contiguous these grid row, wherein this first region and this second electrode district have n type conductivity and p type conductivity one of them.

15, integrated circuit memory element according to claim 12, it is characterized in that wherein said source electrode comprises a first region, this first grid in semiconductor body in contiguous these grid row, and this drain electrode comprises one second electrode district, this final grid in semiconductor body in contiguous these grid row, wherein this first region and this second electrode district have n type conductivity and p type conductivity one of them; And an element, be coupled to this decoding circuit system, this element be suitable for selectivity connect this first region and this second electrode district at least one of them to those bit lines.

16, integrated circuit memory element according to claim 12, it is characterized in that wherein those multiple grid storage elements comprise an additional gate respectively, this first grid of contiguous these grid row and being positioned on this multiple grid channel region, when through after selecting, this additional gate be coupled to this decoding circuit system and with this multiple grid channel region be coupled to this source electrode and this drain electrode one of them.

17, integrated circuit memory element according to claim 12, it is characterized in that wherein said charge storing structure comprises piles up dielectric layer, a charge-trapping dielectric layers and a top dielectric layer, and wherein this piles up dielectric and comprises an end dielectric layer.

18, integrated circuit memory element according to claim 12, it is characterized in that wherein said charge storing structure comprises piles up dielectric layer, a charge-trapping dielectric layers and a top dielectric layer, wherein this piles up dielectric and comprises an end dielectric layer, and wherein this charge-trapping dielectric layers is made up of silicon nitride.

19, integrated circuit memory element according to claim 12, it is characterized in that wherein said sequencing step comprises sets up a bias arrangement to those multiple grid storage elements in this array, this bias arrangement cause the hole inject tunnelling to this two charge-trappings district that is arranged in this grid row one selected grid below one of them.

20, integrated circuit memory element according to claim 12, it is characterized in that wherein said read step comprises sets up a bias arrangement to those multiple grid storage elements in this array, this bias arrangement comprises and applies source electrode bias voltage, drain bias and grid bias, in one of them, cause that current flowing is to respond a threshold voltage with this two charge-trappings district below the selected grid in this grid row.

21, integrated circuit memory element according to claim 12, it is characterized in that wherein said erase step comprises sets up a bias arrangement to those multiple grid storage elements in this array, and this bias arrangement comprises that electronics injects tunnelling to this two charge-trappings district that is arranged in these those grids of grid row one of them or more belows.

22, integrated circuit memory element according to claim 12, it is characterized in that wherein said grid row comprise above two grids, and this charge storing structure comprises that this grid is positioned at most charge-trapping zones that surpass under two those grids in being listed as.

23, a kind of method of operation of integrated circuit memory element, it is characterized in that this integrated circuit memory element comprises the semiconductor main body, most the grids and those grids that are positioned at arranged in series on this semiconductor body form grid row, those grids have a first grid and a final grid in these grid row, and isolate those contiguous in this grid row grids and a charge storing structure that is positioned on this semiconductor body with insulating component, wherein this charge storing structure is continuous structure, and wherein this charge storing structure comprises that being arranged in this grid is listed as most charge-trapping zones that surpass those grids below, wherein this semiconductor body comprises a continuous multiple grid channel region that is arranged in those grids belows of this grid row, this multiple grid channel region have n type conductivity and p type conductivity one of them; The method of operation of this integrated circuit memory element is included on the selected grid and applies a bias arrangement with the sequencing data, this bias arrangement is carried out sequencing to being arranged in the selected charge-trapping zone that this grid row should selected grid below, and this bias arrangement comprises:

The substrate bias condition that applies in this multiple grid channel region is to this semiconductor body;

This first grid and this final grid apply the one source pole bias condition to this semiconductor body near one of them in this grid row;

This first grid and this final grid wherein apply a drain bias condition to this semiconductor body near another in these grid row; And

In these grid row, apply most grid bias conditions to those grids, select the grid lower zone with conduction source electrode bias voltage and drain bias to being somebody's turn to do, wherein those grid bias conditions comprise a sequencing voltage and a reversal voltage, wherein this sequencing voltage on this selected grid in these grid row is with respect to this substrate bias condition, and this source electrode bias condition and this drain bias condition comprise source electrode bias voltage and drain bias in this semiconductor body, enough reduce electron injection current to be positioned at select this fixed grid utmost point below two charge-trappings zone one of them, to set up a low threshold voltage state, this reversal voltage on other grids in these grid row enough reduces the counter-rotating in this multiple grid channel region, and do not have effective electronics or hole to be injected into to be positioned at most charge storaging areas of those other grids belows, wherein this multiple grid channel region is positioned at those other grids belows.

24, the method for operation of integrated circuit memory element according to claim 23 is characterized in that it more comprises to apply a bias arrangement to read, and this bias arrangement comprises:

In these grid row, apply most grid bias conditions to those grids, wherein those grid bias conditions are included in should select on the grid in these grid row and read voltage with respect to one of this substrate bias condition, this reads the threshold voltage that voltage is higher than low threshold voltage state, and those grid bias conditions are included in the counter-rotating bias voltage on other grids in this grid row, this reversal voltage enough reduces the counter-rotating in this multiple grid channel region, wherein this multiple grid channel region is positioned at those other grid belows, and this reversal voltage is higher than the threshold voltage of high threshold voltage state.

25, the method for operation of integrated circuit memory element according to claim 24 is characterized in that it more comprises to apply a bias arrangement to wipe, and this bias arrangement comprises:

In these grid row, apply most grid bias conditions to those grids, wherein those grid bias conditions comprise most voltages, those voltages cause that enough electronics injects those charge-trapping zones, to set up high threshold voltage state, wherein those charge-trapping zones be arranged in this grid row those grids one of them or more under.