CN100570551C - 用于降低流水线处理器中缓冲容量的方法 - Google Patents

用于降低流水线处理器中缓冲容量的方法 Download PDF

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Publication number
CN100570551C
CN100570551C CNB2005800445729A CN200580044572A CN100570551C CN 100570551 C CN100570551 C CN 100570551C CN B2005800445729 A CNB2005800445729 A CN B2005800445729A CN 200580044572 A CN200580044572 A CN 200580044572A CN 100570551 C CN100570551 C CN 100570551C
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packet
cost information
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CN101088065A (zh
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汤玛斯·柏顿
贾克柏·卡斯崔姆
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A Strategic Position Lelateniuke Co
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Xelerated AB
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CNB2005800445729A 2004-12-22 2005-12-20 用于降低流水线处理器中缓冲容量的方法 Expired - Fee Related CN100570551C (zh)

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SE0403128A SE0403128D0 (sv) 2004-12-22 2004-12-22 A method for a processor, and a processor
SE04031282 2004-12-22
US60/643,580 2005-01-14

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CN101088065A CN101088065A (zh) 2007-12-12
CN100570551C true CN100570551C (zh) 2009-12-16

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TW (1) TWI394078B (sv)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3151111B1 (en) * 2014-06-30 2018-10-17 Huawei Technologies Co., Ltd. Data processing method executed by network apparatus, and associated device
CN108628277B (zh) * 2018-08-16 2020-07-24 珠海格力智能装备有限公司 工作站的分配处理方法及装置、系统

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN85107692A (zh) * 1985-10-19 1987-05-06 霍尼韦尔信息系统公司 多处理机公用的流水线超高速缓冲存储器
CN1232219A (zh) * 1998-03-23 1999-10-20 日本电气株式会社 流水线型多处理器系统
WO2002027483A2 (en) * 2000-09-29 2002-04-04 Intel Corporation Trace buffer for loop compression
US6757249B1 (en) * 1999-10-14 2004-06-29 Nokia Inc. Method and apparatus for output rate regulation and control associated with a packet pipeline

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1236097A4 (en) * 1999-09-01 2006-08-02 Intel Corp BRANCH COMMAND TO THE PROCESSOR
KR100800958B1 (ko) * 2001-10-04 2008-02-04 주식회사 케이티 토큰 버켓을 이용한 트래픽 플로우 제어 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN85107692A (zh) * 1985-10-19 1987-05-06 霍尼韦尔信息系统公司 多处理机公用的流水线超高速缓冲存储器
CN1232219A (zh) * 1998-03-23 1999-10-20 日本电气株式会社 流水线型多处理器系统
US6757249B1 (en) * 1999-10-14 2004-06-29 Nokia Inc. Method and apparatus for output rate regulation and control associated with a packet pipeline
WO2002027483A2 (en) * 2000-09-29 2002-04-04 Intel Corporation Trace buffer for loop compression

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SE0403128D0 (sv) 2004-12-22
TW200632741A (en) 2006-09-16
TWI394078B (zh) 2013-04-21
CN101088065A (zh) 2007-12-12

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Effective date of registration: 20120401

Address after: Stockholm, Sweden

Patentee after: A strategic position Lelateniuke company

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Patentee before: Xelerated AB

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091216

Termination date: 20191220