CN100562981C - Semiconductor chip and manufacture method thereof and semiconductor device - Google Patents
Semiconductor chip and manufacture method thereof and semiconductor device Download PDFInfo
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- CN100562981C CN100562981C CNB2006800302109A CN200680030210A CN100562981C CN 100562981 C CN100562981 C CN 100562981C CN B2006800302109 A CNB2006800302109 A CN B2006800302109A CN 200680030210 A CN200680030210 A CN 200680030210A CN 100562981 C CN100562981 C CN 100562981C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Provide a kind of and can judge correctly that whether semiconductor chip is with respect to the semiconductor device of solid unit's joined in parallel such as other semiconductor chips and semiconductor chip and the manufacture method thereof that is used for this device, semiconductor chip comprises: the function projection, it is outstanding from the surface of semiconductor chip with first overhang, is used for being electrically connected with the solid unit; Connect and confirm to use projection, it is outstanding from the surface of semiconductor chip with second overhang less than first overhang, is used to confirm the status of electrically connecting of function projection.
Description
Technical field
The present invention relates to the manufacture method that chip laminate (chip-on-chip) structure and flip-chip weld the semiconductor device of (flip-chip-bonding) structure and be applicable to semiconductor chip and this semiconductor chip of this semiconductor device.
Background technology
As being used to realize the miniaturization of semiconductor device and highly integrated structure, for example, the known chip laminate structure that has the surface that makes semiconductor chip to engage with other semiconductor chip surperficial relative.
In the semiconductor device of chip laminate structure, be provided with a plurality of function projections (bump) on the surface of each semiconductor chip and connect and confirm to use projection.For example, on the surface of each semiconductor chip, portion's assortment has cancellate a plurality of function projection in the central, disposes in four bights to connect and confirms to use projection.
In each semiconductor chip, the function projection is to utilize copper metal materials such as (Cu) all to form uniform height (from the outstanding overhang in the surface of semiconductor chip).In addition, the leading section in each function projection of a side semiconductor chip is formed with the solder bonds material that can carry out alloying with the material of function projection.Via this solder bonds material, each function projection of a semiconductor chip and each function projection of another semiconductor chip are coupled together, thus, realize the electrical and mechanical connection between the semiconductor chip.
On the other hand, in each semiconductor chip, connect and confirm with projection it is to utilize the metal material identical, form the height identical (from the outstanding overhang in the surface of semiconductor chip) with the function projection with the function projection.In addition, confirm to be formed with the solder bonds material in each connection of a semiconductor chip with the leading section of projection.Thus, under two semiconductor chips were parallel to each other situation about engaging, each of a semiconductor chip connects confirmed that being connected affirmation with each of projection and another semiconductor chip uses projection to connect through the solder bonds material.Therefore, connect to confirm with the jockey between projections, can judge the two semiconductor chips joint that whether is parallel to each other by adjusting these.That is, if whole connections confirm with the good connection between projection, then can judge the two semiconductor chips joint that is parallel to each other.On the other hand, if, then can be judged to be two semiconductor chips joints (semiconductor chip with respect to another semiconductor chip tilt joint) that be not parallel to each other even there is one connect to confirm with the connection status of projection badly.
Patent documentation 1: Japanese kokai publication hei 8-153747 communique
But, in existing structure, even under the state that a semiconductor chip more or less tilts with respect to another semiconductor chip, engage, connect to confirm that the connected unfavorable conditions of usefulness projections are confirmed in the whole connections that produce two semiconductor chips thus with the fusion and expanding when the heat treatment of the solder bonds material of the leading section of projection.At this moment, though semiconductor chip tilts to engage with respect to another semiconductor chip, but still be judged as the two semiconductor chips joint that is parallel to each other.
Summary of the invention
Therefore, the purpose of this invention is to provide and a kind ofly can judge correctly that whether semiconductor chip is with respect to the semiconductor device of solid unit's joined in parallel such as other semiconductor chips and semiconductor chip and the manufacture method thereof that is used for this device.
Being used to reach the semiconductor chip of the present invention of described purpose, is the semiconductor chip that is engaged in the solid unit under the state relative with the solid unit of its surface making, and it comprises: semiconductor substrate; Surface protection film, it covers the surface of described semiconductor substrate; Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film; The function projection, it is arranged on the described electrode pad, connects described bonding pad opening, and outstanding with first overhang on described surface protection film, is used for being electrically connected with described solid unit; The interlayer film, this interlayer film disposes described electrode pad in its surface between described semiconductor substrate and described surface protection film; And connection confirms to use projection; it is from the surface elevation of described interlayer film; perforation connects the through hole that forms at described surface protection film, and is outstanding with second overhang less than described first overhang on described surface protection film, is used to confirm the status of electrically connecting of described function projection.
In this structure, owing to connect to confirm to form to such an extent that be lower than the function projection with projection, so even the surface of semiconductor chip tilts slightly with respect to the solid unit, the wide part in interval on the surface of solid unit and semiconductor chip, the solid unit be connected the part confirming the to connect pad or the projection of solid unit's surface configuration (for example) and be connected affirmation and also can produce wide gap between with the leading section of projection with projection.Therefore, when connect confirming to be connected affirmation and to be engaged by being formed on the grafting material on the projection with projection and solid unit, even grafting material expands, this grafting material can not reach the solid unit yet, can not realize connecting and confirm to use being connected of projection and solid unit.Therefore, according to connecting the connection status of confirming with projection and solid unit, can judge correctly whether semiconductor chip engages abreast with respect to the solid unit.
Being used to reach the semiconductor chip of the present invention of described purpose, is the semiconductor chip that is engaged in the solid unit under the state relative with the solid unit of its surface making, and it comprises: semiconductor substrate; Surface protection film, it covers the surface of described semiconductor substrate; Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film; The function projection, it is arranged on the described electrode pad, connects described bonding pad opening, and is outstanding with first overhang on described surface protection film, is used for being electrically connected with described solid unit; And connection confirms to use projection; it is from the surface elevation of described semiconductor substrate; perforation connects the through hole that forms at described surface protection film, and is outstanding with second overhang less than described first overhang on described surface protection film, is used to confirm the status of electrically connecting of described function projection.
The semiconductor chip of this structure can be made by the method that comprises following operation, that is: in the operation of film between cambium layer on the semiconductor substrate; On the interlayer film, form the operation of electrode pad; Form the operation of surface protection film on the surface of semiconductor substrate; Form the operation of through hole on described surface protection film, wherein this through hole connects bonding pad opening and the described surface protection film that described electrode pad is exposed, and described interlayer film is exposed; And form the function projection that connects described bonding pad opening and connect the operation of the connection affirmation of described through hole with projection
Also can also comprise the interlayer film, this interlayer film disposes described electrode pad in its surface between described semiconductor substrate and described surface protection film, and described connection is confirmed with the surface elevation of projection from described interlayer film.
In addition, described connection affirmation also can be from the surface elevation of described semiconductor substrate with projection.
Be used to reach the semiconductor device of the present invention of described purpose, be to have the chip laminate structure, under the state of the surface that makes second semiconductor chip in the face of the surface of first semiconductor chip, engage the semiconductor device of described first semiconductor chip and described second semiconductor chip, described first semiconductor chip comprises: the first semiconductor chip side function projection, and its surface from described first semiconductor chip is outstanding; And first semiconductor chip side connect to confirm use projection, give prominence on its surface from described first semiconductor chip; Described second semiconductor chip comprises: semiconductor substrate; Surface protection film, it covers the surface of described semiconductor substrate; Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film; The second semiconductor chip side function projection, it is arranged on the described electrode pad, connect described bonding pad opening, and it is outstanding with first overhang on described surface protection film, and be connected in the described first semiconductor chip side function projection, be used to realize the electrical connection of described first semiconductor chip and described second semiconductor chip; The interlayer film, this interlayer film disposes described electrode pad in its surface between described semiconductor substrate and described surface protection film; And second semiconductor chip side connect to confirm to use projection; it is from the surface elevation of described interlayer film; perforation connects the through hole that forms at described surface protection film; and it is outstanding with second overhang on described surface protection film less than described first overhang; and be connected with described first semiconductor chip side and confirm to connect with projection, be used to confirm the state of the electrical connection of described first semiconductor chip and described second semiconductor chip.
In this structure, because second semiconductor chip side connect to be confirmed to form to such an extent that be lower than the second semiconductor chip side function projection with projection, so even the surface of second semiconductor chip tilts slightly with respect to the surface of first semiconductor chip, the wide part in interval on the surface of the surface of first semiconductor chip and second semiconductor chip connects in the first relative mutually semiconductor chip side and to confirm to connect with the projection and second semiconductor chip side affirmation and also can produce wide gap between with projection.Therefore, when these connection affirmations are engaged with the grafting material on the projection by the connection affirmation that is formed on a side with projection, even grafting material expands, this grafting material also can not reach the opposing party's connection to be confirmed to use projection, can not realize that first semiconductor chip side connects affirmation and connects the connection of confirming with between the projection with the projection and second semiconductor chip side.Therefore, connection is confirmed to connect the connection status of confirming to use between the projection with the projection and second semiconductor chip side according to first semiconductor chip side, can judge correctly whether second semiconductor chip engages abreast with respect to first semiconductor chip.
Be used to reach the semiconductor device of the present invention of described purpose, be to have the chip laminate structure, under the state of the surface that makes second semiconductor chip in the face of the surface of first semiconductor chip, engage the semiconductor device of described first semiconductor chip and described second semiconductor chip, wherein, described first semiconductor chip comprises: the first semiconductor chip side function projection, and its surface from described first semiconductor chip is outstanding; And first semiconductor chip side connect to confirm use projection, give prominence on its surface from described first semiconductor chip; Described second semiconductor chip comprises: semiconductor substrate; Surface protection film, it covers the surface of described semiconductor substrate; Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film; The second semiconductor chip side function projection, it is arranged on the described electrode pad, connect described bonding pad opening, and it is outstanding with first overhang on described surface protection film, and be connected in the described first semiconductor chip side function projection, be used to realize the electrical connection of described first semiconductor chip and described second semiconductor chip; And second semiconductor chip side connect to confirm to use projection; it is from the surface elevation of described semiconductor substrate; perforation connects the through hole that forms at described surface protection film; and it is outstanding with second overhang on described surface protection film less than described first overhang; and be connected with described first semiconductor chip side and confirm to connect with projection, be used to confirm the state of the electrical connection of described first semiconductor chip and described second semiconductor chip.
The described first semiconductor chip side function projection, the described second semiconductor chip side function projection, described first semiconductor chip side connect confirms that connecting affirmation with projection, described second semiconductor chip side can adopt identical metal material to form with projection.And described semiconductor device also can also comprise the connection metal level, this connects metal level and confirms to confirm that with projection and the connection of described second semiconductor chip side described connection metal level is used to realize being connected between the each part mentioned above with described metallic material alloyization with between the projection between connecting between described first semiconductor chip side function projection and the described second semiconductor chip side function projection and between described first semiconductor chip side respectively.
For example, the described first semiconductor chip side function projection, the described second semiconductor chip side function projection, the connection of described first semiconductor chip side confirm that connecting affirmation with projection and described second semiconductor chip side can adopt copper or gold formation with projection.At this moment, described connection metal level also can be arranged at the described first semiconductor chip side function projection and the connection of described first semiconductor chip side confirms to use projection and/or the described second semiconductor chip side function projection and described second semiconductor chip side to connect the end face of confirming to use projection, forms by the solder bonds material.
The shape of described second semiconductor chip when vertically overlooking its surface is approximate rectangular, the described second semiconductor chip side function projection is configured in the central portion on the surface of described second semiconductor chip, and described second semiconductor chip side connects each bight of confirming to be configured in projection the surface of described second semiconductor chip.
According to this structure, dispose second semiconductor chip side in each bight on the surface of second semiconductor chip and connect and confirm to use projection.Therefore, if the surface of second semiconductor chip with respect to the surface tilt of first semiconductor chip, then at least one group first semiconductor chip side connect to be confirmed to connect with the projection and second semiconductor chip side and is confirmed with producing wide gap between the projection.Therefore, connect affirmation according to second semiconductor chip side and be connected the connection status of confirming with projection with second semiconductor chip side, can judge more correctly whether second semiconductor chip engages abreast with respect to first semiconductor chip with projection.
Described second semiconductor chip side connects to be confirmed to form to such an extent that be lower than the described second semiconductor chip side function projection with projection, and described first semiconductor chip side connects and confirms to form to such an extent that be lower than the described first semiconductor chip side function projection and also can with projection.That is, described first semiconductor chip side connects to be confirmed with the overhang little overhang of projection to give prominence to than the surface from described first semiconductor chip of the described first semiconductor chip side function projection, gives prominence to from the surface of described first semiconductor chip and also can.
Above-mentioned or other purpose of the present invention, feature and effect can be clearer and more definite from the explanation of the execution mode of with reference to the accompanying drawings following narration.
Description of drawings
Fig. 1 is the diagram sectional view of structure of the semiconductor device of expression an embodiment of the invention;
Fig. 2 is the diagram sectional view of the structure of the sub-chip of expression;
Fig. 3 is the coupling part of the function projection between mother chip and the sub-chip and connects the diagram sectional view of confirming with the coupling part of projection, state when being the end face of the solder bonds material of leading section of the function projection of the sub-chip of the expression function projection that is contacted with mother chip (a), the state when (b) joint of expression mother chip and sub-chip is finished;
Fig. 4 is a diagram sectional view of representing the manufacturing process of sub-chip by process sequence;
Fig. 5 is the diagram sectional view of other structures (connect and confirm with the structure of projection from the surface elevation of semiconductor substrate) of the sub-chip of expression;
Fig. 6 is the diagram sectional view that is used for illustrating variation of the present invention (connect confirm also to form to such an extent that be lower than the sample attitude of function projection with projection at mother chip), state when (a) the solder bonds material of leading section of the function projection of the sub-chip of expression is contacted with the end face of function projection of mother chip, the state when (b) joint of expression mother chip and sub-chip finishes;
Fig. 7 is the vertical view diagram of connect confirming with the structure of projection when the internal circuit of mother chip and sub-chip is electrically cut off.
Embodiment
Below, describe embodiments of the present invention with reference to the accompanying drawings in detail.
Fig. 1 is the diagram sectional view of structure of the semiconductor device of expression an embodiment of the invention.
This semiconductor device has to make as solid unit's mother chip 1 with as the sub-chip 2 of semiconductor chip and overlaps the chip laminate structure that engages.
Under the state of mother chip 1 and sub-chip 2 joints, the function projection 6 of mother chip 1 and connect to confirm with the function projection 12 of projection 7 and corresponding with them respectively sub-chip 2 and is connected to confirm to use projection 13, reciprocally make end face involutory relatively, across being connected between the connection metal level 14 between them.Thus, mother chip 1 and sub-chip 2 are electrically connected across function projection 6,12, and are mechanically connected under the state that keeps predetermined distance each other.In addition, mother chip 1 and sub-chip 2 are with guide bracket 4 and sealing wire 9 sealed resin 15 sealings.The part of the guide portion 10 of guide bracket 4 is exposed from sealing resin 15, and (exterior guiding portion) works as external connecting.
Fig. 2 is the diagram sectional view of the structure of the sub-chip 2 of expression.
On surface protection film 25, be formed with bonding pad opening 26 in the position relative with electrode pad 24, electrode pad 24 exposes from surface protection film 25 through this bonding pad opening 26.In addition, on surface protection film 25, be formed with through hole 27 at its circumference, this through hole 27 with the direction of surface 11 quadratures of surface protection film 25 on connect surface protection film 25.
And function projection 12 is arranged on the electrode pad 24, connects bonding pad opening 26, and the overhang (for example 20 μ m) with regulation on surface protection film 25 is outstanding.In addition, connect to confirm with projection 13 to connect through hole 27 from surface elevation in the face of the interlayer dielectric 23 of through hole 27, outstanding with overhang (for example 18 μ m) on surface protection film 25 less than the overhang of function projection 12.That is, be benchmark with the surface 11 of surface protection film 25, connect and confirm to form than function projection 12 low 1～5 μ m (preferably hanging down 1～2 μ m) with projection 13.
And in the present embodiment, function projection 6,12 and connection are confirmed all to adopt same metal materials (for example copper or gold) formation with projection 7,13.In addition, in mother chip 1, function projection 6 and connection are confirmed all to form identical height (overhang of giving prominence to from the surface 3 of mother chip 1) with projection 7.
Fig. 3 is the coupling part of presentation function projection 6,12 and connects the diagram sectional view of confirming with the coupling part of projection 7,13.
Shown in Fig. 3 (a), under the state before the joint of mother chip 1 and sub-chip 2, confirm to be formed with solder bonds material 16 with the leading section of projection 13 in the function projection 12 and the connection of sub-chip 2.
Because function projection 12 and the difference in height that is connected affirmation usefulness projection 13, in the process that engages mother chip 1 and sub-chip 2, be contacted with moment of end face of the function projection 6 of mother chip 1 at the solder bonds material 16 of the leading section of function projection 12, produce clearance D with being connected between the end face of affirmation with projection 7 of mother chip 1 connecting the solder bonds material of confirming with the leading section of projection 13 16.
If the surface 11 of the surface 3 of mother chip 1 and sub-chip 2 is parallel to each other, then whole connection confirm with the solder bonds material 16 of the leading section of projection 13 with is connected the clearance D of confirming with between the end face of projection 7, become with function projection 12 be connected affirmation and use the suitable interval of difference in height of projection 13.Therefore,, then connect affirmation and expand, utilize this solder bonds material 16 to connect whole connections and confirm with between the projection 7,13 with solder bonds material 16 fusions of the leading section of projection 13 if heat-treat afterwards.Then, shown in Fig. 3 (b), between each mutually relative function projection 6,12 and each connect and confirm to become connection metal level 14, the good connection (conducting) of reaching them between each with the solder bonds material 16 between the projection 7,13.
On the other hand, tilt as surface 3, the surface 11 of fruit chip 2 with respect to mother chip 1, then produce the wide part and the narrow at interval part in interval on the surface 11 of the surface 3 of mother chip 1 and sub-chip 2, connect confirm with the solder bonds material 16 of the leading section of projection 13 with is connected the clearance D generation width of confirming to use between the end face of projection 7.And, the wide part in interval on the surface 11 of the surface 3 of mother chip 1 and sub-chip 2, connect confirm with the solder bonds material 16 of the leading section of projection 13 with is connected the interval of confirming with the clearance D between the end face of projection 7 become than function projection 12 be connected affirmation and use the difference in height of projection 13 also wide.Therefore, if the amount of solder bonds material 16 is suitable a certain amount of, then in the wide part in interval on the surface 11 of the surface 3 of mother chip 1 and sub-chip 2, even connect solder bonds material 16 expansions of confirming with the leading section of projection 13 during heat treatment, this solder bonds material 16 can not arrive yet and connect the end face of confirming with projection 7, can not realize connecting the connection of confirming with between the projection 7,13.
Therefore, if reaching whole connections confirms with the connection between the projection 7,13, then can be judged to be sub-chip 2 engages abreast with respect to mother chip 1, if the connection of not reaching arbitrary group is confirmed then can be judged to be sub-chip 2 and engage (not having joined in parallel) obliquely with respect to mother chip 1 with the connection of 7,13 of projections.
Same with existing structure, when the connection of mother chip 1 confirms to form being connected affirmation and forming the height identical with function projection 12 with projection 13 of the height identical with function projection 6, sub-chip 2 with projection 7, even sub-chip 2 tilts to engage with respect to mother chip 1, the wide part in interval on the surface 11 of the surface 3 of mother chip 1 and sub-chip 2 is confirmed with the solder bonds material 16 of the leading section of projection 13 with to be connected the gap that produces between the end face of affirmation with projection 7 very little connecting.Therefore, if 16 melting expansions of solder bonds material, this solder bonds material 16 reaches and connects the end face of confirming with projection 7, realizes connecting the connection of confirming with between the projection 7,13.
With respect to this, in the present embodiment, because the connection of sub-chip 2 affirmation forms with projection 13 and is lower than function projection 12, so even there is slightly inclination on the surface 11 of sub-chip 2 with respect to the surface 3 of mother chip 1, the wide part in interval between the surface 11 of the surface 3 of mother chip 1 and sub-chip 2 then, connect confirm with the solder bonds material 16 of the leading section of projection 13 be connected affirmation and also can produce wide gap between with the end face of projection 7.Therefore, even solder bonds material 16 expands, this solder bonds material 16 can not reach yet and connect the end face of confirming with projection 7, can not realize connecting the connection of confirming with between the projection 7,13 yet.Therefore, can judge correctly that sub-chip 2 is with respect to mother chip 1 joined in parallel whether.
Fig. 4 is a diagram sectional view of representing the manufacturing process of sub-chip 2 by process sequence.
At first, shown in Fig. 4 (a), on the semiconductor substrate 21 that has formed wiring layer 22, interlayer dielectric 23 and electrode pad 24 whole for example forms surface protection film 25 by piling up silicon nitride or silica.Silicon nitride or silica can be piled up by the CVD method.
Then, shown in Fig. 4 (b), on surface protection film 25, connect formation bonding pad opening 26 and through hole 27 by photo-mask process.
Afterwards, shown in Fig. 4 (c),, form function projection 12 and connect and confirm with projection 13 by selecting plating method deposit material in bonding pad opening 26 and through hole 27.Because the height and position of the bottom surface (surface of electrode pad 24) of bonding pad opening 26 and the bottom surface (surface of interlayer dielectric 23) of through hole 27 is different; so confirm with projection 13 with being connected by in same operation, forming function projection 12; thereby do not need special operation, can access function projection 12 and the connection different mutually and confirm with projection 13 with respect to the height (overhang) on the surface of surface protection film 25.
And, being not limited to this, function projection 12 and connection are confirmed also can form in different operations respectively with projection 13.That is, also can form function projection 12 earlier and connect a side who confirms with projection 13, then form the opposing party again.
Fig. 5 is the diagram sectional view of other structures of the sub-chip 2 of expression.In this Fig. 5, part mark with Fig. 2 identical reference symbol suitable with each several part shown in Figure 2 represented.In addition, below, the difference of only enumerating with the sub-chip 2 of structure shown in Figure 2 describes, and omits the detailed explanation of each several part.
In this sub-chip 2 shown in Figure 5, perforation is formed with the intercommunicating pore 28 that is communicated with the through hole 27 of surface protection film 25 on interlayer dielectric 23.And, connect to confirm to connect through hole 27 with the surface elevation of projection 13 from semiconductor substrate 21, outstanding with overhang (for example, 15 μ m) on surface protection film 25 less than the overhang of function projection 12.
By this structure, also can realize the effect same with the situation of structure shown in Figure 2.
More than, an embodiment of the invention have been described, but the present invention can implement also otherwise.For example, in the above-described embodiment, on sub-chip 2, connect to confirm to form to such an extent that be lower than function projection 12, but as shown in Figure 6, even on mother chip 1, also can form to such an extent that be lower than function projection 6 with projection 7 with connecting affirmation with projection 13.At this moment, shown in Fig. 6 (a), connect and confirm to need only the height that forms respectively as follows with projection 7,13, that is: in the process that engages mother chip 1 and sub-chip 2, be contacted with moment of end face of the function projection 6 of mother chip 1 at the solder bonds material 16 of the leading section of function projection 12, connecting the clearance D of confirming with solder bonds material 16 with the mother chip 1 of the leading section of projection 13 that produces 1～5 μ m (preferred 1～2 μ m) between the end face of affirmation with projection 7 that is connected.Form if so, then shown in Fig. 6 (b), as long as the surface 3 of mother chip 1 and the surface 11 of sub-chip 2 are parallel to each other, between each mutually relative function projection 6,12 and each connect and confirm to become connection metal level 14, the good connection that can realize them between each with the solder bonds material 16 between the projection 7,13.
In addition, on sub-chip 2, function projection 12 is confirmed to form identical height with projection 13 with being connected, and on mother chip 1, connects affirmation and forms with projection 7 and be lower than function projection 6 and also can.That is, in this embodiment, though with mother chip 1 and sub-chip 2 respectively as first semiconductor chip and second semiconductor chip, also can be with mother chip 1 as second semiconductor chip, with sub-chip 2 as first semiconductor chip.
And then in addition, connect and confirm to be connected with the internal circuit of mother chip 1 and sub-chip 2 respectively with projection 7,13, also can be respectively electrically disconnect with the internal circuit of mother chip 1 and sub-chip 2, connecting under the situation about confirming with projection 7,13 circuit disconnection internally, as shown in Figure 7, on mother chip 1, confirm with projection 7 in the connection of two one group of each bight in chip join zone configuration, and is connected with each in the overseas setting of chip bonding area and confirms the outside taking-up electrode 17 that is electrically connected with projection 7.On the other hand, on sub-chip 2, confirm with projection 13 in the connection of two one group of each bight configuration, and this connection of two one group is confirmed to be electrically connected mutually with projection 13.Thus, engage if mother chip 1 and sub-chip 2 are abreast, then the connection of each group is confirmed with being connected between the projection 7,13, and the outside of each group is taken out with short circuit between the electrode 17, therefore, and the resistance decreasing between them.On the other hand, be engaged obliquely with respect to mother chip 1 as fruit chip 2, then the wide part in the interval between their surface does not realize connecting the connection of confirming with projection 7,13, can't obtain outside the taking-up, so the resistance between them becomes big with conducting between the electrode 17.Therefore, take out the measurement result of using the resistance between the electrode 17, can judge correctly whether sub-chip 2 engages abreast with respect to mother chip 1 according to the outside of each group.
In addition, though example has gone out the semiconductor device of chip laminate structure, the present invention can also be applicable to the semiconductor device that makes semiconductor chip surface regard to the flip-chip welding structure that wiring substrate (solid unit) engages.
Can implement the change in the various designs in the scope of the item of in claims, putting down in writing in addition.That is, the object lesson that described execution mode only adopts in order to offer some clarification on technology contents of the present invention, and should not be construed as the present invention and be defined in these object lessons, spirit of the present invention and scope are only limited by additional claims.
The application is willing to 2005-241520 number corresponding to the spy who proposed to Japan Patent office on August 23rd, 2005 and the spy is willing to that the disclosure of these applications is quoted and is combined in this 2005-241521 number.
Claims (11)
1. semiconductor chip is engaged in the solid unit making under the state relative with the solid unit of its surface, and it comprises:
Semiconductor substrate;
Surface protection film, it covers the surface of described semiconductor substrate;
Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film;
The function projection, it is arranged on the described electrode pad, connects described bonding pad opening, and outstanding with first overhang on described surface protection film, is used for being electrically connected with described solid unit;
The interlayer film, this interlayer film disposes described electrode pad in its surface between described semiconductor substrate and described surface protection film; And
Connect and confirm to use projection; it is from the surface elevation of described interlayer film; perforation connects the through hole that forms at described surface protection film, and is outstanding with second overhang less than described first overhang on described surface protection film, is used to confirm the status of electrically connecting of described function projection.
2. semiconductor chip is engaged in the solid unit making under the state relative with the solid unit of its surface, and it comprises:
Semiconductor substrate;
Surface protection film, it covers the surface of described semiconductor substrate;
Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film;
The function projection, it is arranged on the described electrode pad, connects described bonding pad opening, and is outstanding with first overhang on described surface protection film, is used for being electrically connected with described solid unit; And
Connect and confirm to use projection; described connection is confirmed with the surface elevation of projection from described semiconductor substrate; perforation connects the through hole that forms at described surface protection film; on described surface protection film, give prominence to, be used to confirm the status of electrically connecting of described function projection with second overhang less than described first overhang.
3. semiconductor chip as claimed in claim 1 or 2,
Described connection is confirmed to electrically disconnect with the internal circuit of projection and described semiconductor chip.
4. method of making semiconductor chip, this semiconductor chip are engaged in the solid unit making under the state relative with the solid unit of its surface,
Comprise:
In the operation of film between cambium layer on the semiconductor substrate;
On the interlayer film, form the operation of electrode pad;
Form the operation of surface protection film on the surface of semiconductor substrate;
Form the operation of through hole on described surface protection film, wherein this through hole connects bonding pad opening and the described surface protection film that described electrode pad is exposed, and described interlayer film is exposed; And
Form the function projection that connects described bonding pad opening and connect the operation of the connection affirmation of described through hole with projection.
5. semiconductor device, it has the chip laminate structure, under the state of the surface that makes second semiconductor chip in the face of the surface of first semiconductor chip, engages described first semiconductor chip and described second semiconductor chip, wherein,
Described first semiconductor chip comprises:
The first semiconductor chip side function projection, its surface from described first semiconductor chip is outstanding; And
First semiconductor chip side connects confirms to use projection, and its surface from described first semiconductor chip is outstanding;
Described second semiconductor chip comprises:
Semiconductor substrate;
Surface protection film, it covers the surface of described semiconductor substrate;
Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film;
The second semiconductor chip side function projection, it is arranged on the described electrode pad, connect described bonding pad opening, and it is outstanding with first overhang on described surface protection film, and be connected in the described first semiconductor chip side function projection, be used to realize the electrical connection of described first semiconductor chip and described second semiconductor chip;
The interlayer film, this interlayer film disposes described electrode pad in its surface between described semiconductor substrate and described surface protection film; And
Second semiconductor chip side connects confirms to use projection; it is from the surface elevation of described interlayer film; perforation connects the through hole that forms at described surface protection film; and it is outstanding with second overhang on described surface protection film less than described first overhang; and be connected with described first semiconductor chip side and confirm to connect with projection, be used to confirm the state of the electrical connection of described first semiconductor chip and described second semiconductor chip.
6. semiconductor device, it has the chip laminate structure, under the state of the surface that makes second semiconductor chip in the face of the surface of first semiconductor chip, engages described first semiconductor chip and described second semiconductor chip, wherein,
Described first semiconductor chip comprises:
The first semiconductor chip side function projection, its surface from described first semiconductor chip is outstanding; And
First semiconductor chip side connects confirms to use projection, and its surface from described first semiconductor chip is outstanding;
Described second semiconductor chip comprises:
Semiconductor substrate;
Surface protection film, it covers the surface of described semiconductor substrate;
Electrode pad, it is configured to the bonding pad opening in the face of forming on described surface protection film between described semiconductor substrate and described surface protection film;
The second semiconductor chip side function projection, it is arranged on the described electrode pad, connect described bonding pad opening, and it is outstanding with first overhang on described surface protection film, and be connected in the described first semiconductor chip side function projection, be used to realize the electrical connection of described first semiconductor chip and described second semiconductor chip; And
Second semiconductor chip side connects confirms to use projection; it is from the surface elevation of described semiconductor substrate; perforation connects the through hole that forms at described surface protection film; and it is outstanding with second overhang on described surface protection film less than described first overhang; and be connected with described first semiconductor chip side and confirm to connect with projection, be used to confirm the state of the electrical connection of described first semiconductor chip and described second semiconductor chip.
7. as claim 5 or 6 described semiconductor devices, wherein,
The described first semiconductor chip side function projection, the described second semiconductor chip side function projection, described first semiconductor chip side connect confirms that connecting affirmation with projection, described second semiconductor chip side adopts identical metal material to form with projection,
And described semiconductor device also comprises the connection metal level, this connects metal level and confirms to confirm that with projection and the connection of described second semiconductor chip side described connection metal level is used to realize being connected between the each part mentioned above with described metallic material alloyization with between the projection between connecting between described first semiconductor chip side function projection and the described second semiconductor chip side function projection and between described first semiconductor chip side respectively.
8. as claim 5 or 6 described semiconductor devices, wherein,
The shape of described second semiconductor chip when vertically overlooking its surface is approximate rectangular,
The described second semiconductor chip side function projection is configured in the central portion on the surface of described second semiconductor chip,
Described second semiconductor chip side connects each bight of confirming to be configured in projection the surface of described second semiconductor chip.
9. as claim 5 or 6 described semiconductor devices, wherein,
Described first semiconductor chip side connects to be confirmed with the overhang little overhang of projection to give prominence to than the surface from described first semiconductor chip of the described first semiconductor chip side function projection, outstanding from the surface of described first semiconductor chip.
10. as claim 5 or 6 described semiconductor devices, wherein,
Described first semiconductor chip side connects confirms that connecting affirmation with projection and described second semiconductor chip side electrically disconnects with the internal circuit of described first semiconductor chip and described second semiconductor chip respectively with projection.
11. semiconductor device as claimed in claim 10, wherein,
Described first semiconductor chip has outside the taking-up and uses electrode, and described outside taking-up is connected with described first semiconductor chip side with electrode to be confirmed to be electrically connected with projection.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP241521/2005 | 2005-08-23 | ||
| JP241520/2005 | 2005-08-23 | ||
| JP2005241520A JP4791104B2 (en) | 2005-08-23 | 2005-08-23 | Semiconductor chip and method for manufacturing semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101243547A CN101243547A (en) | 2008-08-13 |
| CN100562981C true CN100562981C (en) | 2009-11-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006800302109A Expired - Fee Related CN100562981C (en) | 2005-08-23 | 2006-08-18 | Semiconductor chip and manufacture method thereof and semiconductor device |
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| Country | Link |
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| JP (1) | JP4791104B2 (en) |
| CN (1) | CN100562981C (en) |
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|---|---|---|---|---|
| KR100886714B1 (en) | 2007-10-10 | 2009-03-04 | 주식회사 하이닉스반도체 | Semiconductor chip |
| KR102190382B1 (en) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | Semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3325755B2 (en) * | 1995-12-27 | 2002-09-17 | 三菱電機株式会社 | Semiconductor device, method of mounting the same, and method of inspecting the mounted portion |
| JP3870067B2 (en) * | 2001-11-05 | 2007-01-17 | ローム株式会社 | Semiconductor device |
| JP3787295B2 (en) * | 2001-10-23 | 2006-06-21 | ローム株式会社 | Semiconductor device |
| JP2004228202A (en) * | 2003-01-21 | 2004-08-12 | Matsushita Electric Ind Co Ltd | Semiconductor apparatus and its manufacturing method |
-
2005
- 2005-08-23 JP JP2005241520A patent/JP4791104B2/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| JP4791104B2 (en) | 2011-10-12 |
| JP2007059547A (en) | 2007-03-08 |
| CN101243547A (en) | 2008-08-13 |
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