CN100562111C - Discrete cosine inverse transformation method and device thereof - Google Patents
Discrete cosine inverse transformation method and device thereof Download PDFInfo
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- CN100562111C CN100562111C CN 200610090250 CN200610090250A CN100562111C CN 100562111 C CN100562111 C CN 100562111C CN 200610090250 CN200610090250 CN 200610090250 CN 200610090250 A CN200610090250 A CN 200610090250A CN 100562111 C CN100562111 C CN 100562111C
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Abstract
The invention discloses a kind of discrete cosine inverse transformation method, be included in the transformation coefficient block in the image encoding is carried out in the inverse discrete cosine transform processing procedure based on the AAN algorithm, respectively each conversion coefficient in the transformation coefficient block of initial input is amplified to revise and round processing; Revise the conversion process that rounds processing for each conversion coefficient through amplifying, based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process; Each final inverse discrete cosine transform result data is carried out the corresponding processing of dwindling respectively.The invention also discloses a kind of inverse discrete cosine transform device accordingly.The present invention can further accelerate the idct transform processing speed based on the AAN algorithm, better meets the demand of modern real time communication business.
Description
Technical field
The present invention relates to the discrete cosine transform (DCT of communication technical field, Discrete CosineTransform) technology and inverse discrete cosine transform (IDCT, Inverse Discrete Cosine Transform) technology especially relates to a kind of discrete cosine inverse transformation method and device thereof.
Background technology
Since Ahmed and Rao have proposed discrete cosine transform (DCT in 1974, Discrete CosineTransform) since the definition, discrete cosine transform and inverse discrete cosine transform (IDCT, Inverse DiscreteCosine Transform) important technology of just become the signal processing that is widely used in the communications field, image processing, handling especially for compress speech and image compression encoding and decoding, so DCT technology and IDCT technology all are the research focuses of international academic community and high-tech industry circle all the time.
Because the demand of real-time communication characteristic, be used for (the JPEG of rest image panel of expert that the rest image compression coding and decoding is handled, Joint Picture Expert Group) in the standard, and be used for (the MPEG of dynamic image panel of expert that the dynamic image compression coding and decoding is handled, Motion Pictures Expert Group) all adopted DCT processing and IDCT to handle in the standard, the feasible thus research to DCT fast algorithm and IDCT fast algorithm more seems significant.
Because conventional DCT algorithm and IDCT algorithm have all been used more multiplying and add operation, and well-known multiplying is unusual consume system resources in calculating process, as to consumption of computer software and hardware resource etc., multiplying simultaneously is also more consuming time, just makes that therefore conventional DCT calculating process and IDCT calculating process show slowly slightly.The DCT fast algorithm of follow-up proposition and IDCT fast algorithm all are to reduce multiplying number of times in the calculating process and add operation number of times as main purpose, to refer in particular to the operation times that reduces multiplication for above-mentioned reasons.In recent years, various DCT fast algorithms and IDCT fast algorithm all emerge in an endless stream, but mostly are based on dish-shaped computational methods, reduce redundancy in the computational process with the periodicity that makes full use of trigonometric function, thereby reach quick computation purpose.
The AAN algorithm that has proposed to be used for dct transform and idct transform by people such as Arai in 1988 is recommended to use by the Joint Photographic Experts Group tissue.Measured AAN algorithm carries out need carrying out 13 multiplyings and 29 sub-addition computings when idct transform is handled to one dimension 8 dot image, but 8 multiplyings are wherein carried out before input signal being carried out the IDCT processing in advance synchronously, be convenient to that like this input signal is carried out unified cut position processing and sequencing control and handle, realize idct transform thereby help hardware.Based on this basis, the AAN algorithm will at first multiply by the coefficient zoom factor of correspondence respectively to the IDCT coefficient of each input signal, data after will handling are then sent into the AAN process chart and are carried out the idct transform processing, thereby obtain one dimension 8 dot image are carried out the intermediate conversion data that idct transform is handled.Help hardware and realize it being the superiority of AAN algorithm with respect to other IDCT fast algorithm.In the AAN algorithm, the multiplication preliminary treatment of coefficient zoom factor can be handled with the inverse quantization of input signal and combine, thereby can further reduce the amount of calculation of AAN algorithm simultaneously.
A kind of IDCTAAN process chart of standard as shown in Figure 1, by this figure as seen, in the AAN process chart, one dimension 8 dot image are carried out only need carrying out 5 times when idct transform is handled floating-point multiplication, and Duhamel has proved that the floating-point multiplication number of times lower limit of using general IDCT fast algorithm that one dimension 8 dot image are carried out need carrying out when IDCT handles is 11 times, and this just illustrates that the AAN algorithm has certain superiority with respect to other IDCT fast algorithm.In IDCT AAN process chart shown in Figure 1, a
1The multiplication constant term that occurs in the multiplication procedure is C
4, a
2The multiplication constant term that occurs in the multiplication procedure is C
2-C
6, a
3The multiplication constant term that occurs in the multiplication procedure is C
4, a
4The multiplication constant term that occurs in the multiplication procedure is C
2+ C
6, a
5The constant term that occurs in the multiplication procedure is C
6Coefficient zoom factor wherein
A
i=1/ (4C
i), i=1 ... 7, in this formula
The IDCT AAN process chart of another kind of standard needing too to carry out 5 times when idct transform is handled to carry out floating-point multiplication to one dimension 8 dot image as shown in Figure 2 in the AAN process chart shown in this figure.Coefficient zoom factor among the figure
As fully visible, though the AAN algorithm belongs to IDCT fast algorithm technology, but be based on the AAN algorithm one dimension 8 dot image signals are carried out idct transform when handling, still need to do cosine function value floating-point multiplication 5 times, because when the picture signal of 8 * 8 of two dimensions is carried out DCT and idct transform encoding and decoding processing, the situation that normally with the two dimensional image signal decomposition is row one peacekeeping row one dimension is handled respectively, use the AAN algorithm that one 8 * 8 two dimensional image signal is carried out just need carrying out 80 times when DCT and idct transform are handled floating-point multiplication like this, because the floating-point multiplication process is that very consumption systems is handled resource, wherein the resource of Xiao Haoing comprises to the consumption of operation time with to consumption of system hardware and software resource etc., therefore with regard to also needing the idct transform processing procedure based on the AAN algorithm is carried out further optimization process, to accelerate the conversion process speed of IDCT, better meet the demand of modern real time communication business.
Summary of the invention
The present invention proposes a kind of discrete cosine inverse transformation method and device thereof, with the idct transform processing speed of further quickening based on the AAN algorithm, better meets the demand of modern real time communication business.
For addressing the above problem, the technical scheme that the present invention proposes is as follows:
A kind of discrete cosine inverse transformation method comprises step:
In the inverse discrete cosine transform processing procedure of the transformation coefficient block in the image encoding being carried out, respectively each conversion coefficient in the transformation coefficient block of initial input is amplified correction and round processing based on the AAN algorithm;
Revise the conversion process that rounds processing for each conversion coefficient through amplifying, based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process;
Each final inverse discrete cosine transform result data based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process is carried out the corresponding processing of dwindling respectively.
Preferably, described transformation coefficient block refers to two dimension 8 * 8 dot factor matrixes in the image encoding.
Preferably, described each conversion coefficient in the transformation coefficient block of initial input is amplified to revise round processing and specifically be meant to amplify and revise the correspondence position element and second that rounds in the matrix and amplify and revise the correspondence position element that rounds in the matrix and respectively the same position coefficient element in two dimension 8 * 8 dot factor matrixes is amplified to revise and round processing based on first.
Preferably, each the coefficient element in two dimension 8 * 8 dot factor matrixes is carried out following amplification correction and rounds processing:
Block[i][j]=Block[i][j]×Coef0[i][j]+((Block[i][j]×Coef1[i][j])>>P
2);
And to the coefficient element B lock[0 in the coefficient matrix] [0] carry out following processing and amplifying:
Block[0][0]=Block[0][0]+(1<<(P
1-1));
Block[i wherein] [j] refer to the coefficient element in two dimension 8 * 8 dot factor matrixes, i, j=0,1 ..., 7; P
1And P
2Be two default amplifying parameters; Coef0 refers to that the first amplification correction rounds matrix, and Coef1 refers to that the second amplification correction rounds matrix.
Preferably, it is definite according to following processing procedure that the first amplification correction rounds Matrix C oef0:
Default one rounds corrected parameter Δ τ;
Based on Coef[i] each element in 8 * 8 floating-point parameter matrixs of [j] expression, i, j=0,1 ..., 7;
Respectively to each the Elements C oef[i in the described floating-point parameter matrix] [j] carry out following processing and amplifying:
Coef[i][j]=Coef[i][j]×(1<<P
1);
Then respectively to each the Elements C oef[i after the processing and amplifying] [j] carry out the following processing that rounds:
Coef0[i] and [j]=(int) (Coef[i] [j]+Δ τ), obtain the first amplification correction and round Matrix C oef0.
Preferably, it is definite according to following processing procedure that the second amplification correction rounds Matrix C oef1:
Default one rounds corrected parameter Δ τ;
Based on Coef[i] each element in 8 * 8 floating-point parameter matrixs of [j] expression, i, j=0,1 ..., 7;
Respectively to each the Elements C oef[i in the described floating-point parameter matrix] [j] carry out following processing and amplifying:
Coef[i][j]=Coef[i][j]×(1<<P
1);
Then respectively to each the Elements C oef[i after the processing and amplifying] [j] carry out the following processing that rounds:
Coef0[i] and [j]=(int) (Coef[i] [j]+Δ τ), obtain the first amplification correction and round Matrix C oef0;
Calculate the relevant position Elements C oef[i in the floating-point parameter matrix after the described processing and amplifying respectively] [j] and described first amplify revise the relevant position Elements C oef0[i that rounds in the matrix] difference of [j]:
Coef[i] [j]=Coef[i] [j]-Coef0[i] [j], obtain corresponding matrix of differences;
Respectively to each the Elements C oef[i in the described matrix of differences] [j] carry out following processing:
Coef1[i] [j]=(int) (Coef[i] [j] * (1<<P
2)+Δ τ), obtain the second amplification correction and round Matrix C oef1.
Preferably, each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=18, P
2=3, Δ τ=0.5;
The described first amplification correction rounds Matrix C oef0 and is:
Preferably, each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=12, P
2=3, Δ τ=0.5;
The described first amplification correction rounds Matrix C oef0 and is:
Preferably, each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=18, P
2=3, Δ τ=0.5;
The described second amplification correction rounds Matrix C oef1 and is:
Preferably, each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=12, P
2=3, Δ τ=0.5;
The described second amplification correction rounds Matrix C oef1 and is:
Preferably, the process based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process specifically comprises:
At utilizing aw based on different input value a, b in the conversion process
1+ bw
2Each varitron process of output valve is asked in computing, by with constant value w
1And w
2Dissolve and be binary form, with aw
1+ bw
2Computing is converted to
Computing, wherein m
i, n
iValue is 0 or 1 respectively, and t is a positive integer; And
Calculating is respectively changed out based on fixed point displacement accumulating operation
End value, and with the output valve of result of calculation value as the correspondent transform subprocess, wherein, the transformed value when described input value a, b are respectively the transformation coefficient block in the image encoding carried out inverse discrete cosine transform and handle; Or be the median in the inverse discrete cosine transform processing procedure; Or the image coefficient piece element value when in the compressed image decode procedure, carrying out inverse discrete cosine transform and handle.
Preferably, based on 24 shift register and the accumulator accumulating operation that is shifted of fixing a point.
Preferably, based on 32 shift register and the accumulator accumulating operation that is shifted of fixing a point.
Preferably, calculating
End value before also comprise the step of calculating different input value a, b sum a+b in advance.
Preferably, respectively to each final inverse discrete cosine transform result data Block1[i] [j], i, j=0,1 ..., 7 dwindling of execution are treated to:
Block1[i][j]=(Block1[i][j])>>P
1。
A kind of inverse discrete cosine transform device comprises:
The conversion coefficient processing unit is used in the transformation coefficient block to image encoding carries out inverse discrete cosine transform processing procedure based on the AAN algorithm, respectively each conversion coefficient in the transformation coefficient block of initial input is amplified to revise to round processing;
The displacement unit that adds up is used for each conversion coefficient amplified through the conversion coefficient processing unit and revises the conversion process that rounds after the processing, based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process;
The result data processing unit is used for add up each final inverse discrete cosine transform result data of the corresponding floating-point multiplication that the unit occurs based on fixed point displacement accumulating operation alternative transforms process of displacement is carried out the corresponding processing of dwindling respectively.
Preferably, described conversion coefficient processing unit specifically comprises:
Matrix amplifies subelement, is used for based on first amplification coefficient, and the floating-point parameter matrix to the transformation coefficient block in the image encoding carries out processing and amplifying respectively, obtains corresponding amplification floating-point parameter matrix;
First matrix is determined subelement, is used for matrix is amplified amplification floating-point parameter matrix after the subelement processing and amplifying revising and rounding processing based on rounding corrected parameter, obtains corresponding first and amplifies to revise and round matrix;
Matrix of differences is asked for subelement, and what be used for that compute matrix amplifies that amplification floating-point parameter matrix and first matrix after the subelement processing and amplifying determine that subelement obtains first amplifies and revise the difference that rounds between the matrix, obtains the matrix of differences of correspondence;
Second matrix is determined subelement, is used for based on second amplification coefficient and rounds corrected parameter matrix of differences is asked for matrix of differences that subelement obtains amplifying to revise and rounding processing, obtains corresponding second and amplifies to revise and round matrix;
Transform coefficient matrix amplifies subelement, is used for first amplifying revise that the element that rounds the matrix relevant position and second matrix determine that subelement obtains second amplify and revise the element that rounds relevant position in the matrix element of same position in the transform coefficient matrix of described initial input is carried out processing and amplifying based on what first matrix determined that subelement obtains.
Preferably, the described displacement unit that adds up specifically comprises:
The conversion subelement is used for utilizing aw at conversion process based on different input value a, b
1+ bw
2Each varitron process of output valve is asked in computing, by with constant value w
1And w
2Dissolve and be binary form, with aw
1+ bw
2Computing is converted to
Computing, wherein m
i, n
iValue is 0 or 1 respectively, and t is a positive integer;
Displacement adds up and exports the unit that bears fruit, and is used for changing out based on fixed point displacement accumulating operation calculating conversion subelement
End value, and with the output valve of result of calculation value as the correspondent transform subprocess, wherein, the transformed value when described input value a, b are respectively the transformation coefficient block in the image encoding carried out inverse discrete cosine transform and handle; Or be the median in the inverse discrete cosine transform processing procedure; Or the image coefficient piece element value when in the compressed image decode procedure, carrying out inverse discrete cosine transform and handle.
Preferably, the described displacement unit that adds up specifically also comprises input value addition subelement, is used in the described displacement output subunit computes as a result that adds up
End value before, calculate described
In different input value a, b sum a+b.
Preferably, the described displacement unit that adds up is 24 a displacement accumulation processor.
Preferably, the described displacement unit that adds up is 32 a displacement accumulation processor.
The beneficial effect that the present invention can reach is as follows:
Technical solution of the present invention is in the idct transform processing procedure of carrying out based on AAN, each conversion coefficient of initial input amplified respectively to revise round processing, and in the idct transform process, use fixed point displacement accumulating operation to substitute floating-point multiplication, thereby make and in idct transform processing procedure, avoided floating-point multiplication fully based on the AAN algorithm, and then realized guaranteeing that idct transform is as a result under the prerequisite of precision, accelerated the conversion process speed of IDCT greatly, and reduced too much consumption to the system hardware and software resource, especially when fixing a point shifting processing and fixed point accumulation process respectively based on 24 bit shift register and accumulator, chip area and energy consumption in the time of can saving hardware preferably and realize; Therefore the present invention program has better met the demand of modern real time communication business, and in like manner the technical solution of the present invention principle is equally applicable to the DCT Fast transforms processing procedure based on the AAN algorithm.
Description of drawings
Fig. 1 is a kind of IDCTAAN process chart of standard;
Fig. 2 is the IDCTAAN process chart of another kind of standard;
Fig. 3 is the main realization principle flow chart of discrete cosine inverse transformation method of the present invention;
Fig. 4 is for after using the inventive method principle, and the idct transform based on AAN among above-mentioned prior art Fig. 2 is handled and upgraded flow chart;
Fig. 5 is for after using the inventive method principle, and the idct transform based on AAN among above-mentioned prior art Fig. 1 is handled and upgraded flow chart;
Fig. 6 is the main composition structured flowchart of the inverse discrete cosine transform device of the present invention's proposition;
Fig. 7 is the concrete composition structured flowchart of conversion coefficient processing unit in apparatus of the present invention;
Fig. 8 is the add up concrete composition structured flowchart of unit of displacement in apparatus of the present invention.
Embodiment
Technical solution of the present invention is here by calculating principle analysis fast to the IDCT based on the AAN algorithm of the prior art, proposition rounds processing to amplifying based on the initial input coefficient in the idct transform process of AAN algorithm to revise, and the mode that the part that needs to do floating-point multiplication in the conversion process uses fixed point displacement and fixed point to add up handled, so that the whole quick computational process of IDCT based on AAN has been avoided floating-point multiplication, thereby realized guaranteeing that idct transform is as a result under the prerequisite of precision, accelerated the conversion rate of IDCT greatly, and reduced too much consumption to the system hardware and software resource, better met the demand of modern real time communication business with this, in like manner the technical solution of the present invention principle is equally applicable to handle based on the DCT Fast transforms of AAN algorithm.
Be explained in detail to the main realization principle of technical solution of the present invention, embodiment and to the beneficial effect that should be able to reach below in conjunction with each accompanying drawing.
Please refer to Fig. 3, this figure is the main realization principle flow chart of discrete cosine inverse transformation method of the present invention, and it realizes that mainly principle is as follows:
Step S10 in the idct transform processing procedure of digital signal being carried out based on the AAN algorithm, amplifies to revise to each conversion coefficient of initial input respectively and rounds processing; Wherein the digital signal here can refer in the image encoding each element data value of two dimension 8 * 8 coefficient block, preferably each conversion coefficient of initial input is amplified to revise to round processing and specifically can refer to amplify based on first and revise the relevant position element and second that rounds in the matrix and amplify and revise the relevant position element that rounds in the matrix and the same position coefficient element in two dimension 8 * 8 dot factor matrixes is amplified to revise round processing;
Step S20 rounds conversion process after the processing for each conversion coefficient through above-mentioned amplification correction, comes the corresponding floating-point multiplication that occurs in the alternative transforms process based on fixed point displacement accumulating operation;
Step S30 carries out the corresponding processing of dwindling respectively to each final idct transform result data at last.
Because dct transform technology and idct transform technology are widely used in digital signal processing technique field at present, particularly be applied to the digital compression technology field, since 2D-IDCT conversion can be respectively one dimension IDCT (1D-IDCT) conversion by row and column realize, so based on the following quick computational process that in execution mode, discusses the 1D-IDCT conversion of the inventive method principle.
To be applied in the inventive principle of said method of the present invention below 8 * 8 dot image signals are carried out being treated to example based on the idct transform of AAN, the specific implementation process of the inventive method will be explained in detail.
First embodiment: as shown in Figure 4, after using the inventive method principle, the idct transform based on AAN among above-mentioned prior art Fig. 2 is handled and is upgraded flow chart, here suppose in idct transform processing procedure, use 32 shift register and the accumulator accumulating operation that is shifted to handle based on AAN.
The product of (one) wherein high order end is represented to import in Fig. 48 image signal values and coefficient of correspondence zoom factor, low order end is 8 picture signal output valves finishing idct transform of output, when application the inventive method principle is carried out the processing of AAN idct transform to two dimension 8 * 8 dot image signals, at first will carry out preliminary treatment to 64 transformation matrix coefficients of two dimension 8 * 8 dot image signals, its pretreated principle process is as follows:
1. preestablishing two amplifying parameters is respectively: P
1=18 and P
2=3, and set one and round corrected parameter Δ τ=0.5;
2. suppose that each element is based on Coef[i in 8 * 8 floating-point parameter matrixs] [j] expression, i, j=0,1 ..., 7; Then the value of each element is respectively among the Matrix C oef: Coef[i] [j]=A
i* A
j, wherein
3. to each the Elements C oef[i among the above-mentioned floating-point parameter matrix Coef] [j] carry out following processing and amplifying respectively:
Coef[i][j]=Coef[i][j]×(1<<P
1)=Coef[i][j]×(1<<18);
4. then to each the Elements C oef[i after the above-mentioned processing and amplifying] [j] carry out and followingly to round processing, amplify to revise and round Matrix C oef0 thereby obtain corresponding first:
Coef0[i] [j]=(int) (Coef[i] [j]+0.5), can obtain like this amplifying and revise 8 * 8 integer constant Matrix C oef0 that round after the processing based on first of 8 * 8 dot image signals, specific as follows:
5. and then respectively calculating among the floating-point parameter matrix Coef after the above-mentioned processing and amplifying relevant position element and above-mentioned first amplifies to revise and rounds the difference between the element of relevant position among the Matrix C oef0:
Coef[i] [j]=Coef[i] [j]-Coef0[i] [j], thus obtain corresponding matrix of differences;
6. each element is carried out following amplification correction respectively and is rounded processing and then in the matrix of differences that aforementioned calculation is obtained:
Coef1[i] [j]=(int) (Coef[i] [j] * (1<<P
2)+0.5)=(int) (Coef[i] [j] * (1<<3)+0.5), round Matrix C oef1 thereby obtain the second corresponding amplification correction;
Can obtain second 8 * 8 integer constant matrix that amplify after correction rounds processing like this based on 8 * 8 dot image signals, specific as follows:
7. suppose that each the coefficient element in the primary input transition coefficient matrix of 8 * 8 dot image signals is respectively Block[i] [j], then to each the coefficient element B lock[i in this transform coefficient matrix] [j] carry out following processing and amplifying respectively:
Block[i][j]=Block[i][j]×Coef0[i][j]+((Block[i][j]×Coef1[i][j])>>P
2)=
Block[i][j]=Block[i][j]×Coef0[i][j]+((Block[i][j]×Coef1[i][j])>>3);
And then to the coefficient element B lock[0 in the transform coefficient matrix] [0] carry out following processing and amplifying:
Block[0][0]=Block[0][0]+(1<<(P
1-1))=Block[0][0]+(1<<17)。
(2) round the conversion coefficient of pretreated 64 initial inputs based on above-mentioned amplification correction, and then the row one peacekeeping row one dimension of picture signal of 8 * 8 of two dimensions carried out conversion process according to process chart shown in Figure 4 respectively, at first go the calculation process of one dimension direction, carry out the calculation process of row one dimension direction again.
Here with the T among Fig. 4
1Calculating process is that example describes, according to following computing formula computational transformation subprocess T
1Output valve:
T
1=a×cos(π/8)-b×cos(3π/8)
Thereby can obtain following general expression formula according to following formula:
T
1=aw
1+bw
2
A in the following formula, b are respectively the image coefficient piece element values of input, also may be the picture signal median in the idct transform processing procedure certainly.The input value a here, b can also be for carrying out the digital signal conversion value of idct transform when handling to digital signal in addition, or are the median etc. in the idct transform processing procedure.
To specify below and how to calculate above-mentioned general expression formula T based on fixed point displacement and fixed point accumulation process
1=aw
1+ bw
2End value:
Here be without loss of generality, respectively with two constant value w
1, w
2Be decomposed into the binary expression form:
w
1=m
0+ m
12
-1+ ...+m
T-12
-t+1+ m
t 2-t(m
i=0 or 1, i=0,1 ... t)
w
2=n
0+ n
12
-1+ ...+n
T-12
-t+1+ n
t 2-t(n
i=0 or 1, i=0,1 ... t)
Like this based on above-mentioned with constant value w
1, w
2Be decomposed into the basis of binary expression form, then T
1=aw
1+ bw
2Expression formula just can be represented based on following expression formula:
Respectively with each am in the following formula
i+ bn
i, i=0,1 ..., t calculates, and just can calculate the T value by every result of calculation right shift is added up respectively, because m
i, n
iValue is 0 or 1 respectively, so each am
i+ bn
iHaving 4 kinds of possible values is respectively: 0, and a, b, a+b is for further speed up processing can be in the accumulation process calculating that is shifted based on fixed point
End value before, precompute the value of a+b, thereby calculating each am
i+ bn
iThe time just can be according to m
i, n
iValue condition effectively avoided multiplication.
According to above-mentioned to T
1The calculating principle of calculating process, following table has provided after fixed point displacement accumulation process is used in corresponding multiplying place in the IDCTAAN process chart based on the inventive method principle, in requisition for shift count and accumulative frequency, wherein B1 in this table and B2 represent w respectively
1, w
2Binary fraction:
Wherein go up in the table once ">>" representative shifting processing of need once fixing a point of every appearance, the accumulation process of need once fixing a point is represented in every appearance once "+" or "-", then as can be seen from the above table, IDCTAAN process chart based on the inventive method principle, one dimension 8 dot image signals are carried out idct transform when handling, and add up (Adds) number of times and fixed point displacement (Shifts) number of times of the fixed point that need carry out altogether is as shown in the table:
From the aforementioned calculation analytic process as can be seen, finish the idct transform of one dimension 8 dot image signals based on the inventive method and handle to fix a point for 50 times at most add operation and the shift operation of 26 fixed points, and avoided floating-point multiplication fully; Expand to two-dimensional case like this, finish the idct transform of two dimension 8 * 8 dot image signals and handle to fix a point for 801 times at most add operation and the shift operation of 416 fixed points, and avoided floating-point multiplication fully.This shows that the inventive method can be so that whole idct transform processing procedure based on the AAN algorithm had floating-point multiplication, thereby obtained a kind of IDCT Fast transforms scheme of brand-new no floating-point multiplication process, this IDCT Fast transforms scheme can be under the prerequisite that guarantees the idct transform operational precision, improved the arithmetic speed of idct transform greatly, and reduced too much consumption to the system hardware and software resource, therefore satisfied the demand of modern real time communication business preferably.
(3) last corresponding 64 output result signals also will finishing the IDCTAAN process chart conversion process shown in Fig. 4 (be designated as Block1[i] [j], i, j=0,1 ..., 7) carry out the following reprocessing of dwindling respectively:
Block1[i][j]=(Block1[i][j])>>P
1=(Block1[i][j])>>18;
Thereby the idct transform of two dimension 8 * 8 dot image signals after the inventive method that finally the is applied principle is handled the output end value.
Be that hypothesis is in the idct transform processing procedure based on AAN among above-mentioned first embodiment, use 32 shift register and accumulator fix a point respectively shifting processing and fixed point accumulation process, certainly can also use 24 shift register and accumulator fix a point respectively shifting processing and fixed point accumulation process here, taking and energy consumption when reducing to realize the inventive method principle to chip area based on hardware.When selecting for use 24 shift register and accumulator to fix a point shifting processing and fixed point accumulation process respectively, the default first amplification coefficient P in the above-mentioned first embodiment processing procedure
1Preferably adopt 12, amplify that to revise two integer constant matrixes that round processing as follows respectively thereby obtain 64 conversion coefficients to 8 * 8 dot image signal initial inputs:
Other implementation procedures repeat no more here with first embodiment.
Second embodiment: as shown in Figure 5, after using the inventive method principle, the idct transform based on AAN among above-mentioned prior art Fig. 1 is handled and is upgraded flow chart, wherein in this second embodiment, no matter in idct transform processing procedure based on AAN, use 32 shift register and the accumulator accumulating operation that is shifted to handle, also be to use 24 shift register and the accumulator accumulating operation that is shifted to handle, it is all similar respectively that it carries out the implementation procedure narrated among process that idct transform handles and above-mentioned first embodiment to 8 * 8 dot image signals, and its specific implementation process please refer to the associated description among above-mentioned first embodiment.
Method principle corresponding to the above-mentioned proposition of the present invention, the proposition that the present invention is also corresponding here a kind of inverse discrete cosine transform device, as shown in Figure 6, the main composition structured flowchart of the inverse discrete cosine transform device that proposes for the present invention, it mainly comprises conversion coefficient processing unit 10, unit 20 and the result data processing unit 30 of adding up that be shifted, and wherein the concrete effect of each component units is as follows:
Conversion coefficient processing unit 10 is mainly used in the idct transform processing procedure of digital signal being carried out based on the AAN algorithm, respectively each conversion coefficient of initial input is amplified to revise to round processing;
The displacement unit 20 that adds up is mainly used in each conversion coefficient amplified through above-mentioned conversion coefficient processing unit 10 and revises the idct transform process that rounds after the processing, based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process;
Result data processing unit 30 is mainly used in the above-mentioned displacement unit 20 that adds up is carried out the corresponding processing of dwindling respectively based on each final idct transform result data of the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process.
Further please refer to Fig. 7, this figure is the concrete composition structured flowchart of conversion coefficient processing unit in apparatus of the present invention, wherein conversion coefficient processing unit 10 comprises that specifically matrix amplifies subelement 110, first matrix determines that subelement 120, matrix of differences are asked for subelement 130, second matrix determines that subelement 140 and transform coefficient matrix amplify subelement 150, and wherein each concrete effect of forming subelement is as follows:
Matrix amplifies subelement 110, is used for based on first amplification coefficient each element of floating-point parameter matrix of digital signal being carried out processing and amplifying respectively, obtains corresponding amplification floating-point parameter matrix;
First matrix is determined subelement 120, is used for above-mentioned matrix is amplified each element of amplification floating-point parameter matrix after subelement 110 processing and amplifying revising respectively and rounding processing based on rounding corrected parameter, obtains corresponding first and amplifies to revise and round matrix;
Matrix of differences is asked for subelement 130, be used for calculating respectively that above-mentioned matrix amplifies that amplification floating-point parameter matrix relevant position element and above-mentioned first matrix after subelement 110 processing and amplifying determine that subelement 120 obtains first amplifies to revise and round the difference between the element of relevant position in the matrix, obtain the matrix of differences of correspondence;
Second matrix is determined subelement 140, be used for above-mentioned matrix of differences is asked for each element of matrix of differences that subelement 130 obtains amplifying respectively to revise and rounding processing, obtain corresponding second and amplify to revise and round matrix based on second amplification coefficient and the above-mentioned corrected parameter that rounds;
Transform coefficient matrix amplifies subelement 150, be used for first amplifying revise that the element that rounds the matrix relevant position and second matrix determine that subelement 140 obtains second amplify and revise the element that rounds relevant position in the matrix and respectively the element of same position in the primary input transition coefficient matrix of digital signal is carried out corresponding processing and amplifying, revise the purpose that rounds processing thereby reach each conversion coefficient of initial input carried out to amplify based on what above-mentioned first matrix determined that subelement 120 obtains.
Further please refer to Fig. 8, this figure is the add up concrete composition structured flowchart of unit of displacement in apparatus of the present invention, wherein the displacement unit 20 that adds up specifically comprises conversion subelement 210, displacement add up output bear fruit unit 220 and input value addition subelement 230, and wherein each concrete effect of forming subelement is as follows:
Input value addition subelement 230 is used for calculating in displacement the bear fruit unit 220 of output that adds up
End value before, precompute
In different input value a, b sum a+b;
The displacement output unit 220 that bears fruit that adds up is used for the result of calculation according to above-mentioned input value addition subelement 230, calculates based on fixed point displacement accumulating operation that above-mentioned conversion subelement 210 changes out
End value, and with the output valve of result of calculation value as the correspondent transform subprocess.
The wherein above-mentioned displacement unit 20 that adds up can adopt 24 displacement accumulation processor to realize, also can adopt 32 displacement accumulation processor to realize.
Wherein the input value a that mentions in the said apparatus, b can but be not limited to be respectively digital signal carried out the digital signal conversion value of idct transform when handling, or be the median in the idct transform processing procedure; Can also be respectively the image coefficient piece element value when in the compressed image decode procedure, carrying out the idct transform processing, or be respectively the median in the idct transform processing procedure.
Realize that for other the concrete technology in the inverse discrete cosine transform device of the present invention details can realize the description of details with reference to the correlation technique in the above-mentioned discrete cosine inverse transformation method of the present invention, no longer gives too much to give unnecessary details here.
In addition, because the algorithm structure of dct transform and idct transform is similar, so relevant dct transform based on the AAN algorithm is handled equally and can just no longer be given too much to give unnecessary details here with reference to the idct transform processing procedure that the present invention is based on the AAN algorithm.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (21)
1, a kind of discrete cosine inverse transformation method is characterized in that, comprises step:
In the inverse discrete cosine transform processing procedure of the transformation coefficient block in the image encoding being carried out, respectively each conversion coefficient in the transformation coefficient block of initial input is amplified correction and round processing based on the AAN algorithm;
Revise the conversion process that rounds after the processing for each conversion coefficient through amplifying, based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process;
Each final inverse discrete cosine transform result data based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process is carried out the corresponding processing of dwindling respectively.
2, the method for claim 1 is characterized in that, described transformation coefficient block refers to two dimension 8 * 8 dot factor matrixes in the image encoding.
3, method as claimed in claim 2, it is characterized in that, described each conversion coefficient in the transformation coefficient block of initial input is amplified to revise round processing and specifically be meant: amplify based on first and revise the correspondence position element and second that rounds in the matrix and amplify and revise the correspondence position element that rounds in the matrix and respectively the same position coefficient element in two dimension 8 * 8 dot factor matrixes is amplified to revise and round processing.
4, method as claimed in claim 3 is characterized in that, each the coefficient element in two dimension 8 * 8 dot factor matrixes is carried out following amplification correction round processing:
Block[i][j]=Block[i][j]×Coef0[i][j]+((Block[i][j]×Coef1[i][j])>>P
2);
And to the coefficient element B lock[0 in the coefficient matrix] [0] carry out following processing and amplifying:
Block[0][0]=Block[0][0]+(1<<(P
1-1));
Block[i wherein] [j] refer to the coefficient element in two dimension 8 * 8 dot factor matrixes, i, j=0,1 ..., 7; P
1And P
2Be two default amplifying parameters; Coef0 refers to that the first amplification correction rounds matrix, and Coef1 refers to that the second amplification correction rounds matrix.
5, method as claimed in claim 4 is characterized in that, the described first amplification correction rounds Matrix C oef0 and determines according to following processing procedure:
Default one rounds corrected parameter Δ τ;
Based on Coef[i] each element in 8 * 8 floating-point parameter matrixs of [j] expression, i, j=0,1 ..., 7;
Respectively to each the Elements C oef[i in the described floating-point parameter matrix] [j] carry out following processing and amplifying:
Coef[i][j]=Coef[i][j]×(1<<P
1);
Then respectively to each the Elements C oef[i after the processing and amplifying] [j] carry out the following processing that rounds:
Coef0[i] and [j]=(int) (Coef[i] [j]+Δ τ), obtain the first amplification correction and round Matrix C oef0.
6, method as claimed in claim 4 is characterized in that, the described second amplification correction rounds Matrix C oef1 and determines according to following processing procedure:
Default one rounds corrected parameter Δ τ;
Based on Coef[i] each element in 8 * 8 floating-point parameter matrixs of [j] expression, i, j=0,1 ..., 7;
Respectively to each the Elements C oef[i in the described floating-point parameter matrix] [j] carry out following processing and amplifying:
Coef[i][j]=Coef[i][j]×(1<<P
1);
Then respectively to each the Elements C oef[i after the processing and amplifying] [j] carry out the following processing that rounds:
Coef0[i] and [j]=(int) (Coef[i] [j]+Δ τ), obtain the first amplification correction and round Matrix C oef0;
Calculate the relevant position Elements C oef[i in the floating-point parameter matrix after the described processing and amplifying respectively] [j] and described first amplify revise the relevant position Elements C oef0[i that rounds in the matrix] difference of [j]:
Coef[i] [j]=Coef[i] [j]-Coef0[i] [j], obtain corresponding matrix of differences;
Respectively to each the Elements C oef[i in the described matrix of differences] [j] carry out following processing:
Coef1[i] [j]=(int) (Coef[i] [j] * (1<<P
2)+Δ τ), obtain the second amplification correction and round Matrix C oef1.
7, method as claimed in claim 5 is characterized in that,
Each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=18, P
2=3, Δ τ=0.5;
The described first amplification correction rounds Matrix C oef0 and is:
8, method as claimed in claim 5 is characterized in that,
Each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=12, P
2=3, Δ τ=0.5;
The described first amplification correction rounds Matrix C oef0 and is:
9, method as claimed in claim 6 is characterized in that,
Each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=18, P
2=3, Δ τ=0.5;
The described second amplification correction rounds Matrix C oef1 and is:
10, method as claimed in claim 6 is characterized in that,
Each Elements C oef[i in described 8 * 8 floating-point parameter matrixs] [j]=A
i* A
j, wherein
Described P
1=12, P
2=3, Δ τ=0.5;
The described second amplification correction rounds Matrix C oef1 and is:
11, the method for claim 1 is characterized in that, the process of the corresponding floating-point multiplication that occurs in the accumulating operation alternative transforms that is shifted based on the fixing a point process specifically comprises:
At utilizing aw based on different input value a, b in the conversion process
1+ bw
2Each varitron process of output valve is asked in computing, by with constant value w
1And w
2Dissolve and be binary form, with aw
1+ bw
2Computing is converted to
Computing, wherein m
i, n
iValue is 0 or 1 respectively, and t is a positive integer; And
Calculating is respectively changed out based on fixed point displacement accumulating operation
End value, and with the output valve of result of calculation value as the correspondent transform subprocess, wherein, the transformed value when described input value a, b are respectively the transformation coefficient block in the image encoding carried out inverse discrete cosine transform and handle; Or be the median in the inverse discrete cosine transform processing procedure; Or the image coefficient piece element value when in the compressed image decode procedure, carrying out inverse discrete cosine transform and handle.
12, as claim 1 or 11 described methods, it is characterized in that, based on 24 shift registers and the accumulator accumulating operation that is shifted of fixing a point.
13, as claim 1 or 11 described methods, it is characterized in that, based on 32 shift registers and the accumulator accumulating operation that is shifted of fixing a point.
15, method as claimed in claim 4 is characterized in that, respectively to each final inverse discrete cosine transform result data Block1[i] [j], i, j=0,1 ..., 7 dwindling of execution are treated to:
Block1[i][j]=(Block1[i][j])>>P
1。
16, a kind of inverse discrete cosine transform device is characterized in that, comprising:
The conversion coefficient processing unit is used in the transformation coefficient block to image encoding carries out inverse discrete cosine transform processing procedure based on the AAN algorithm, respectively each conversion coefficient in the transformation coefficient block of initial input is amplified to revise to round processing;
The displacement unit that adds up is used for each conversion coefficient amplified through the conversion coefficient processing unit and revises the conversion process that rounds after the processing, based on the corresponding floating-point multiplication that occurs in the fixed point displacement accumulating operation alternative transforms process;
The result data processing unit is used for add up each final inverse discrete cosine transform result data of the corresponding floating-point multiplication that the unit occurs based on fixed point displacement accumulating operation alternative transforms process of displacement is carried out the corresponding processing of dwindling respectively.
17, device as claimed in claim 16 is characterized in that, described conversion coefficient processing unit specifically comprises:
Matrix amplifies subelement, is used for based on first amplification coefficient, respectively each element in the floating-point parameter matrix of the transformation coefficient block in the image encoding is carried out processing and amplifying, obtains corresponding amplification floating-point parameter matrix;
First matrix is determined subelement, is used for based on rounding corrected parameter each element correction that matrix amplifies the amplification floating-point parameter matrix after the subelement processing and amplifying being rounded processing, obtains corresponding first and amplifies to revise and round matrix;
Matrix of differences is asked for subelement, what be used for that element that compute matrix respectively amplifies the amplification floating-point parameter matrix relevant position after the subelement processing and amplifying and first matrix determine that subelement obtains first amplifies the difference of revising between the element that rounds relevant position in the matrix, obtains the matrix of differences of correspondence;
Second matrix is determined subelement, is used for based on second amplification coefficient and rounds corrected parameter respectively matrix of differences being asked for each element of matrix of differences that subelement obtains and amplifying to revise and round processing, obtains corresponding second and amplifies to revise and round matrix;
Transform coefficient matrix amplifies subelement, is used for first amplifying revise that the element that rounds the matrix relevant position and second matrix determine that subelement obtains second amplify and revise the element that rounds relevant position in the matrix and respectively the element of same position in the transform coefficient matrix of described initial input is carried out processing and amplifying based on what first matrix determined that subelement obtains.
18, device as claimed in claim 16 is characterized in that, the described displacement unit that adds up specifically comprises:
The conversion subelement is used for utilizing aw at conversion process based on different input value a, b
1+ bw
2Each varitron process of output valve is asked in computing, by with constant value w
1And w
2Dissolve and be binary form, with aw
1+ bw
2Computing is converted to
Computing, wherein m
i, n
iValue is 0 or 1 respectively, and t is a positive integer;
Displacement adds up and exports the unit that bears fruit, and is used for changing out based on fixed point displacement accumulating operation calculating conversion subelement
End value, and with the output valve of result of calculation value as the correspondent transform subprocess, wherein, the transformed value when described input value a, b are respectively the transformation coefficient block in the image encoding carried out inverse discrete cosine transform and handle; Or be the median in the inverse discrete cosine transform processing procedure; Or the image coefficient piece element value when in the compressed image decode procedure, carrying out inverse discrete cosine transform and handle.
19, device as claimed in claim 18 is characterized in that, the described displacement unit that adds up specifically also comprises input value addition subelement, is used in the described displacement output subunit computes as a result that adds up
End value before, calculate described
In different input value a, b sum a+b.
As claim 16,18 or 19 described devices, it is characterized in that 20, the described displacement unit that adds up is 24 a displacement accumulation processor.
As claim 16,18 or 19 described devices, it is characterized in that 21, the described displacement unit that adds up is 32 a displacement accumulation processor.
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