CN100561993C - A kind of rebuilt-up device for digital asynchronous clock - Google Patents

A kind of rebuilt-up device for digital asynchronous clock Download PDF

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CN100561993C
CN100561993C CNB2007100627380A CN200710062738A CN100561993C CN 100561993 C CN100561993 C CN 100561993C CN B2007100627380 A CNB2007100627380 A CN B2007100627380A CN 200710062738 A CN200710062738 A CN 200710062738A CN 100561993 C CN100561993 C CN 100561993C
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clock
frequency
digital
signal
control word
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CN101001228A (en
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陈培
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Beihang University
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Beihang University
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Abstract

The invention discloses a kind of rebuilt-up device for digital asynchronous clock, form by digital signal input interface, digital signal output interface, asynchronous FIFO memory, nonvolatile memory, general processor, first clock distributor, second clock distributor, first band pass filter, second band pass filter, digital frequency synthesizer and high speed crystal resonator; Apparatus of the present invention are separate with the clock of output digital signal with the clock of supplied with digital signal, uncertain problem at the clock jitter of supplied with digital signal, using asynchronous buffer mechanism that dateout is done to lag behind with respect to the input data handles, like this when supplied with digital signal clock and output digital signal clock exist the frequency of short-term or phase place difference, use DDS to regenerate the output clock, utilize the clock distribution chip further to improve the quality of output clock.Utilize general processor that the output frequency of DDS is finely tuned, thereby eliminate supplied with digital signal clock and the long run frequency difference of exporting the digital signal clock, avoid the asynchronous buffer device to overflow or full sky.Guaranteed that like this shake of output digital signal clock and the shake of input clock have nothing to do, and only are subjected to the output jitter performance impact of multichannel DDS chip and clock distribution chip.

Description

A kind of rebuilt-up device for digital asynchronous clock
Technical field
The present invention relates to a kind of asynchronous clock reconstructing device, more particularly say, be meant a kind of asynchronous clock reconstructing device that is used to eliminate the digital signal clock jitter.
Background technology
Digital signal tends to the outer clock jitter of plus in the process of processed and transmission, though these clock jitters can not constitute influence to the correctness of data content, can reduce the precision of digital-to-analogue conversion.If clock jitter is too serious, also may cause the digital information in the communication process to lose position or dislocation.
Summary of the invention
The purpose of this invention is to provide a kind of rebuilt-up device for digital asynchronous clock, this device is separate with the clock of output digital signal with the clock of supplied with digital signal, and according to the digital signal and the clock of outside input, rebuild a low jitter asynchronous clock, thereby realize the jitter elimination of input digit clock signal.
The present invention is a kind of rebuilt-up device for digital asynchronous clock, is made up of digital signal input interface, digital signal output interface, asynchronous FIFO memory, nonvolatile memory, general processor, first clock distributor, second clock distributor, first band pass filter, second band pass filter, digital frequency synthesizer and high speed crystal resonator.
Described asynchronous FIFO memory receives the band dithering clock signal D by the output of digital signal input interface 1, the auspicious synchronizing signal D of band shake 2With initial data D 3, and will be with dithering clock signal D 1Auspicious synchronizing signal D with the band shake 2As the storage triggering signal, described storage triggering signal is in order to described initial data D 3Be stored in the asynchronous FIFO memory according to the first-in first-out mode;
Described general processor reads the data digital D in the asynchronous FIFO memory continuously 6, and according to a described data digital D 6Rewrite the frequency control word D of general processor output 7, frequency division multiple control word A D 8, frequency division multiple control word B D 9
The frequency control word D of described digital frequency synthesizer to receiving 7With reference frequency f 0Difference output frequency A f after the Direct Digital frequency synthesis is handled 1Give first band pass filter, output frequency B f 2Give second band pass filter; Through filtered frequency A f 1Export to first clock distributor, through filtered frequency B f 2Export to the second clock distributor;
Described first clock distributor is according to the frequency division multiple control word A D that receives 8To filtered frequency A f 1Carry out frequency division and handle the auspicious synchronizing signal D of acquisition reconstruction 5
Described second band pass filter is according to the frequency division multiple control word B D that receives 9To filtered frequency B f 2Carry out frequency division and handle acquisition reconstruction clock signal D 4
Described asynchronous FIFO memory is according to the reconstruction clock signal D that receives 4, rebuild auspicious synchronizing signal D 5As read trigger signal, described read trigger signal is in order to described initial data D 3Export the digital signal output interface to according to the first-in first-out mode, and export through the digital signal output interface.
The advantage of rebuilt-up device for digital asynchronous clock of the present invention is: (1) is by utilizing independent clock source and many/single channel DDS chip, rebuild the clock signal and the auspicious synchronizing signal of low jitter, thoroughly eliminated of the influence of supplied with digital signal clock jitter output digital signal clock jitter; (2) in conjunction with the many/single channel DDS chip of asynchronous FIFO and general processor control, avoided respectively since short-term between input clock and the output clock and long-term difference may cause lose the position or misplace; (3) at short notice, the shake of input clock is not more than half of asynchronous FIFO total capacity, not can because of the input and output clock asynchronous cause data lose the position or the dislocation; (4) rebuild the low jitter characteristic that clock not only can guarantee to rebuild the great dynamic range of clock but also can guarantee to rebuild clock owing to being used in combination many/single channel DDS chip and clock distribution chip; (5) owing to introduced general processor frequency is carried out tracking Control, reduced absolute precision requirement crystal oscillator or external clock; (6) asynchronous clock reconstructing device of the present invention can improve the clock jitter problem that causes in the data processing transmission course, thereby prolongs the distance of transfer of data.
Description of drawings
Fig. 1 is the structured flowchart of rebuilt-up device for digital asynchronous clock of the present invention.
Among the figure: 1. digital signal input interface 2. digital signal output interfaces 3. asynchronous FIFO memories 4. non-volatile memories 5. general processors 6. first clock distributors 7. first band pass filters 8. digital frequency synthesizers 9. high speed crystal resonators 10. second clock distributors 11. second band pass filters
Embodiment
The present invention is described in further detail below in conjunction with accompanying drawing.
See also shown in Figure 1, the present invention is a kind of rebuilt-up device for digital asynchronous clock, is made up of digital signal input interface 1, digital signal output interface 2, asynchronous FIFO memory 3, nonvolatile memory 4, general processor 5, first clock distributor 6, second clock distributor 10, first band pass filter 7, second band pass filter 11, digital frequency synthesizer (DDS chip) 8 and high speed crystal resonator 9.
Be set with relevant nominal value and initial value in the nonvolatile memory 4 among the present invention, these nominal values and initial value read usefulness for general processor 5 when handling.Be set with in the nonvolatile memory 4:
Band dithering clock signal D 1Nominal value D 1〉=4D 2
The auspicious synchronizing signal D of band shake 2Nominal value;
Reference frequency f 0Nominal value f 0〉=10 * D 1
Frequency control word D 7Initial value include clock frequency synthesis and auspicious synchronous frequency synthesis, wherein, the clock frequency synthesis is [2,4,8,16] band dithering clock signal D doubly 1Nominal value, auspicious synchronous frequency synthesis are the auspicious synchronizing signal D of [8,16,32] band shake doubly 2Nominal value;
Frequency division multiple control word A D 8Initial value be [8,16,32];
Frequency division multiple control word B D 9Initial value be [2,4,8,16].
In the present invention, the data flow of timing reconstruction is:
(1) asynchronous FIFO memory 3 receives the band dithering clock signal D that is exported by digital signal input interface 1 1, the auspicious synchronizing signal D of band shake 2With initial data D 3, and will be with dithering clock signal D 1Auspicious synchronizing signal D with the band shake 2As the storage triggering signal, described storage triggering signal is in order to described initial data D 3Be stored in the asynchronous FIFO memory 3 according to the first-in first-out mode; Initial data D in described asynchronous FIFO memory 3 3The enabling signal of general processor 5 appears for the first time being considered as when half-full.
(2) general processor 5 reads the data digital D in the asynchronous FIFO memory 3 continuously 6, and according to a described data digital D 6Rewrite the frequency control word D of general processor 5 outputs 7, frequency division multiple control word AD 8, frequency division multiple control word B D 9Thereby keep a described data digital D 6Relatively stable;
(3) high speed crystal resonator 9 is used to provide reference frequency f 0Give digital frequency synthesizer (DDS chip) 8;
(4) the frequency control word D of 8 pairs of receptions of digital frequency synthesizer (DDS chip) 7With reference frequency f 0Difference output frequency A f after the Direct Digital frequency synthesis is handled 1Give first band pass filter 7, output frequency B f 2Give second band pass filter 11; Through filtered frequency A f 1Export to first clock distributor 6, through filtered frequency B f 2Export to second clock distributor 10; In the present invention, the DDS chip can be the frequency synthesis chip of multichannel, also can be the frequency synthesis chip of single channel.
(5) first clock distributors 6 are according to the frequency division multiple control word A D that receives 8To filtered frequency A f 1Carry out frequency division and handle the auspicious synchronizing signal D of acquisition reconstruction 5
(6) second band pass filters 11 are according to the frequency division multiple control word B D that receives 9To filtered frequency Bf 2Carry out frequency division and handle acquisition reconstruction clock signal D 4
(7) asynchronous FIFO memory 3 is according to the reconstruction clock signal D that receives 4, rebuild auspicious synchronizing signal D 5As read trigger signal, described read trigger signal is in order to described initial data D 3Export digital signal output interface 2 to according to the first-in first-out mode;
(8) the digital signal output interface 2 reconstruction clock signal D that will receive 4, rebuild auspicious synchronizing signal D 5, initial data D 3Output.
In the present invention, frequency division multiple control word A D 8, frequency division multiple control word B D 9Be the frequency instruction of two different multiples, wherein, frequency division multiple control word B D 9The frequency division multiple be [2,4,8,16], frequency division multiple control word A D 8The frequency division multiple be [8,16,32].
In the present invention, frequency A f 1, frequency B f 2Be two different frequencies, wherein, frequency A f 1Frequency for rebuilding auspicious synchronizing signal D 5[8,16,32] of frequency doubly, frequency B f 2Frequency for rebuilding clock signal D 4[2,4,8,16] of frequency doubly.
In the present invention, general processor 5 is according to a data digital D 6Adopt pid algorithm to frequency control word D 7Dynamically adjust.
Embodiment:Be used for realizing the clock jitter elimination of serial communication process
Experiment condition: 1 input of digital signal input interface: band dithering clock signal D1 nominal value is 10.24MHz, the auspicious synchronizing signal D2 nominal value of band shake is 0.32MHz, the transmission rate nominal value of initial data D3 is 10.24Mbps, wherein, band dithering clock signal D1 and the auspicious synchronizing signal D2 of band shake are dithered as 10ps RMS, and absolute error is 0.High speed crystal resonator 9 nominal values are 102.4MHz, and actual value is 102.399MHz.The initial value of frequency control word D7 is [1/ (10 * 4), 1/ (320 * 32)], revise through PID, corrected frequency control word D7 is [10.24/ (102.399 * 4), (0.32/ 102.399 * 32)], if 48 of the frequency accuracies of digital frequency synthesizer 8, the reconstruction clock signal D4 nominal value of output is 10.24MHz, rebuilding auspicious synchronizing signal D5 nominal value is 0.32MHz, the transmission rate nominal value of initial data D3 is 10.24Mbps, the dither signal of wherein rebuilding the auspicious synchronizing signal D5 output of clock signal D4 and reconstruction is 0.7ps RMS, and absolute error is ± 0.4 μ Hz.Clock after apparatus of the present invention are handled, its shake is reduced to 0.7ps RMS, has improved the clock jitter that causes in the initial data D3 transmission course effectively, has prolonged data transmission distance.
Rebuilt-up device for digital asynchronous clock of the present invention adopts band dithering clock signal D 1Auspicious synchronizing signal D with the band shake 2As the storage triggering signal, with reconstruction clock signal D 4With the auspicious synchronizing signal D of reconstruction 5Realized being stored in initial data D in the asynchronous FIFO memory 3 as read trigger signal 3Hysteresis handle.Uncertain problem at the clock jitter of supplied with digital signal, using asynchronous buffer mechanism that dateout is done to lag behind with respect to the input data handles, like this when supplied with digital signal clock and output digital signal clock exist the frequency of short-term or phase place difference, use DDS to regenerate the output clock, utilize the clock distribution chip further to improve the quality of output clock, make the clock of supplied with digital signal separate with the clock of output digital signal.
In the present invention, digital signal input interface 1 can be the external digital signal transmission medium, also can be internal digital signal transmission wire or printed circuit board (PCB) and wireless medium; Digital signal output interface 2 can be the external digital signal transmission medium, also can be internal digital signal transmission wire or printed circuit board (PCB) and wireless medium; Described asynchronous memory 3 can be that special-purpose asynchronous FIFO chip also can be the asynchronous FIFO that utilizes programmable logic device such as FPGA to realize, can also be the software asynchronous FIFO of realizing by High Speed General processor or DSP and high-speed memory; Described general processor 5 can be High Speed General processor, MCU, DSP or utilize programmable logic devices such as FPGA to realize the device of similar general processor function; Digital frequency synthesizer 8 is chosen the DDS chip.
Rebuilt-up device for digital asynchronous clock of the present invention is at the uncertain problem at the clock jitter of supplied with digital signal, using asynchronous buffer mechanism that dateout is done to lag behind with respect to the input data handles, when supplied with digital signal clock and output digital signal clock exist the frequency of short-term or phase place difference, can not cause dislocation or lose the position like this.Use DDS to regenerate the output clock, utilize the clock distribution chip further to improve the quality of output clock.Utilize general processor that the output frequency of DDS is finely tuned, thereby eliminate supplied with digital signal clock and the long run frequency difference of exporting the digital signal clock, avoid the full up or full sky of asynchronous buffer device.

Claims (7)

1, a kind of rebuilt-up device for digital asynchronous clock is characterized in that: be made up of digital signal input interface (1), digital signal output interface (2), asynchronous FIFO memory (3), nonvolatile memory (4), general processor (5), first clock distributor (6), second clock distributor (10), first band pass filter (7), second band pass filter (11), digital frequency synthesizer (8) and high speed crystal resonator (9);
Described asynchronous FIFO memory (3) receives the band dithering clock signal D by digital signal input interface (1) output 1, the auspicious synchronizing signal D of band shake 2With initial data D 3, and will be with dithering clock signal D 1Auspicious synchronizing signal D with the band shake 2As the storage triggering signal, described storage triggering signal is in order to described initial data D 3Be stored in the asynchronous FIFO memory (3) according to the first-in first-out mode;
Described general processor (5) reads the data digital D in the asynchronous FIFO memory (3) continuously 6, and according to a described data digital D 6Rewrite the frequency control word D of general processor (5) output 7, frequency division multiple control word A D 8, frequency division multiple control word B D 9
The frequency control word D of described digital frequency synthesizer (8) to receiving 7With reference frequency f 0Difference output frequency A f after the Direct Digital frequency synthesis is handled 1Give first band pass filter (7), output frequency B f 2Give second band pass filter (11); Through filtered frequency A f 1Export to first clock distributor (6), through filtered frequency B f 2Export to second clock distributor (10);
Described first clock distributor (6) is according to the frequency division multiple control word A D that receives 8To filtered frequency Af 1Carry out frequency division and handle the auspicious synchronizing signal D of acquisition reconstruction 5
Described second band pass filter (11) is according to the frequency division multiple control word B D that receives 9To filtered frequency Bf 2Carry out frequency division and handle acquisition reconstruction clock signal D 4
Described asynchronous FIFO memory (3) is according to the reconstruction clock signal D that receives 4, rebuild auspicious synchronizing signal D 5As read trigger signal, described read trigger signal is in order to described initial data D 3Export digital signal output interface (2) to according to the first-in first-out mode, and export through digital signal output interface (2).
2, rebuilt-up device for digital asynchronous clock according to claim 1 is characterized in that: frequency division multiple control word AD 8, frequency division multiple control word B D 9Be the frequency instruction of two different multiples, wherein, frequency division multiple control word B D 9The frequency division multiple be [2,4,8,16], frequency division multiple control word A D 8The frequency division multiple be [8,16,32].
3, rebuilt-up device for digital asynchronous clock according to claim 1 is characterized in that: frequency A f 1, frequency B f 2Be two different frequencies, wherein, frequency A f 1Frequency for rebuilding auspicious synchronizing signal D 5[8,16,32] of frequency doubly, frequency B f 2Frequency for rebuilding clock signal D 4[2,4,8,16] of frequency doubly.
4, rebuilt-up device for digital asynchronous clock according to claim 1 is characterized in that: described general processor (5) is according to a data digital D 6Adopt pid algorithm to frequency control word D 7Dynamically adjust.
5, rebuilt-up device for digital asynchronous clock according to claim 1 is characterized in that: adopt band dithering clock signal D 1Auspicious synchronizing signal D with the band shake 2As the storage triggering signal, with reconstruction clock signal D 4With the auspicious synchronizing signal D of reconstruction 5Realized being stored in initial data D in the asynchronous FIFO memory (3) as read trigger signal 3Hysteresis handle.
6, rebuilt-up device for digital asynchronous clock according to claim 1 is characterized in that: the initial data D in the described asynchronous FIFO memory (3) 3The enabling signal of general processor (5) appears for the first time being considered as when half-full.
7, rebuilt-up device for digital asynchronous clock according to claim 1 is characterized in that: described nonvolatile memory is set with in (4):
Band dithering clock signal D 1Nominal value D 1〉=4D 2
The auspicious synchronizing signal D of band shake 2Nominal value;
Reference frequency f 0Nominal value f 0〉=10 * D 1
Frequency control word D 7Initial value include clock frequency synthesis and auspicious synchronous frequency synthesis, wherein, the clock frequency synthesis is [2,4,8,16] band dithering clock signal D doubly 1Nominal value, auspicious synchronous frequency synthesis are the auspicious synchronizing signal D of [8,16,32] band shake doubly 2Nominal value;
Frequency division multiple control word A D 8Initial value be [8,16,32];
Frequency division multiple control word B D 9Initial value be [2,4,8,16].
CNB2007100627380A 2007-01-16 2007-01-16 A kind of rebuilt-up device for digital asynchronous clock Expired - Fee Related CN100561993C (en)

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CN102163977B (en) * 2011-03-14 2014-04-02 中国电子科技集团公司第二十四研究所 Direct digital frequency synthesizer (DDS) modulation system capable of reducing output signal time domain discontinuity
US10037293B2 (en) * 2015-02-17 2018-07-31 Nephos (Hefei) Co. Ltd. Wafer-level package having asynchronous FIFO buffer used to deal with data transfer between different dies and associated method
CN108696716A (en) * 2017-04-07 2018-10-23 上海峰宁信息科技股份有限公司 A kind of timing reconstruction processing method and module for data image signal
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US10928850B2 (en) * 2019-04-25 2021-02-23 Realtek Semiconductor Corporation First in and first out apparatus and driving method thereof
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