CN100559690C - The switch regulator of primary side control - Google Patents

Abstract

A kind of switch regulator comprises switching device and control circuit, and switching device is used to switch the transformer that is transformed into secondary side from primary side.Control circuit produces the switching signal of the output be used to regulate switch regulator.Control circuit comprises first circuit, second circuit, first feedback circuit, second feedback circuit and control switching circuit.First circuit produces first signal and clock signal by the reflected signal of measuring transformer, and second circuit produces secondary signal by integration current signal and clock signal, wherein the primary side switch current of current signal indication transformer.First feedback circuit produces first feedback signal according to first signal and reference signal, and wherein reference signal changes according to the variation of secondary signal.Second feedback circuit produces second feedback signal according to secondary signal.Control switching circuit produces switching signal according to feedback signal.

Description

The switch regulator of primary side control

Technical field

The present invention relates to a kind of switch regulator, and it relates to a kind of isolated switch regulator or rather.

Background technology

Various switch regulators have been widely used in providing regulation voltage and electric current.For the sake of security, off-line type (off-line) switch regulator must provide the isolation between its primary side (primary side) and the secondary side (secondary side).Therefore, equip a control circuit, need an optical coupler (optical-coupler) and secondary side circuit to regulate the output voltage and the output current of switch regulator at the primary side of switch regulator.Be size and the cost that reduces switch regulator, the needs of removing optical coupler and secondary side circuit are current trend.

In the development of coming in, many primary side controlling schemes have been disclosed, the United States Patent (USP) the 6th that is entitled as " regulating the output voltage of primary side and pulse-width modulation (PWM) controller of output current " such as Yang Dayong people such as (Ta-yungYang), 721, No. 192, people's such as Yang Dayong the United States Patent (USP) the 6th that is entitled as " the PWM controller that tool improves the primary side adjusting of load regulation ", 836, No. 415, the United States Patent (USP) the 6th that is entitled as " flyback (flyback) power converter that under primary side PWM control, has constant voltage and constant current output " with people such as Yang Dayong, 862, No. 194.Yet, the inaccuracy control that the aforementioned shortcoming that has known primary side controlling schemes now is output voltage and output current.

Target of the present invention provides a kind of output voltage of the primary side that can accurately control switch regulator and the switch regulator of output current.Therefore, reduce the size and the cost of described switch regulator.

Summary of the invention

The switch regulator (switch regulator) of a kind of primary side control comprises that one switches element, with switching transformer energy is delivered to secondary side from the primary side of described switch regulator.One control circuit is coupled to described transformer, is used to produce switching signal, to switch described switching device and to regulate the output of switch regulator.Comprise first circuit that is coupled to transformer in the described control circuit, be used for producing first signal and clock signal by the reflected signal of measuring transformer.The discharge time of clock signal indication transformer.Second circuit and tertiary circuit produce secondary signal by integration current signal and described clock signal, the primary side switch current of wherein said current signal indication transformer.In addition, the time constant of tertiary circuit is associated with the switching cycle of switching signal.First error amplifier that receives first reference signal is used for producing first feedback signal according to first signal.Be to improve load regulation, increase by first reference signal according to the increase of secondary signal.Second feedback signal is to be produced according to secondary signal by second error amplifier that receives second reference signal.Therefore, switching signal is to be produced according to first feedback signal and second feedback signal by control switching circuit.When enabling switching signal, switching signal has minimum ON time (on-time), and then has guaranteed the minimum value of discharge time, is used for reflected signal is carried out multiple sampling.

Should be appreciated that, aforementioned general describe and following detailed description be exemplary, and wish as advocated for the invention provides further explanation.From the consideration of description and accompanying drawing subsequently, will understand further target and advantage.

Description of drawings

Fig. 1 is the circuit diagram that illustrates the switch regulator of an existing known primary side control.

Fig. 2 is the key waveforms that illustrates an existing known switch regulator.

Fig. 3 is the control circuit according to one embodiment of the invention.

Fig. 4 is first circuit according to one embodiment of the invention.

Fig. 5 is the oscillator according to one embodiment of the invention.

Fig. 6 is the second circuit according to one embodiment of the invention.

Fig. 7 is the tertiary circuit according to one embodiment of the invention.

Fig. 8 is the pwm circuit according to one embodiment of the invention.

Fig. 9 is the circuit diagram according to the adder of one embodiment of the invention.

Figure 10 is used to programme the adjustment circuit of reference signal according to one embodiment of the invention.

Embodiment

See also shown in Figure 1ly, the switch regulator of an existing known primary side control is described.Described switch regulator comprises transformer 10, and it has auxiliary winding N _A, a winding N _P, and secondary winding N _SFor regulating the output voltage V of switch regulator _OWith output current I _O, control circuit 70 produces switching signal V _PWMTo transistor 20, be used for switching transformer 10.

See also shown in Figure 2ly, the signal waveform of existing known switch regulator illustrated in fig. 1 is described.Because switching signal V _PWMBe high potential (logic-high), can corresponding generation primary side switch current I _PPrimary side switch current I _PPeak I _PIBe given by the following formula:

${\mathrm{<figure-callout\; id="1"\; label="I\; P"\; filenames="C20061000835900211.png"\; state="\{\{state\}\}">I</figure-callout>}}_P=\frac{V_{\mathrm{IN}}}{L_P}\&times;T_{\mathrm{ON}}---\left(1\right)$

Wherein, V _INBe the input voltage that is applied to transformer 10, L _PBe a winding N of transformer 10 _PInductance value, and T _ONBe switching signal V _PWMON time.

In case switching signal V _PWMDrop to electronegative potential (logic-low), the energy that is stored in the transformer 10 will be sent to the secondary side of transformer 10, and arrive the output of switch regulator via rectifier 40.Correspondingly produce secondary side switch current I _SSecondary side switch current I _SPeak I _S1By following equation expression:

$I_{\mathrm{<figure-callout\; id="1"\; label="S"\; filenames="C20061000835900211.png"\; state="\{\{state\}\}">S</figure-callout>}1}=\frac{(V_O+V_F)}{L_S}\&times;T_{\mathrm{DS}}---\left(2\right)$

Wherein, V _OBe the output voltage of switch regulator, V _FBe the forward voltage drop of rectifier 40, and L _SBe the secondary winding N of transformer 10 _SInductance value, and T _DSBe secondary side switch current I _sDischarge time.

Simultaneously, the auxiliary winding N of transformer 10 _AThe place produces reflected signal V _AUXDescribed reflected signal V _AUXBe given by the following formula:

$V_{\mathrm{AUX}}=\frac{T_{\mathrm{NA}}}{T_{\mathrm{NS}}}\&times;(V_O+V_F)---\left(3\right)$

Wherein, T _NAAnd T _NSBe respectively the auxiliary winding N of transformer 10 _AWith secondary winding N _SUmber of turn.

As secondary side switch current I _SWhen reducing to zero, reflected signal V _AUXBegin to reduce.This energy that also demonstrates transformer 10 discharges this moment fully.Therefore, as shown in Figure 2, from switching signal V _PWMThe drop edge to reflected signal V _AUXT discharge time in the point measurement equation (2) that begins to descend _DSSecondary side switch current I _SBy primary side switch current I _PDetermine with the umber of turn of transformer 10.Secondary side switch current I _SBy following equation expression:

$I_S=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\&times;I_P---\left(4\right)$

Wherein, T _NPBe a winding N of transformer 10 _PUmber of turn.

Please consult shown in Figure 1ly again, control circuit 70 comprises power end VCC and the earth terminal GND that is used to receive electric power.One voltage divider is connected the auxiliary winding N of transformer 10 _AAnd between the grounded reference potential, and voltage divider is formed by resistor 50 and resistor 51.One test side DET of control circuit 70 is connected to the junction point of resistor 50 and resistor 51.The voltage V that DET place, test side produces _DETBe given by the following formula:

$V_{\mathrm{DET}}=\frac{R_{51}}{R_{50}+R_{51}}\&times;V_{\mathrm{AUX}}---\left(5\right)$

Wherein, R ₅₀And R ₅₁It is the resistance value of resistor 50 and 51.

By rectifier 60, the capacitor 65 signal V that further is reflected _AUXCharging thinks that control circuit 70 provides electric power.Current sensing resistor 30 is a current sensing elements.Current sensing resistor 30 is connected to grounded reference potential from the source electrode of transistor 20, with primary side switch current I _PConvert current sensing signal V to _CSThe induction end CS of control circuit 70 is connected to current sensing resistor 30, to detect current sensing signal V _CS

The output OUT of control circuit 70 produces switching signal V _PWMCome switching transformer 10.Voltage compensation end COMV is connected to first compensating network, is used for the frequency compensation of first error amplifier.First compensating network can be one to be connected to the capacitor of grounded reference potential, such as capacitor 31.Current compensation end COMI has second compensating network, is used for the frequency compensation to second error amplifier.Second compensating network also can be one to be connected to the capacitor of grounded reference potential, such as capacitor 32.End COMR able to programme has the resistor 33 that is connected to ground, with according to output current I _OFor the voltage feedback loop of control circuit 70 is adjusted reference signal V _REFReference signal V _REFAdjustment be to compensate the pressure drop of output cable 46, thereby realize load regulation preferably.

See also shown in Figure 3ly, the control circuit 70 according to one embodiment of the invention has been described.First circuit (V-LOOP) 100 passes through voltage V _DETCarry out multiple sampling and produce the first signal V _VWith clock signal S _DSClock signal S _DSExpression secondary side switch current I _ST discharge time _DSSecond circuit (I-LOOP) 300 is by measuring current sensing signal V _CSProduce current waveform signal V _WOscillator (OSC) 200 produces oscillator signal PLS to be used to determine switching signal V _PWMSwitching frequency.Tertiary circuit (π) 400 is by integration current waveform signal V _WWith clock signal S _DSProduce secondary signal V _I Operational amplifier 71 and reference signal V _REFForm first error amplifier, to be used to amplify the first signal V _VAnd provide first feedback loop circuitry for output voltage control.Operational amplifier 72 and reference signal V _REF2Form second error amplifier, to be used to amplify secondary signal V _IAnd provide second feedback loop circuitry for output current control.Adjust circuit (ADJ) 700 and be coupled to end COMR able to programme, with according to the first reference signal V _REF1With secondary signal V _IAdjust reference signal V _REFPulse-width modulation (PWM) circuit 500 and comparator 73,75 form control switching circuit, to produce switching signal V _PWM, and control switching signal V according to the output of first error amplifier and second error amplifier _PWMPulsewidth. Operational amplifier 71 and 72 all has mutual conductance (trans-conductance) output.The output of operational amplifier 71 is connected to the positive input terminal of voltage compensation end COMV and comparator 73.The output of operational amplifier 72 is connected to the positive input terminal of current compensation end COMI and comparator 75.The negative input end of comparator 73 is connected to the output of adder 600.The negative input end of comparator 75 is supplied with ramp signal (ramp signal) RMP that produces from oscillator 200.

Adder 600 is by making current sensing signal V _CSProduce slope signal (slope signal) V in the Calais mutually with ramp signal RMP _SLPThe positive input terminal of comparator 74 is supplied with reference signal V _REF3The negative input end of comparator 74 is connected to induction end CS, thus (cycle-by-cycle) electric current of property performance period restriction.Three outputs of NAND door 79 are connected respectively to the output of comparator 73,74 and 75.Reset signal (reset signal) RST is produced by the output of NAND door 79.Reset signal RST is fed to pwm circuit 500, to be used to control switching signal V _PWMDuty cycle (duty cycle).

To primary side switch current I _PDetect switching signal V _PWMCarry out pulse-width modulation and form current control loop, it is according to reference signal V _REF2And control primary side switch current I _PAmplitude (magnitude).Shown in equation (4), secondary side switch current I _SWith primary side switch current I _PProportional.According to the signal waveform of Fig. 2, the output current I of switch regulator _OBe secondary side switch current I _SMean value.It is by following equation expression:

$I_O=I_S\&times;\frac{T_{\mathrm{DS}}}{2T}---\left(6\right)$

Thus, the output current I of switch regulator _ORegulated.

Second circuit 300 detects current sensing signal V _CS, and produce current waveform signal V _W Tertiary circuit 400 is by integration current waveform signal V _WWith T discharge time _DSAnd then generation secondary signal V _ISo secondary signal V _IBe expressed as following formula:

$V_I=\frac{V_W}{2}\&times;\frac{T_{\mathrm{DS}}}{T_I}---\left(7\right)$

Wherein, current waveform signal V _WBy following equation expression:

$V_W=\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\&times;R_S\&times;I_S---\left(8\right)$

T wherein _IIt is the time constant of tertiary circuit 400.

From equation (6)-(8) as seen, secondary signal is expressed as follows again:

$V_I=\frac{T}{T_I}\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\&times;R_S\&times;I_O---\left(9\right)$

As seen secondary signal V _IOutput current I with switch regulator _OProportional.Secondary signal V _IWith output current I _OIncrease and increase.Yet, secondary signal V _IThe adjusting of maximum by current control loop be limited to reference signal V _REF2Value.Under the FEEDBACK CONTROL of current control loop, maximum output current I _O(max) be given by the following formula:

$I_{O\left(\max \right)}=\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\&times;\frac{G_A\&times;G_{\mathrm{SW}}\&times;V_{\mathrm{REF}2}}{1+(G_A\&times;G_{\mathrm{SW}}\&times;\frac{R_S}{K})}---\left(10\right)$

Wherein K equals T _IThe constant of/T, G _ABe the gain of second error amplifier, and G _SWIt is the gain of commutation circuit.

The very high (G of loop gain (loop gain) when current control loop _A* G _SW＞＞1), maximum output current I _O(max) can briefly be defined as following formula:

$I_{O\left(\max \right)}=K\&times;\frac{T_{\mathrm{NP}}}{T_{\mathrm{NS}}}\&times;\frac{V_{\mathrm{REF}2}}{R_S}---\left(11\right)$

Thus, according to reference signal V _REF2And with the maximum output current I of switch regulator _O(max) be adjusted to constant current.

In addition, to reflected signal V _AUXBe sampled to switching signal V _PWMCarry out pulse-width modulation and form voltage control loop, it is according to reference signal V _REFAnd control reflected signal V _AUXAmplitude.Shown in equation (3), reflected signal V _AUXWith output voltage V _OProportional.Reflected signal V _AUXAnd then be attenuated to voltage V shown in equation (5) _DET First circuit 100 passes through voltage V _DETCarry out multiple sampling and produce the first signal V _VAccording to reference signal V _RETValue, control the first signal V by the adjusting of voltage control loop _VValue.First error amplifier and commutation circuit provide the loop gain of voltage control loop.Therefore, output voltage V _OBriefly be defined as following formula:

$V_O=(\frac{R_{50}+R_{51}}{R_{50}}\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NA}}}\&times;V_{\mathrm{REF}})-V_F---\left(12\right)$

100 couples of reflected signal V of first circuit _AUXCarry out multiple sampling.At secondary side switch current I _SReduced to before zero, immediately voltage is taken a sample and measure.Therefore, secondary side switch current I _SVariation do not influence the forward voltage drop V of rectifier 40 _FValue.Yet, as output current I _ODuring variation, the pressure drop of output cable 46 changes thereupon.The formation of adjusting circuit 700 is the pressure drop in order to compensation output cable 46.Resistor 33 is used for the slope of programming, with according to secondary signal V _IVariation and determine reference signal V _REFVariation.Therefore, pressure drop is able to and output current I _OCompensation pro rata.Use the resistor 33 of different value, compensating action can be multiple output cable 46 and programmes.

See also shown in Figure 4ly, first circuit 100 according to an embodiment of the invention has been described.Sampling pulse generator 190 produces sample-pulse signal to carry out multiple sampling.Critical voltage 156 and reflected signal V _AUXProduced current potential translation reflected signal (level-shift reflected signal) mutually.First signal generator comprises counter 171 and AND door 165166, is used to produce sampled signal V _SP1V _SPNThe secondary signal generator comprises d type flip flop (flip-flop) 170, NAND door 163, AND door 164 and comparator 155, is used to produce clock signal S _DSTime delay circuit comprises inverter 162, current source 180, transistor 181 and capacitor 182, be used for when switching signal is disabled, producing one time of delay T _dThe input of inverter 161 is supplied with switching signal V _PWMThe output of inverter 161 is connected to the input of inverter 162, the first input end of AND door 164 and the input end of clock (clock-input) of d type flip flop 170.Signal opening/closing (on/off) transistor 181 of the output of inverter 162.Capacitor 182 is connected in parallel with transistor 181.Applying current source 180 comes to capacitor 182 chargings.Therefore, T time of delay of the capacitance of the electric current of current source 180 and capacitor 182 decision time delay circuit _dOn capacitor 182, obtain the output of time delay circuit.The D input of d type flip flop 170 is by supply voltage V _CCMove high potential to.The output of d type flip flop 170 is connected to second input of AND door 164.AND door 164 output timing signal S _DSTherefore as switching signal V _PWMWhen disabled, clock signal S _DSEnable.The output of NAND door 163 is connected to the RESET input of d type flip flop 170.Two inputs of NAND door 163 are connected respectively to the output of time delay circuit and the output of comparator 155.The negative input end of comparator 155 is supplied with current potential translation reflected signal.The positive input terminal of comparator 155 is supplied with sustaining voltage V _HDTherefore, at T time of delay _dAfter, in case current potential translation reflected signal is lower than sustaining voltage V _HD, clock signal S _DSJust disabled.In addition, as long as switching signal V _PWMBe activated clock signal S _DSAlso disabled.

The 3rd input supply sample-pulse signal of counter 171 and AND door 165166.The output of counter 171 is connected respectively to second input of AND door 165166.The first input end of AND door 165166 is supplied with clock signal S _DSThe four-input terminal of AND door 165166 is connected to the output of time delay circuit.Therefore, produce sampled signal V according to sample-pulse signal _SP1V _SPNIn addition, at clock signal S _DSThe cycle of enabling this section during alternately produce sampled signal V _SP1V _SPNYet, time of delay T _dBe at clock signal S _DSBeginning the time introduce, to suppress sampled signal V _SP1V _SPNSo sampled signal V _SP1V _SPNAt T time of delay _dCycle this section during disabled.

Via test side DET and voltage divider, sampled signal V _SP1V _SPNBe used in regular turn to reflected signal V _AUXTake a sample.Sampled signal V _SP1V _SPNControl switch 121122 is to obtain the sustaining voltage on the capacitor 110111 respectively.Switch 123124 is connected in parallel with capacitor 110111, to be used for capacitor 110111 discharges.Buffer circuit comprises operational amplifier 150151, diode 130131 and current source 135, is used to produce sustaining voltage V _HDThe positive input terminal of operational amplifier 150151 is connected respectively to capacitor 110111.The negative input end of operational amplifier 150151 is connected to the output of buffer circuit.Diode 130131 is connected to the output of buffer circuit from the output of operational amplifier 150151.So sustaining voltage V _HDObtain from the high voltage of sustaining voltage.Current source 135 is used for stopping.Switch 125 is periodically with sustaining voltage V _HDBe transmitted to capacitor 115, to produce the first signal V _VVia oscillator signal PLS off/on switches 125.At T time of delay _dAfter, sampled signal V _SP1V _SPNBegin to produce sustaining voltage.Reflected signal V _AUXSurging disturb (spikeinterference) to be eliminated.As switching signal V _PWMWhen disabled and transistor 20 is closed, reflected signal V _AUXSurging disturb and may occur.

As secondary side switch current I _SWhen reducing to zero, reflected signal V _AUXBegin to reduce.Comparator 155 will detect aforesaid reflected signal V _AUXWith forbidding clock signal S _DSTherefore, clock signal S _DSPulsewidth and secondary side switch current I _ST discharge time _DSBe associated.Simultaneously, sampled signal V _SP1V _SPNDisabled, and as clock signal S _DSStop multiple sampling when disabled.At this moment, the sustaining voltage V of the output of buffer circuit generation _HDTherefore with reflected signal V _AUXBe associated, in case secondary side switch current I wherein _SReduce to zero just to reflected signal V _AUXTake a sample.Sustaining voltage V _HDObtain from the high voltage of sustaining voltage, as reflected signal V _AUXWhen beginning to reduce, it will ignore the voltage of being taken a sample.

See also shown in Figure 5ly, oscillator 200 according to an embodiment of the invention has been described.First voltage is formed by operational amplifier 201, resistor 210, transistor 250 to current converter (first V-to-I converter).First voltage to current converter according to reference signal V _RAnd generation reference current I ₂₅₀Current mirror is formed by several transistors, and for example transistor 251,252,253,254 and 255, are used for according to reference current I ₂₅₀Produce oscillator charging current I ₂₅₃With oscillator discharge current I ₂₅₅The drain electrode of transistor 253 (drain) produces oscillator charging current I ₂₅₃The drain electrode of transistor 255 produces oscillator discharge current I ₂₅₅Switch 230 is connected between the drain electrode and capacitor 215 of transistor 253.Ramp signal RMP obtains on capacitor 215.The positive input terminal of comparator 205 is connected to capacitor 215.Comparator 205 outputting oscillation signal PLS.Switching signal V _PWMSwitching frequency determine by oscillator signal PLS.First end of switch 232 is supplied with high critical voltage V _HFirst end of switch 233 is supplied with low critical voltage V _LSecond end of switch 232 and second end of switch 233 all are connected to the negative input end of comparator 205.The input of inverter 260 is connected to the output of comparator 205, to produce counter-rotating oscillator signal/PLS.Switch 231 and switch 233 are by oscillator signal PLS opening/closing.Switch 230 and switch 232 are by counter-rotating oscillator signal/PLS opening/closing.The resistance value R of resistor 210 ₂₁₀Capacitance C with capacitor 215 ₂₁₅Switching cycle T with the decision switching frequency:

$T=\frac{{\mathrm{<figure-callout\; id="215"\; label="C"\; filenames="C20061000835900221.png"\; state="\{\{state\}\}">C</figure-callout>}}_{215}\&times;V_{\mathrm{OSC}}}{V_R/{\mathrm{<figure-callout\; id="210"\; label="R"\; filenames="C20061000835900221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{210}}={\mathrm{<figure-callout\; id="210"\; label="R"\; filenames="C20061000835900221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{210}\&times;{\mathrm{<figure-callout\; id="215"\; label="C"\; filenames="C20061000835900221.png"\; state="\{\{state\}\}">C</figure-callout>}}_{215}\&times;\frac{V_{\mathrm{OSC}}}{V_R}---\left(13\right)$

V wherein _OSC=VH-VL.

See also shown in Figure 6ly, second circuit 300 according to an embodiment of the invention is described.The 4th circuit comprises comparator 310, current source 320, switch 330,340 and capacitor 361.To current sensing signal V _CSPeak value take a sample, to produce the 4th signal.The positive input terminal of comparator 310 is supplied with current sensing signal V _CSThe negative input end of comparator 310 is connected to capacitor 361.Switch 330 is connected between current source 320 and the capacitor 361.Switch 330 is by the signal opening/closing of the output of comparator 310.Switch 340 is connected in parallel with capacitor 361, so that capacitor 361 is discharged.Switch 350 periodically is transmitted to capacitor 362 with the 4th signal, to produce current waveform signal V _WSwitch 350 is by oscillator signal PLS opening/closing.

See also shown in Figure 7ly, tertiary circuit 400 according to an embodiment of the invention has been described.Second voltage comprises operational amplifier 410, resistor 450 and transistor 420,421,422 to current converter (second V-to-I converter).The positive input terminal of operational amplifier 410 is supplied with current waveform signal V _WThe negative input end of operational amplifier 410 is connected to resistor 450.The gate pole of the signal driving transistors 420 of the output of operational amplifier 410.The source-coupled of transistor 420 is to resistor 450.Via the drain electrode of transistor 420, electric current I 420 by second voltage to current converter according to current waveform signal V _WAnd produce.Transistor 421 and 422 formation ratios are 2: 1 current mirror.Via the drain electrode of transistor 422, electric current I ₄₂₀Driven current mirror is to produce programmable charge current I _PRGProgrammable charge current I _PRGBy following equation expression:

$I_{\mathrm{PRG}}=\frac{1}{{\mathrm{<figure-callout\; id="450"\; label="R"\; filenames="C20061000835900241.png"\; state="\{\{state\}\}">R</figure-callout>}}_{450}}\&times;\frac{V_W}{2}---\left(14\right)$

R wherein ₄₅₀It is the resistance value of resistor 450.

Capacitor 471 is used for producing integrated signal.Switch 460 is connected between the drain electrode and capacitor 471 of transistor 422.Switch 460 is by clock signal S _DSOpening/closing.Switch 462 is connected in parallel with capacitor 471, so that capacitor 471 is discharged.Switch 461 periodically is transmitted to integrated signal capacitor 472, to produce secondary signal V _ISwitch 461 is by oscillator signal PLS opening/closing.So secondary signal V _IOn capacitor 472, obtain, as follows:

$V_I=\frac{1}{{\mathrm{<figure-callout\; id="450"\; label="R"\; filenames="C20061000835900241.png"\; state="\{\{state\}\}">R</figure-callout>}}_{450}\&times;{\mathrm{<figure-callout\; id="471"\; label="C"\; filenames="C20061000835900241.png"\; state="\{\{state\}\}">C</figure-callout>}}_{471}}\&times;\frac{V_W}{2}\&times;T_{\mathrm{DS}}---\left(15\right)$

One embodiment of the invention illustrated according to Fig. 4～7, secondary signal V _ISecondary side switch current I with switch regulator _S, output current I _OBe associated.Therefore, equation (9) is expressed as follows again:

$V_I=m\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\&times;R_S\&times;I_O---\left(16\right)$

Wherein m is a constant, and it is determined by following formula:

$m=\frac{{\mathrm{<figure-callout\; id="210"\; label="R"\; filenames="C20061000835900221.png"\; state="\{\{state\}\}">R</figure-callout>}}_{210}\&times;C_{215}}{{\mathrm{<figure-callout\; id="450"\; label="R"\; filenames="C20061000835900241.png"\; state="\{\{state\}\}">R</figure-callout>}}_{450}\&times;{\mathrm{<figure-callout\; id="471"\; label="C"\; filenames="C20061000835900241.png"\; state="\{\{state\}\}">C</figure-callout>}}_{471}}\&times;\frac{V_{\mathrm{OSC}}}{V_R}---\left(17\right)$

The resistance value R of resistor 450 ₄₅₀Resistance value R with resistor 210 ₂₁₀Be associated.The capacitance C of capacitor 471 ₄₇₁Capacitance C with capacitor 215 ₂₁₅Be associated.Therefore, secondary signal V _IOutput current I with switch regulator _OProportional.

See also shown in Figure 8ly, the circuit diagram of pwm circuit 500 according to an embodiment of the invention has been described.Pwm circuit 500 comprises NAND door 511, d type flip flop 515, AND door 519, blanking circuit (blanking circuit) 520 and inverter 512,518.The D input of d type flip flop 515 is by supply voltage V _CCMove high potential to.The input of inverter 512 is driven by oscillator signal PLS.The output of inverter 512 is connected to the input end of clock of d type flip flop 515, to enable switching signal V _PWMThe output of d type flip flop 515 is connected to the first input end of AND door 519.Second input of AND door 519 is coupled to the output of inverter 512.AND door 519 output switching signal V _PWM, with switching transformer 10.The RESET input of d type flip flop 515 is connected to the output of NAND door 511.The first input end of NAND door 511 is supplied with reset signal RST, to be used for periodically forbidding switching signal V _PWMSecond input of NAND door 511 is connected to the output of blanking circuit 520, to guarantee as switching signal V _PWMSwitching signal V when being activated _PWMMinimum ON time (minimum on-time).Switching signal V _PWMMinimum ON time guarantee T discharge time _DSMinimum value, it is guaranteed the reflected signal V in first circuit 100 _AUXCarry out suitable multiple sampling.Discharge time T _DSWith switching signal V _PWMON time be associated.With reference to equation (1), (2) and (4), and the secondary side inductance value L shown in the equation (18) _S, discharge time T _DSExpress by following equation (19):

L _s＝(T _NS/T _NP) ²×L _P --------------------------------(18)

$T_{\mathrm{DS}}=\left(\frac{V_{\mathrm{IN}}}{V_O+V_F}\right)\&times;\frac{T_{\mathrm{NS}}}{T_{\mathrm{NP}}}\&times;T_{\mathrm{ON}}---\left(19\right)$

T wherein _ONBe switching signal V _PWMON time.

The input of blanking circuit 520 is supplied with switching signal V _PWMAs switching signal V _PWMWhen being activated, blanking circuit 520 will produce blanking signal V _BLKSuppress resetting of d type flip flop 515.Blanking circuit 520 more comprises NAND door 523, current source 525, capacitor 527, transistor 526 and inverter 521,522.The first input end supply switching signal V of the input of inverter 521 and NAND door 523 _PWMApply current source 525 so that capacitor 527 is charged.Capacitor 527 is connected in parallel with transistor 526.Transistor 526 is by the signal opening/closing of the output of inverter 521.The input of inverter 522 is coupled to capacitor 527.The output of inverter 522 is connected to second input of NAND door 523.The output output blanking signal V of NAND door 523 _BLKBlanking signal V _BLKPulsewidth by the capacitance decision of the current value of current source 525 and capacitor 527.The input of inverter 518 is connected to the output of NAND door 523.The output of inverter 518 produces clear signal CLR with off/on switches 123,124,340 and 462.

See also shown in Figure 9ly, the circuit diagram of adder 600 according to an embodiment of the invention has been described.Tertiary voltage is formed by operational amplifier 610, transistor 620,621,622 and resistor 650 to current converter (third V-to-I converter), is used for producing electric current I 622 according to ramp signal RMP.The positive input terminal of operational amplifier 611 is supplied with current sensing signal V _CSThe negative input end and the output of operational amplifier 611 link together, so that operational amplifier 611 is as buffer.The drain electrode of transistor 622 is connected to the output of operational amplifier 611 via resistor 651.Slope signal V _SLPResult from drain electrode place of transistor 622.So slope signal V _SLPWith ramp signal RMP, current sensing signal V _CSBe associated.

See also shown in Figure 10ly, the circuit diagram of adjusting circuit 700 according to an embodiment of the invention is described.Voltage is formed by operational amplifier 710, transistor 711,714,715 and resistor 712 to current converter, is used for according to secondary signal V _IAnd the generation electric current I ₇₁₅The positive input terminal of operational amplifier 710 is supplied with secondary signal V _IElectric current I ₇₁₅Be output to end COMR able to programme.Electric current I ₇₁₅Produce voltage V in conjunction with resistor 33 _COMRAnd be connected to operational amplifier 720.Another voltage is formed by operational amplifier 720, transistor 721,724,725 and resistor 722 to current converter, is used for according to voltage V _COMRAnd produce electric current I in drain electrode place of transistor 725 ₇₂₅The negative input end and the output of operational amplifier 750 link together, so that operational amplifier 750 is as buffer.The positive input terminal of operational amplifier 750 is connected to reference signal V _REF1The drain electrode of transistor 725 is connected to the output of operational amplifier 750 via resistor 760.Reference signal V _REFResult from drain electrode place of transistor 725.Based on reference signal V _REF1, reference signal V _REFBy secondary signal V _IAdjust and by resistor 33 programmings.

The those skilled in the art should easily understand, and can make various modifications and variations to its structure under the situation that does not break away from category of the present invention and spirit.In view of mentioned above, wish that the present invention is encompassed in the interior modifications and variations of the present invention of scope of aforesaid right claim and its equivalent.

Claims (27)

1. the switch regulator of primary side control is characterized in that it comprises:

One transformer is used for energy is delivered to a secondary side from a primary side of described transformer;

One switches element, is used to switch described transformer; With

One control circuit, it is coupled to described transformer, is used for producing one and switches signal, in order to switching described switching device, and regulates the output of described switch regulator,

Wherein said control circuit comprises:

One first circuit, it is coupled to described transformer, and the reflected signal by measuring described transformer is producing one first signal and a clock signal, and wherein said clock signal is represented a discharge time of described transformer;

One second circuit and a tertiary circuit, it be used for producing a secondary signal, and wherein said current signal is represented a primary side switch current of described transformer by integration one current signal and described clock signal;

One first error amplifier receives one first reference signal, be used for producing one first feedback signal according to described first signal, and wherein said first reference signal increases according to the increase of described secondary signal;

One second error amplifier receives one second reference signal, is used for producing one second feedback signal according to described secondary signal; With

One switches control circuit, and it produces described switching signal according to described first feedback signal and described second feedback signal.

2. the switch regulator of primary side control according to claim 1 is characterized in that wherein said control circuit further comprises:

One power end and an earth terminal are used to receive electric power;

One test side is used for by a resistor of a voltage divider described first circuit being connected to described transformer;

One induction end is used for described second circuit is connected to a current sensing elements, and receiving described current signal, and described current sensing elements is used for described primary side switch current is converted to described current signal;

One output by described switching device, is used to produce described switching signal and switches described transformer;

One voltage compensation end, it is connected to one first compensating network, is used for described first error amplifier is carried out frequency compensation;

One current compensation end, it is connected to one second compensating network, is used for described second error amplifier is carried out frequency compensation; With

One end able to programme, it connects a resistor to a ground connection, and in order to determine a slope, wherein said slope represents that the variation of described first reference signal contrasts the variation of described secondary signal.

3. the switch regulator of primary side control according to claim 1 is characterized in that a time constant of wherein said tertiary circuit was associated with a switching cycle of described switching signal.

4. the switch regulator of primary side control according to claim 1 is characterized in that wherein said first circuit comprises:

One critical voltage, wherein said critical voltage add described reflected signal to produce a current potential translation reflected signal;

A plurality of capacitors;

One signal generator, it is used to produce sampled signal, wherein said sampled signal is used for described reflected signal is taken a sample, and produces sustaining voltage respectively on described capacitor, and produces described sampled signal in regular turn during one of described clock signal is enabled this section of cycle;

One buffer circuit, the high voltage of its sustaining voltage from the described capacitor produces an inhibit signal;

One first output capacitor is used for producing described first signal according to described inhibit signal; With

One secondary signal generator, it is used to produce described clock signal, wherein when described switch signal forbidden, enables described clock signal, and when described current potential translation reflected signal is lower than described inhibit signal, forbids described clock signal.

5. the switch regulator of primary side control according to claim 1, it is characterized in that wherein said first circuit carries out multiple sampling to described reflected signal, to produce described first signal, and just described reflected signal is taken a sample in case the switch current of described secondary side drops to zero, obtain described first signal behind the multiple sampling.

6. the switch regulator of primary side control according to claim 1 is characterized in that wherein said second circuit comprises:

One the 4th circuit, it produces one the 4th signal by the peak value of current signal is taken a sample;

One the 3rd capacitor, it keeps described the 4th signal;

One second output capacitor, it produces a current waveform signal; With

One switch, it is transmitted to described second output capacitor with described the 4th signal.

7. the switch regulator of primary side control according to claim 1 is characterized in that wherein said tertiary circuit comprises:

One voltage is to current converter, and it produces a charging current according to current waveform signal;

One sequential capacitor, it is coupled to described charging current via one first switch, to produce an integrated signal according to described clock signal;

One second switch, itself and described sequential capacitor are connected in parallel, so that described sequential capacitor is discharged;

One the 3rd output capacitor, it produces described secondary signal; With

One the 3rd switch, it is transmitted to described the 3rd output capacitor with described integrated signal.

8. the switch regulator of primary side control according to claim 1, it is characterized in that wherein when described switching signal is enabled, described switching signal has a minimum ON time, and the minimum value that it has further guaranteed described discharge time is used for described reflected signal is carried out multiple sampling.

9. switch regulator is characterized in that it comprises:

One transformer is used for energy is delivered to a secondary side from a primary side of described transformer;

One switches element, is used to switch described transformer; With

One control circuit, it is coupled to described transformer, is used for producing one and switches signal, in order to switching described switching device, and regulates the output of described switch regulator,

Wherein said control circuit comprises:

One first circuit, it is coupled to described transformer, produces one first signal and a clock signal by a reflected signal of measuring described transformer, and described clock signal is represented a discharge time of described transformer;

One second circuit, it produces a secondary signal by integration one current signal and described clock signal, and described current signal is represented a primary side switch current of described transformer;

One first feedback circuit is used for producing one first feedback signal according to described first signal;

One second feedback circuit is used for producing one second feedback signal according to described secondary signal; With

One switches control circuit, and it produces described switching signal according to described first feedback signal and described second feedback signal.

10. switch regulator according to claim 9, it is characterized in that wherein said first feedback circuit further comprises one first reference signal, it produces described first feedback signal according to described first signal and described first reference signal, and described first reference signal changes according to the variation of described secondary signal.

11. switch regulator according to claim 9 is characterized in that wherein said control circuit further comprises:

One power end and an earth terminal are used to receive electric power;

One test side is used for described first which couple to described transformer;

One induction end is used for described second circuit is coupled to a current sensing elements, and to receive described current signal, wherein said current sensing elements is used for described primary side switch current is converted to described current signal;

One output by described switching device, is used to produce described switching signal to switch described transformer;

One voltage compensation end is used for the frequency compensation of described first feedback circuit; With

One current compensation end is used for the frequency compensation of described second feedback circuit.

12. switch regulator according to claim 9 is characterized in that wherein said first circuit comprises:

One critical voltage, wherein said critical voltage add described reflected signal to produce a current potential translation reflected signal;

A plurality of capacitors;

One signal generator, it produces sampled signal described reflected signal is taken a sample and keep described reflected signal in described capacitor, wherein produces sustaining voltage respectively on described capacitor, and produces sampled signal according to enabling of described clock signal;

One buffer circuit, it produces described first signal according to described sustaining voltage;

One secondary signal generator, it produces described clock signal according to sustaining voltage and described current potential translation reflected signal, wherein when described switch signal forbidden, enables described clock signal, and when described current potential translation reflected signal is lower than described sustaining voltage, forbid described clock signal.

13. switch regulator according to claim 9, it is characterized in that wherein said first circuit carries out multiple sampling to described reflected signal, to produce described first signal, and drop to zero at the switch current of described secondary side and just described reflected signal is taken a sample, described first signal of acquisition behind the multiple sampling.

14. switch regulator according to claim 9 is characterized in that wherein said second circuit comprises:

One current generator, it produces a charging current by described current signal is taken a sample; With

One capacitor, it is coupled to described charging current, is used for producing described secondary signal according to described clock signal.

15. switch regulator according to claim 9, it is characterized in that wherein when described switching signal is enabled, described switching signal has a minimum ON time, and the minimum value that it has further guaranteed described discharge time is used for described reflected signal is carried out multiple sampling.

16. a switching power converter is characterized in that it comprises:

One transformer is used for described energy is delivered to a secondary side from a primary side of described transformer;

One switches element, is used to switch described transformer; With

One control circuit, it is coupled to described transformer, is used to produce one and switches signal, switching described switching device, and regulates the output of described switch regulator,

Wherein said control circuit comprises:

One first circuit, it is coupled to described transformer, is used for producing one first signal by a reflected signal of measuring described transformer;

One second circuit, it produces a secondary signal according to a current signal, and wherein said current signal is represented a primary side switch current of described transformer;

One first feedback circuit, it produces one first feedback signal according to described first signal;

One second feedback circuit, it produces one second feedback signal according to described secondary signal; With

One switches control circuit, and it produces described switching signal according to described first feedback signal and described second feedback signal.

17. switching power converter according to claim 16, it is characterized in that wherein said first feedback circuit further comprises one first reference signal, be used for producing described first feedback signal, and described first reference signal changes according to the variation of described secondary signal according to described first signal.

18. switching power converter according to claim 16 is characterized in that wherein said control circuit further comprises:

One power end and an earth terminal are used to receive electric power;

One test side is used for by a resistor of a voltage divider described first circuit being connected to described transformer;

One induction end is used for described second circuit is connected to a current sensing elements, and to receive described current signal, wherein said current sensing elements is used for described primary side switch current is converted to described current signal;

One output by described switching device, is used to produce described switching signal to switch described transformer;

One first compensation is held, and is used for the frequency compensation of described first feedback circuit; With

One second compensation is held, and is used for the frequency compensation of described second feedback circuit.

19. switching power converter according to claim 16 is characterized in that wherein said first circuit comprises:

A plurality of capacitors;

One signal generator, it produces sampled signal described reflected signal is taken a sample and keep described reflected signal in described capacitor, wherein produces sustaining voltage respectively on described capacitor, and produces sampled signal according to enabling of a clock signal;

One buffer circuit, it produces described first signal according to described sustaining voltage; With

One secondary signal generator, it produces described clock signal according to sustaining voltage, wherein when described switch signal forbidden, enables described clock signal, and when described reflected signal is lower than described inhibit signal, forbids described clock signal.

20. switching power converter according to claim 16, it is characterized in that wherein said first circuit carries out multiple sampling to described reflected signal, to produce described first signal, and just described reflected signal is taken a sample in case the switch current of described secondary side drops to zero, obtain described first signal behind the multiple sampling.

21. switching power converter according to claim 16, it is characterized in that wherein when described switching signal is enabled, described switching signal has a minimum ON time, and the minimum value that it has further guaranteed discharge time is used for described reflected signal is carried out multiple sampling.

22. a switch regulator is characterized in that it comprises:

One transformer is used for energy is delivered to a secondary side from a primary side of described transformer;

One switches element, is used to switch described transformer; With

One control circuit, it is coupled to described transformer, and be used to produce one and switch signal switching described switching device and to regulate the output of described switch regulator,

Wherein said control circuit comprises:

One first circuit, it is coupled to described transformer, to produce one first signal by a reflected signal of measuring described transformer;

One second circuit, it produces a secondary signal by measuring a current signal, and wherein said current signal is associated with the output current of described switch regulator;

One feedback circuit, it comprises a reference signal, be used for producing a feedback signal according to described first signal and described reference signal, and described reference signal changes according to described secondary signal; With

One switches control circuit, and it produces described switching signal according to described feedback signal.

23. switch regulator according to claim 22 is characterized in that wherein said first circuit comprises:

A plurality of capacitors;

One signal generator, it produces sampled signal, in order to described reflected signal is taken a sample and keep described reflected signal in described capacitor, wherein produces sustaining voltage respectively on described capacitor, and produces sampled signal according to enabling of a clock signal;

One buffer circuit, it produces described first signal according to described sustaining voltage; With

One secondary signal generator, it produces described clock signal according to sustaining voltage, wherein when described switch signal forbidden, enables described clock signal; When described reflected signal is lower than described inhibit signal, forbid described clock signal.

24. switch regulator according to claim 22, it is characterized in that wherein said first circuit carries out multiple sampling to described reflected signal, to produce described first signal, and just described reflected signal is taken a sample in case the switch current of described secondary side drops to zero, obtain described first signal behind the multiple sampling.

25. switch regulator according to claim 22 is characterized in that wherein said second circuit comprises:

One current generator, it produces a charging current according to described current signal; With

One capacitor, it is coupled to described charging current, is used for producing described secondary signal according to a clock signal.

26. switch regulator according to claim 22, it is characterized in that wherein when described switching signal is enabled, described switching signal has a minimum ON time, and the minimum value that it has further guaranteed discharge time is used for described reflected signal is carried out multiple sampling.

27. a switch regulator is characterized in that it comprises:

One transformer is used for energy is delivered to a secondary side from a primary side of described transformer;

One switches element, is used to switch described transformer; With

One control circuit, it is coupled to described transformer, and be used to produce a switching signal and switch described switching device, and regulate the output of described switch regulator,

Wherein said control circuit comprises:

One first circuit, it is coupled to described transformer, is used for producing one first signal by a reflected signal of measuring described transformer;

One second circuit, it produces a secondary signal by measuring a current signal, and wherein said current signal is associated with the output current of described switch regulator;

One feedback circuit, it produces a feedback signal according to described first signal, and described first signal changes according to described secondary signal; With

One switches control circuit, and it produces described switching signal according to described feedback signal.

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