CN100559414C - Cluster control system and method that the multidimensional synchronous high-speed is measured - Google Patents
Cluster control system and method that the multidimensional synchronous high-speed is measured Download PDFInfo
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Abstract
The invention provides the cluster control system that a kind of multidimensional synchronous high-speed is measured, this system comprises measurement data acquisition synchronized clusters controller and measurement data sampling and caching system, and this measurement data acquisition synchronized clusters controller comprises processor, SDRAM storer, direct memory access (DMA) control register group, direct memory access (DMA) controller, interruptable controller, double-port RAM, synchronous sequence controller, measuring system isochronous controller, data bus and address bus; This measurement data sampling comprises data acquisition controller, signal condition and sampling integrated circuit board group, sampling trigger signal and data transmission approach, synchronous bus with caching system.Compared with prior art, technical scheme of the present invention is applied to a plurality of measurement subsystems with the multidimensional synchronous bus, obtained to be easier to realize synchronous good result than the past measurement system, improving the real-time and the high precision of measuring system, is an important raising to the precise machining equipment system performance.
Description
Technical field
The present invention relates to a kind of measuring method, specifically, relate to cluster control system and method that a kind of multidimensional synchronous high-speed is measured.
Background technology
Along with the development of modern industry manufacturing technology and infotech, realize that to using the close measuring system of high speed and super precision the requirement of High Accuracy Control further improves.And, also provide the application platform of the close control of more realization high speed and super precision along with the raising of performance of integrated circuits.System equipment uses distributed control mode and framework to realize multiple spot control more now, this has formed restriction to high speed data transfer and rapid movement control survey, thereby the directly raising of the measurement sample frequency of restriction system has significant impact for the characteristic performance and the production capacity that improve equipment.And synchronous cluster control method and the system of employing multi-channel data high speed acquisition, let us obtains more control informations quickly, make discrete message that we measure more near actual information, make that the control response of system equipment is faster, the precision of control is higher.
Disclosed method is in No. the 60153245th, the U.S. Patent application, after cycle length, calculates communication cycles periodicity by the computation period number at known synchronous clock, obtains synchronous absolute time, thus realize a plurality of communication terminal users synchronously.The defective of this method is, the synchronous clock that need know synchronous issue one side could pass through to calculate the communication cycles periodicity after cycle length, calculates issue one side's the absolute synchronization time synchronously, obtain user one side's local synchronous absolute time again, realize between a plurality of users synchronously; Its limitation is to issue synchronously a side can not adjust and control synchronous sequence relation between a plurality of users, can only passive reception issue one side's synchro control synchronously.
In No. the 7054336th, U.S. Patent application, the programmable synchronous of multidimensional digital frame structure has been described, its frame structure has comprised frame head, frame load and preposition error-checking, and it allows the load variable size of frame synchronization, and this method is mainly used in and realizes the data synchronization transport communication.But its defective is that definition super frame structure defines the passage that synchronous transmission is communicated by letter earlier, just can carry out the transmission of Frame, and can not carry out data transmission to a plurality of frame take over partys simultaneously, is the mode of point-to-point broadcasting.It is the definition of utilization multidimensional frame structure, realizing selecting transmission objectives and transmission mode, is a kind of serial one point selection broadcasting, the data transmission communication means of multiple spot selective reception, can not carry out the multi-channel parallel Data Transmission Controlling, limit the raising of the efficient of data transmission.
And in No. the 200510023859.5th, Chinese patent application, what it adopted is some broadcasting, multiple spot discharges data, multiple spot is accepted the method for data, realized the synchronized broadcast data acquisition, when a large amount of passages of needs are gathered,, limited the raising of the frequency of measurement data acquisition transmission because this broadcasting method is the synchronous broadcasting method of a kind of multistage serial.
Summary of the invention
The object of the present invention is to provide a kind of measuring method, specifically, relate to cluster control system and method that a kind of multidimensional synchronous high-speed is measured.
For achieving the above object, the invention provides the cluster control system that a kind of multidimensional synchronous high-speed is measured, this system comprises measurement data acquisition synchronized clusters controller and measurement data sampling and caching system, and this measurement data acquisition synchronized clusters controller comprises processor, SDRAM storer, direct memory access (DMA) control register group, direct memory access (DMA) controller, interruptable controller, double-port RAM, synchronous sequence controller, measuring system isochronous controller, data bus and address bus; This measurement data sampling comprises data acquisition controller, signal condition and sampling integrated circuit board group, sampling trigger signal and data transmission approach, synchronous bus with caching system.During measurement, the parameter of the cluster control that described processor configuration multidimensional data passage high-speed synchronous is gathered, and by writing the cluster sampling trigger signal that described synchronous sequence controller sends synchro measure, then the data that collect are sent in the described double-port RAM, the pending data collection is finished, described double-port RAM forms look-at-me, described processor receives described look-at-me, start the direct memory access (DMA) data transmission, finish a synchronous acquisition group's acquisition controlling.
Compared with prior art, technical scheme of the present invention is applied to a plurality of measurement subsystems with the multidimensional synchronous bus, obtained to be easier to realize synchronous good result than the past measurement system, improving the real-time and the high precision of measuring system, is an important raising to the precise machining equipment system performance.
Description of drawings
To the description of the embodiment of the invention, can further understand purpose, specific structural features and the advantage of its invention by following in conjunction with its accompanying drawing.Wherein, accompanying drawing is:
Fig. 1 is the structured flowchart of the cluster control system of multidimensional synchronous high-speed measurement of the present invention.
Fig. 2 is the structured flowchart of data acquisition controller of the present invention.
Fig. 3 triggers the signal condition of sampling and the structured flowchart of sampling integrated circuit board for the present invention is unified
Fig. 4 is the signal condition of independent triggers sampling of the present invention and the structured flowchart of sampling integrated circuit board.
Fig. 5 triggers the signal condition of independent extended channel sampling and the structured flowchart of sampling integrated circuit board for the accurate multilevel delay control of the present invention.
Fig. 6 triggers the conditioning of time division multiplex extended channel sampling and the structured flowchart of sampling integrated circuit board for the accurate multilevel delay control of the present invention.
Fig. 7 is the sequential chart of the cluster control system of multidimensional synchronous high-speed measurement of the present invention.
Embodiment
As shown in Figure 1, the cluster control system of multidimensional synchronous high-speed measurement of the present invention mainly comprises two parts: measurement data acquisition synchronized clusters controller SCCAMD (Synchronization Cluster Controller ofAcquiring Measure Data) and measurement data sampling and caching system MDSBS (System ofSampling and Buffering Measure Data).
Wherein, measurement data acquisition synchronized clusters controller SCCAMD is by PROCESSOR processor 1, SDRAM (synchronous dynamic random) storer 2, direct memory access (DMA) DMA (Directive MemoryAccess) control register group 3, direct memory access (DMA) dma controller 30～3n, interruptable controller 4, double-port RAM DPRAM (Dual Port Random Access Memory) 40～4n, synchronous sequence controller STC, synchronous base controller group 7, isochronous controller SC (SynchronizationController) organizes 70～7n, data bus DB (Data Bus) 10, address bus AB (Address Bus) 11, synchronous bus SB (Synchronization Bus) 50～5n.
Wherein, synchronous bus SB comprises sync address bus SDB (Synchronization Data Bus) and synchronous data bus SAB (Synchronization Address Bus).Synchronous sequence controller STC (Synchronization Timing Controller) comprises SYN register group 60～6n, synchro control registers group 6.Measuring system isochronous controller MSSC (Measuring System SynchronizationController) comprises synchronous base controller group 7, isochronous controller group 70～7n and synchronous bus 50～5n.
The measurement data sampling is made up of data acquisition controller DAC (Data AcquiringController) 80～8n, signal condition and sampling integrated circuit board group GSCSB (Group of Signal Condition andSampling Boards) 900～90t...9n0～9nt, synchronous bus 50～5n and sampling trigger signal and data transmission approach TASD (Transmission Avenue of Signal and Data) etc. with caching system MDSBS.
Data acquisition controller DAC structure as shown in Figure 2.Sampling trigger signal and data transmission approach TASD can be electromagnetic transmission mode (comprise Optical Fiber Transmission mode and less radio-frequency transmission mode, their transmission protocol mode are identical); Signal condition can be one or more shown in Fig. 3 to Fig. 6 with sampling integrated circuit board (SCSB:Signal Condition and SamplingBoards) 900～90t...9n0～9nt, and next its structure will described in detail.
The PROCESSOR processor 1 of SCCAMD is used to dispose the parameter of the cluster control that multidimensional data passage high-speed synchronous gathers among Fig. 1.These parameter parts are placed among the synchronous sequence controller STC, and another part leaves in the DMA control register group 3.
As shown in Figure 2, data acquisition controller DAC is by synchronous bus SB (Synchronization Bus), synchronous bus interface SBI (Synchronization Bus Interface), synchro measure parameter transmit control device SCSMP (Sending Controller of Synchronization Measure Parameters), data acquisition buffer group FIFOBG (First input First Output Buffer Group), sample Data Receiving controller RCSD (Receiving Controller of Sample Data) and formations such as optical fiber and radio transceiver interface.In the synchro measure parameter transmit control device SCSMP of each data acquisition controller DAC an identical address is arranged, the local motor synchronizing measurement sampling that is used for enabling signal conditioning and sampling integrated circuit board SCSB triggers to be controlled.
As shown in Figure 3, the unified signal condition that triggers sampling can only be measured the unified sampling simultaneously of passage to each with sampling integrated circuit board SCSB.This signal condition is by optical fiber or radio transceiver interface with sampling integrated circuit board SCSB, the synchro measure parameter receives controller RCSMP (Receiving Controller of SynchronizationMeasure Parameters), signal condition controller SCC (Signal Conditioner Controller) 1～m, simulating signal controller ASC (Analog Signal Controller) 1～m, local motor synchronizing controller LSC (Local Self-synchronization Controller), analog to digital converter ADC (Analog to DigitalConverter) 1～m, delayer DY (Delayer), analog to digital conversion registers group ADCRG (Analog toDigital Converter Register Group) and sampled data send controller SCSD formations such as (SendingController of Sample Data).
As shown in Figure 4, the signal condition of independent triggers sampling can carry out the independent triggers controlling of sampling to each measurement passage respectively with sampling integrated circuit board SCSB.It constitutes identical with the integrated circuit board SCSB that samples with the unified signal condition that triggers sampling, unique different be local motor synchronizing controller LSC to the triggering of each passage be independently to carry out, the triggering sequential between them is controlled by local motor synchronizing controller LSC.The sort signal conditioning realizes the step of signal condition, signal sampling and sampled data transmission and the signal condition and the identical of integrated circuit board SCSB of sampling of unified triggering sampling with the integrated circuit board SCSB that samples
As shown in Figure 5, the signal condition that accurate multilevel delay control triggers independent extended channel sampling is same with sampling integrated circuit board SCSB analog signal conditioner passage, but the digital sample passage is independently, and it can realize the expansion and the raising of sample frequency.It is by optical fiber or radio transceiver interface, the synchro measure parameter receives controller RCSMP, signal condition controller SCC, simulating signal controller ASC, local motor synchronizing controller LSC, analog to digital converter ADC1～m, high precision multilevel delay controller MDC (Multilevel DaleyController), analog to digital conversion registers group ADCRG and sampled data send formations such as controller SCSD, wherein, high precision multilevel delay device MDC is made of delayer DY1～m, for narrow pulse signal, DY1～m among the high precision multilevel delay device MDC, can postpone to obtain multistage little delayed trigger signal with the raceway groove of transistor or MOSFET (mos field effect transistor), the realization high-accuracy pulse is controlled towards the timesharing multistage sampling.
As shown in Figure 6, accurate multilevel delay control triggers the signal condition of time division multiplex extended channel sampling and the analog signal conditioner passage of sampling integrated circuit board SCSB also is same, but the digital sample passage is multiplexing, and it also can realize the expansion and the raising of sample frequency.It is to be made of optical fiber or radio transceiver interface, synchro measure parameter reception controller RCSMP, signal condition controller SCC, simulating signal controller ASC, local motor synchronizing controller LSC, analog to digital converter ADC1～m, multiplexer switch multiplexer, high precision multilevel delay controller MDC, analog to digital conversion registers group ADCRG and sampled data transmission controller SCSD etc., and wherein high precision multilevel delay device MDC is made of delayer DY1～m.The sort signal conditioning triggers the signal condition of independent extended channel sampling and the basic identical of integrated circuit board SCSB of sampling with step and the control of accurate multilevel delay that sampling integrated circuit board SCSB realization signal condition, signal sampling and sampled data are transmitted.Difference is that the sort signal conditioning and the sampling triggering of sampling integrated circuit board SCSB digital channel are to realize time division multiplex by multiplexer switch multiplexer.
Below referring to figs. 1 through Fig. 7 the concrete application of the cluster control system that multidimensional synchronous high-speed of the present invention is measured is described.For example, in certain lithographic equipment, both there had been continuous signal, had pulse signal again, also had a large amount of sampling channels of gathering.There are three synchro measure control subsystem in it, and the synchro measure subsystem comprises that position measurement control system, pulse energy are measured, the Continuous Energy measurement subsystem.With shown in Figure 1 similar, it specifically is constructed as follows:
SCCAMD is by PROCESSOR processor 1, SDRAM storer 2, direct memory access (DMA) DMA control register group 3, direct memory access (DMA) dma controller 30～32, interruptable controller 4, double-port RAM DPRAM40～42, SYN register group 60～62, synchro control registers group 6, synchronous base controller group 7, isochronous controller SC group 70～72, data bus DB10, address bus AB11, synchronous bus SB50～52 compositions such as (comprising sync address bus SDB and synchronous data bus SAB).
Synchronous sequence controller STC is made up of SYN register group 60～62, synchro control registers group 6.Wherein SYN register group 60 is used to deposit the synchronization parameter that control subsystem is measured in the control position; SYN register group 61 is used to deposit the synchronization parameter of gating pulse energy measurement control subsystem; SYN register group 62 is used to deposit the synchronization parameter that the control Continuous Energy is measured control subsystem, and synchro control registers group 6 is used to deposit these three the sequential basic parameters between the amount control subsystem.
Measuring system isochronous controller MDSBS is made up of synchronous base controller group 7, isochronous controller group 70～72 and synchronous bus 50～52.MDSBS is made up of with sampling integrated circuit board group GSCSB900～90t...920～92t, synchronous bus 50～52 and sampling trigger signal and data transmission approach TASD etc. data acquisition controller DAC80～82 signal conditions.
Data acquisition controller DAC structure as shown in Figure 2.Sampling trigger signal and data transmission approach TASD can be that the electromagnetic transmission mode (comprises Optical Fiber Transmission mode and less radio-frequency transmission mode, their transmission protocol mode is identical), the data acquisition of control subsystem is measured in the DAC0 control position, the data acquisition of DAC1 gating pulse energy measurement control subsystem, the data acquisition that DAC2 control Continuous Energy is measured control subsystem.Signal condition and sampling integrated circuit board SCSB900～90t ..., 920～92t, wherein 900～90t is used for the position measurement control subsystem, can adopt signal condition and sampling plate SCSB unified or the independent triggers sampling; 920～92t is used for Continuous Energy and measures control subsystem, can adopt signal condition and sampling plate SCSB unified or the independent triggers sampling; 910～91t is used for pulse energy and measures control subsystem, can adopt accurate multilevel delay control to trigger signal condition and sampling plate SCSB independent extended channel sampling or the sampling of time division multiplex extended channel.
The PROCESSOR processor 1 of SCCAMD among Fig. 1 is used to dispose the cluster controlled variable that the multidimensional synchronous high-speed is measured.These parameter parts are placed among the synchronous sequence controller STC, and another part leaves in the DMA control register group 3.
PROCESSOR processor 1 is by writing some or certain register of synchro control registers group 6, control the cluster sampling trigger signal that sends synchro measure, and the data that collect are sent to reference numeral is among 40～42 the double-port RAM DPRAM, here, DPRAM0 is used for the exchange of position measurement control subsystem image data, DPRAM1 is used for the exchange that pulse energy is measured the control subsystem image data, the exchange that DPRAM2 control Continuous Energy is measured the control subsystem image data.After data are finished in collection, DPRAM forms look-at-me by the operation double-port RAM, PROCESSOR processor 1 starts direct memory access (DMA) DMA data transmission after receiving look-at-me, wherein control subsystem is measured in dma controller 30 control positions; Dma controller 31 gating pulse energy measurement control subsystem, dma controller 32 control continuous coverage control subsystem; Thereby finished a synchronous acquisition group's acquisition controlling, each measurement subsystem is all passed through similar process, realizes the cluster control that the multidimensional synchronous high-speed is measured.
As shown in Figure 7, the controlled step of certain lithographic equipment system of the cluster control method of measuring based on multidimensional synchronous high-speed of the present invention is as follows:
1) writes the SYN register group.Comprise the synchronization delay relation between measurement subsystem, the signal condition controlled variable of system definition, survey frequency, measure dot number, and inner passage trigger delay relation etc.;
2) initialization DMA control register group.DMA control register group is being deposited destination address, the source address of each dimension synchro measure bus direct memory access (DMA) DMA one side DMA transmission, and the length of direct memory access (DMA) DMA transmission;
3) write measuring system isochronous controller group.Delay sequential, sampling that the measuring system isochronous controller reads in signal condition parameter, synchronous triggering frequency and the sampling channel of respectively measuring passage in each measurement subsystem trigger parameters such as number;
4) start isochronous controller.The PROCESSOR processor starts isochronous controller, and isochronous controller sends the synchro control parameter information to data acquisition controller one by one;
5) log-on data acquisition controller DAC carries out synchro measure, gathers sampled data.The synchro measure controlling of sampling parameter that data acquisition controller DAC receives isochronous controller comprises that signal condition parameter, synchronized sampling trigger parameter and synchronized sampling trigger the sequential identification parameter.Then, log-on data acquisition controller DAC gathers sampled data;
6) isochronous controller SC transmitting synchronous measurement parameter is given data acquisition controller DAC;
7) data acquisition controller DAC sends the synchro measure parameter for signal condition and sampling integrated circuit board SCSB;
8) start local motor synchronizing sampling, gather synchronously sampled data.With this step carry out simultaneously in steps 9) to 11), step 13) has part period and this step to carry out simultaneously, sees shown in Figure 7;
9) signal condition receives and is provided with the synchro measure parameter with sampling integrated circuit board SCSB;
10) signal condition starts local motor synchronizing continuous sampling triggering with sampling integrated circuit board SCSB and measures;
11) signal condition transmits sampled data for data acquisition controller DAC with sampling integrated circuit board SCSB;
12) isochronous controller SC issue acquisition channel address;
13) data acquisition controller DAC is transferred to measurement data among the DPRAM;
14) isochronous controller SC issue DPRAM interrupt register address;
15) under the driving of DPRAM look-at-me, enter processor P ROCESSOR interrupt service routine, start the DMA transmission;
16) under the control of dma controller, the synchronously sampled data that the transmitting synchronous measurement collects.
In step 1), synchro control registers group 6 among the synchronous sequence controller STC is used to deposit benchmark lock in time of each measurement subsystem definition, comprise the synchronization delay relation between measurement subsystem, SYN register group 60～6n among the STC is used to deposit signal condition controlled variable, survey frequency, the measure dot number of each measurement subsystem definition, and inner passage trigger delay relation etc.
In step 2) in, DMA control register group is being deposited destination address, the source address of each dimension synchro measure bus direct memory access (DMA) DMA one side DMA transmission, and the length of direct memory access (DMA) DMA transmission.
In step 3), measuring system isochronous controller MSSC is after receiving the measurement instruction that PROCESSOR processor 1 sends, synchronous base controller group 7 will be read in the reference time of each measurement subsystem and the synchronization delay time sequence parameter between each measurement subsystem, from SYN register group 60～6n, delay sequential, the sampling of reading in signal condition parameter, synchronous triggering frequency and the sampling channel of respectively measuring passage in each measurement subsystem trigger parameters such as number to isochronous controller group 70～7n respectively.
In step 4), PROCESSOR processor 1 is by writing certain or some register in the synchro control registers group 6, start isochronous controller, isochronous controller sends the synchro control parameter information to data acquisition controller one by one, with the sampled data of control data acquisition controller DAC synchronous acquisition from signal condition and sampling integrated circuit board SCSB.
In step 5), data acquisition controller DAC is when receiving the synchro control parameter information of isochronous controller, the synchronous bus interface SBI of data acquisition controller DAC, the synchro control parameter information that obtains from synchronous bus SB comprises that signal condition parameter, synchronized sampling trigger parameter and synchronized sampling trigger the sequential identification parameter.Then, log-on data acquisition controller DAC gathers sampled data, step 6)～8) carry out simultaneously with this step.
In step 6), isochronous controller SC is transferred to the synchro measure parameter transmit control device SCSMP among the data acquisition controller DAC with the synchro measure parameter.
In step 7), synchro measure parameter transmit control device SCSMP in data acquisition controller DAC, the synchro control parameter information is received controller RCSMP by the synchro measure parameter that optical fiber or radio transceiver interface are sent to signal condition and sampling integrated circuit board SCSB, this integrated circuit board can just like Fig. 3～6 totally 4 kinds dissimilar, the signal condition and sampling integrated circuit board SCSB of selecting corresponding type for use according to different sample modes.
In step 8), all isochronous controller SC issue synchro measure start-up control frame by the data acquisition controller DAC to their correspondences, data acquisition controller DAC passes through optical fiber or radio transceiver interface separately, local motor synchronizing controller LSC on enabling signal conditioning and the sampling integrated circuit board SCSB allows local motor synchronizing controller LSC realize synchronized sampling.Optical fiber or radio transceiver interface as data acquisition controller DAC, after receiving the sampled data on signal condition and the sampling integrated circuit board SCSB, synchronously sampled data is sent among the data acquisition buffer group FIFOBG, after finishing measurement or during measuring, can receive controller RCSD by sampled data, the state of data acquisition buffer group FIFOBG is sent in the status register of synchronous bus interface SBI, and it is to receive controller RCSD by sampled data to finish record that the state of data acquisition buffer group FIFOBG changes.With this step carry out simultaneously in steps 9)～11), step 13) has part period and this step to carry out simultaneously, sees shown in Figure 7.
In step 9), trigger and the signal condition of independent triggers sampling and the integrated circuit board SCSB that samples for unified: the synchro measure parameter receives controller RCSMP and triggers the sequential identification parameter from optical fiber or radio transceiver interface received signal conditioning parameter, synchronized sampling trigger parameter and synchronized sampling, is provided with and controls synchronized sampling triggering number and synchronous sequence parameter.The signal condition parameter is issued signal condition controller SCC1～m, by simulating signal controller ASC1～m is controlled, with analog signal conditioner in measurement range.
In step 9), trigger the conditioning and sampling integrated circuit board SCSB of independent and time division multiplex extended channel sampling extended channel for accurate multilevel delay control: the synchro measure parameter receives controller RCSMP and triggers the sequential identification parameter from optical fiber or radio transceiver interface received signal conditioning parameter, synchronized sampling trigger parameter and synchronized sampling, the control synchronized sampling is set triggers number and synchronous sequence parameter.The signal condition parameter is issued signal condition controller SCC, by simulating signal controller ASC is controlled, with analog signal conditioner in measurement range.
In step 10), trigger and the signal condition and the integrated circuit board SCSB that samples of independent triggers sampling for unified: according to the parameter information that receives from optical fiber and wireless radio interface, local motor synchronizing controller LSC triggers number according to the control synchronized sampling and synchronized sampling triggers the sequential identification parameter, start local motor synchronizing controller LSC, the synchronized sampling of finishing a series of analog to digital conversion ADC1～m sampling channel triggers, and the unified here sampling of carrying out each synchro measure passage simultaneously triggers.
In step 10), control triggers the conditioning and the integrated circuit board SCSB that samples of independent and the sampling of time division multiplex extended channel for accurate multilevel delay: according to the parameter information that receives from optical fiber and wireless radio interface, local motor synchronizing controller LSC triggers number according to the control synchronized sampling and synchronized sampling triggers the sequential identification parameter, start local motor synchronizing controller LSC, local motor synchronizing controller LSC triggers number according to the control synchronized sampling and synchronized sampling triggers the sequential identification parameter, and startup high precision multilevel delay controller MDC carries out synchronized sampling to be triggered.The conditioning that accurate multilevel delay control triggers independent extended channel sampling realizes that by high precision multilevel delay device DY1～m-1 the sampling of same analog channel being carried out multiple digital passage ADC1～m triggers with sampling integrated circuit board SCSB.And the sampling of the digital channel of the conditioning of accurate multilevel delay control triggering time division multiplex extended channel sampling and sampling integrated circuit board SCSB triggers, and is by multiplexer switch multiplexer realization time division multiplex.
In step 11), the signal condition and the integrated circuit board SCSB that samples for unified triggering and independent triggers sampling: when signal condition is finished signal condition and each synchronized sampling triggering with the integrated circuit board SCSB that samples, sampling triggers start delay device DY, delay will be sampled and be issued sampled data transmission controller SCSD, start sampled data and send controller SCSD, by optical fiber or radio transceiver interface, with the synchronously sampled data that leaves among the analog to digital conversion registers group ADCRG, to the transmission of data acquisition controller DAC.
In step 11), trigger the conditioning and the sampling integrated circuit board SCSB of independent and time division multiplex extended channel sampling extended channel for accurate multilevel delay control: after signal condition is finished signal condition and finished the synchronized sampling triggering of analog to digital conversion sampling ADC 1～m passage with sampling integrated circuit board SCSB, trigger pip after will postponing through delayer DYm is issued sampled data and is sent controller SCSD, start sampled data and send controller SCSD, by optical fiber or radio transceiver interface, will leave synchronously sampled data among the analog to digital conversion registers group ADCRG in to the transmission of data acquisition controller DAC.
In step 12), isochronous controller SC0～n determines whether to carry out synchronized broadcast according to the status register of synchronous bus interface SBI in each measurement subsystem.Obtain broadcast authorized after, isochronous controller SC0～n issues a series of acquisition channels address, forms multicast bussing technique (MBBT:Multi Broadcast BusTechnology) and realizes multicast parallel data transmission control.
In step 13), data acquisition controller DAC is behind the address of receiving isochronous controller SC issue, read the sampled measurements data that leave among the FIFOBG, good according to the rules sequential is put on the synchronous bus SB, under the control of isochronous controller SC, all synchronously sampled datas are write in the DPRAM data exchange zone of measurement subsystem correspondence separately according to sampled point, the reading FIFOBG and the write data of DPRAM is carried out simultaneously of data acquisition controller DAC wherein, this is one of isochronous controller SC feature of realizing synchronized broadcast.
In step 14), isochronous controller SC carries out DMA at DPRAM and transmits side generation interruption by writing DPRAM interrupt register address.
In step 15), processor P ROCESSOR receive by step 14) cause in have no progeny, enter interrupt service routine, setting up procedure 16), promptly start the DMA data transmission, and revise the DMA transmission objectives address of depositing in the DMA control register group.
In step 16) in, under the control of dma controller, the synchronously sampled data that the transmitting synchronous measurement collects.
At first, PROCESSOR processor 1 writing position in the SYN register group 6 and 60～62, pulse energy and Continuous Energy in synchronous sequence controller STC are measured control subsystem definition synchronous base time, signal condition controlled variable, survey frequency, measure dot number, and inner passage trigger delay relation etc.Initialization DMA control register group 30～32 writes destination address, source address that DMA transmits respectively, and the length of direct memory access (DMA) DMA transmission.Delay sequential, the sampling of respectively measuring signal condition parameter, synchronous triggering frequency and the sampling channel of passage from SYN register group 60～62 in the measurement subsystem that will read trigger parameters such as number, write to measuring system isochronous controller group 70～72.
Next, PROCESSOR processor 1 startup isochronous controller sends the synchro control parameter information to data acquisition controller one by one.Synchro measure is carried out in log-on data acquisition controller DAC0～2, obtain synchro measure controlling of sampling parameter from synchronous bus SB and comprise that signal condition parameter, synchronized sampling trigger parameter and synchronized sampling trigger the sequential identification parameter, and it is stored among the synchro measure parameter transmit control device SCSMP one by one.By optical fiber or radio transceiver interface, the synchro measure parameter that is sent to signal condition and sampling integrated circuit board SCSB receives among the controller RCSMP again.
Then, the local motor synchronizing controller LSC on enabling signal conditioning and the sampling integrated circuit board SCSB allows local motor synchronizing controller LSC realize synchronized sampling.Start local motor synchronizing sampling, the optical fiber of data acquisition controller DAC or radio transceiver interface, after receiving the data that signal condition and sampling integrated circuit board SCSB900～90t, 910～91t and 920～92t be upsampled to, through optical fiber or radio transceiver interface synchronously sampled data is sent among the data acquisition buffer group FIFOBG, when finish measure after or measuring during, can receive controller RCSD by sampled data the state of data acquisition buffer group FIFOBG is sent in the status register of synchronous bus interface SBI.
At last, isochronous controller SC is according to the state of the status register of synchronous bus interface SBI, obtain broadcast authorized after, isochronous controller SC issues a series of acquisition channels address, synchronous bus is read FIFOBG to data acquisition controller DAC and simultaneously to the DPRAM write data, according to sampled point synchronously sampled data is write in the DPRAM data exchange zone of measurement subsystem correspondence separately.Isochronous controller SC is by writing DPRAM interrupt register address, carry out DMA at DPRAM and transmit side generation interruption, make PROCESSOR processor 1 enter interrupt service routine, start the DMA transmission, before End of Interrupt, revise the DMA transmission objectives address of depositing in the DMA control register group.
The present invention is than the difference of prior art, has used the synchronous and local motor synchronizing of multidimensional to combine Realize the at a high speed cluster control method of measurement, so that between the different measuring subsystem of this cluster control system Do not need synchronously synchronous calibration, just can realize very high synchronization accuracy, thus the complexity of the system that reduces, Improved the real-time of system. And, because local self synchronous clock frequency is higher, not not complete on the clock The full measurement synchronous error that causes synchronously is littler, can be not between a plurality of measurement subsystems and in the measurement subsystem Section carries out clock synchronous, also can realize very high measurement synchronization accuracy.
In addition, because the cluster control method that the multidimensional synchronous high-speed is measured of having sampled, so that the multidimensional synchronous high-speed The cluster control system of measuring not only can compatible continuous signal and the synchronous acquisition of pulse signal, can also Realize the concurrent working of signal sampling, data acquisition and the Synchronization Control of a plurality of systems, improved measurement data The data throughput of acquisition system and the sample frequency of a plurality of systems. Use the multilevel delay method of sampling to measure arteries and veins Rush signal, can take correlation method to improve and measure signal to noise ratio. Use local motor synchronizing and electromagnetic transmission mode Realize very little data and signal transmission delay, reduced the complexity of Synchronization Control, improved data acquisition The integrated level of collecting system has improved the speed of system data collection and the precision of synchronized sampling.
Claims (40)
1, a kind of cluster control system of multidimensional synchronous high-speed measurement, it is characterized in that, described system comprises measurement data acquisition synchronized clusters controller and measurement data sampling and caching system, and described measurement data acquisition synchronized clusters controller comprises processor, SDRAM storer, direct memory access (DMA) control register group, direct memory access (DMA) controller, interruptable controller, double-port RAM, synchronous sequence controller, measuring system isochronous controller, data bus, address bus and synchronous bus; Described measurement data sampling comprises data acquisition controller, signal condition and sampling integrated circuit board group, sampling trigger signal and data transmission approach and synchronous bus with caching system;
During measurement, the parameter of the cluster control that described processor configuration multidimensional data passage high-speed synchronous is gathered, and by writing the cluster sampling trigger signal that described synchronous sequence controller sends synchro measure, then the data that collect are sent in the described double-port RAM, the pending data collection is finished, described double-port RAM forms look-at-me, described processor receives described look-at-me, start the direct memory access (DMA) data transmission, finish a synchronous acquisition group's acquisition controlling.
2, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 1, it is characterized in that: described parameter is stored in described synchronous sequence controller and the direct memory access (DMA) control register group.
3, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 1, it is characterized in that: described synchronous sequence controller comprises SYN register group and synchro control registers group.
4, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 3, it is characterized in that: described processor sends the cluster sampling trigger signal of synchro measure by one or more registers of writing described synchro control registers group.
5, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 1, it is characterized in that: described measuring system isochronous controller comprises synchronous base controller group, isochronous controller group and synchronous bus.
6, as any cluster control system that described multidimensional synchronous high-speed is measured of claim 1 to 5, it is characterized in that: described synchronous bus comprises sync address bus and synchronous data bus.
7, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 1, it is characterized in that: described sampling trigger signal and data transmission approach comprise Optical Fiber Transmission mode and less radio-frequency transmission mode.
8, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 1, it is characterized in that: described data acquisition controller comprises synchronous bus, synchronous bus interface, synchro measure parameter transmit control device, data acquisition buffer group, sample Data Receiving controller and optical fiber and radio transceiver interface.
9, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 1 is characterized in that: described signal condition and sampling integrated circuit board comprise that the unification triggering is sampled, independent triggers is sampled, the independent extended channel of accurate multilevel delay control triggering is sampled and accurate multilevel delay is controlled four types of triggering time division multiplex extended channel samplings.
10, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 9, it is characterized in that: the signal condition of described unified triggering sampling has identical construction with the signal condition and the sampling plate jig of sampling integrated circuit board and independent triggers sampling, and it comprises that optical fiber or radio transceiver interface, synchro measure parameter reception controller, signal condition controller, simulating signal controller, local motor synchronizing control, analog to digital converter, delayer, analog to digital conversion registers group and sampled data send controller.
11, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 10 is characterized in that: the described unified signal condition that triggers sampling is measured the unified sampling simultaneously of passage with the integrated circuit board of sampling to each.
12, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 10 is characterized in that: the signal condition of described independent triggers sampling carries out independent triggers to each measurement passage respectively with the sampling integrated circuit board and samples.
13, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 9 is characterized in that: described accurate multilevel delay is controlled the signal condition that triggers independent extended channel sampling and the integrated circuit board of sampling and is comprised that optical fiber or radio transceiver interface, synchro measure parameter reception controller, signal condition controller, simulating signal controller, local motor synchronizing controller, analog to digital converter, high precision multilevel delay controller, analog to digital conversion registers group and sampled data send controller.
14, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 9 is characterized in that: the signal condition that described accurate multilevel delay control triggers the time division multiplex extended channel comprises that with the sampling integrated circuit board optical fiber or radio transceiver interface, synchro measure parameter reception controller, signal condition controller, simulating signal controller, local motor synchronizing controller, analog to digital converter, multiplexer switch, high precision multilevel delay controller, analog to digital conversion registers group and sampled data send controller.
15, as the cluster control system of claim 13 or 14 described multidimensional synchronous high-speeds measurements, it is characterized in that: described high precision multilevel delay device comprises some delayers.
16, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 13 is characterized in that: the signal condition that described accurate multilevel delay control triggers independent extended channel sampling adopts independently digital sample passage with the integrated circuit board of sampling.
17, the cluster control system of multidimensional synchronous high-speed measurement as claimed in claim 14 is characterized in that: described accurate multilevel delay control triggers the signal condition and the multiplexing digital sample passage of sampling integrated circuit board employing of time division multiplex extended channel.
18, a kind of cluster control method of multidimensional synchronous high-speed measurement is characterized in that, said method comprising the steps of:
A) parameter information with each measurement subsystem definition writes the synchronous sequence controller;
B) initialization direct memory access (DMA) control register group;
C) parameter information in each measurement subsystem is write the isochronous controller group;
D) start isochronous controller, the synchro control parameter information is sent to data acquisition controller;
E) data acquisition controller receives described synchro control parameter information, carries out synchro measure, gathers sampled data;
F) isochronous controller transmitting synchronous measurement parameter is to data acquisition controller;
G) data acquisition controller is sent to signal condition and sampling integrated circuit board with described synchro measure parameter;
H) start local motor synchronizing sampling, gather synchronously sampled data;
I) the synchro measure parameter is received and is provided with in signal condition and sampling plate clamping;
J) the local motor synchronizing continuous sampling of signal condition and sampling plate card start-up triggers and measures;
K) signal condition is sent to data acquisition controller with the sampling integrated circuit board with sampled data;
L) isochronous controller issue acquisition channel address;
M) data acquisition controller is transferred to measurement data in the double-port RAM;
N) the interrupt register address of isochronous controller issue double-port RAM;
O) drive by the double-port RAM look-at-me, enter the processor interrupt service routine, start the direct memory access (DMA) transmission;
P) synchronously sampled data that collects of direct memory access (DMA) controller control transmission synchro measure.
19, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: the parameter information among the described step a comprises synchronization delay relation, the signal condition controlled variable of system definition, survey frequency, the measure dot number between measurement subsystem, and inner passage trigger delay relation.
20, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18 is characterized in that: the parameter information among the described step c comprises that the delay sequential of signal condition parameter, synchronous triggering frequency and the sampling channel of respectively measuring passage, sampling trigger number.
21, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18 is characterized in that: the synchro control parameter information in the described steps d comprises that signal condition parameter, synchronized sampling trigger parameter and synchronized sampling trigger the sequential identification parameter.
22, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: the synchronous sequence controller comprises synchro control registers group and SYN register group among the described step a, described synchro control registers group is used to deposit benchmark lock in time of each measurement subsystem definition, comprise the synchronization delay relation between measurement subsystem, described SYN register group is used to deposit signal condition controlled variable, survey frequency, the measure dot number of each measurement subsystem definition, and inner passage trigger delay relation.
23, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step b, direct memory access (DMA) control register group is being deposited destination address, source address and the transmission length thereof of each dimension synchro measure bus direct memory access (DMA) one side direct memory access (DMA) transmission.
24, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step c, the measuring system isochronous controller is after receiving the measurement instruction that processor sends, synchronous base controller group will be read in the reference time of each measurement subsystem and the synchronization delay time sequence parameter between each measurement subsystem, from the SYN register group, delay sequential, the sampling of reading in signal condition parameter, synchronous triggering frequency and the sampling channel of respectively measuring passage in each measurement subsystem trigger number to the isochronous controller group respectively.
25, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described steps d, processor is by writing the one or more registers in the synchro control registers group, start isochronous controller, isochronous controller sends the synchro control parameter information to data acquisition controller one by one, with the sampled data of control data acquisition controller synchronous acquisition from signal condition and sampling integrated circuit board.
26, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step e, data acquisition controller is when receiving the synchro measure control parameter information of isochronous controller, the synchronous bus interface of data acquisition controller obtains synchro measure controlling of sampling parameter from synchronous bus, and the log-on data acquisition controller is gathered sampled data afterwards.
27, the cluster control method measured of multidimensional synchronous high-speed as claimed in claim 18 is characterized in that: in described step f, isochronous controller transfers to synchro measure parameter transmit control device in the data acquisition controller with the synchro measure parameter.
28, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step g, the synchro measure parameter transmit control device of data acquisition controller receives controller with the synchro control parameter information by the synchro measure parameter that optical fiber or radio transceiver interface are sent to signal condition and sampling integrated circuit board.
29, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step h, isochronous controller is by issuing synchro measure start-up control frame to its corresponding data acquisition controller, data acquisition controller passes through optical fiber or radio transceiver interface separately, local motor synchronizing controller on enabling signal conditioning and the sampling integrated circuit board allows local motor synchronizing controller realize synchronized sampling.
30, the cluster control method that multidimensional synchronous high-speed as claimed in claim 18 is measured, it is characterized in that: in described step I, signal condition for unification triggering and independent triggers sampling is nursed one's health parameter with sampling integrated circuit board synchro measure parameter reception controller from optical fiber or radio transceiver interface received signal, synchronized sampling trigger parameter and synchronized sampling trigger the sequential identification parameter, the control synchronized sampling is set triggers number and synchronous sequence parameter, and the signal condition parameter issued the signal condition controller, by the simulating signal controller is controlled, with analog signal conditioner in measurement range.
31, the cluster control method that multidimensional synchronous high-speed as claimed in claim 18 is measured, it is characterized in that: in described step I, trigger the conditioning and sampling integrated circuit board of independent and time division multiplex extended channel sampling extended channel for accurate multilevel delay control, the synchro measure parameter receives controller from optical fiber or radio transceiver interface received signal conditioning parameter, synchronized sampling trigger parameter and synchronized sampling trigger the sequential identification parameter, the control synchronized sampling is set triggers number and synchronous sequence parameter, and the signal condition parameter issued the signal condition controller, by the simulating signal controller is controlled, with analog signal conditioner in measurement range.
32, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step j, trigger and the signal condition of independent triggers sampling and the integrated circuit board of sampling for unified, local motor synchronizing controller triggers number according to the control synchronized sampling and synchronized sampling triggers the startup of sequential identification parameter, and the synchronized sampling of finishing a series of analog to digital conversion sampling channels triggers.
33, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step j, trigger the conditioning and sampling integrated circuit board of independent and the sampling of time division multiplex extended channel for accurate multilevel delay control, local motor synchronizing controller triggers number according to the control synchronized sampling and synchronized sampling triggers the startup of sequential identification parameter, trigger number and synchronized sampling triggering sequential identification parameter according to the control synchronized sampling again, start high precision multilevel delay controller and carry out the synchronized sampling triggering.
34, the cluster control method that multidimensional synchronous high-speed as claimed in claim 18 is measured, it is characterized in that: in described step k, trigger and the signal condition of independent triggers sampling and the integrated circuit board of sampling for unified, when signal condition and sampling integrated circuit board are finished signal condition and each synchronized sampling triggering, sampling triggers the start delay device, delay will be sampled and be issued sampled data transmission controller, start sampled data and send controller, by optical fiber or radio transceiver interface, the synchronously sampled data that leaves in the analog to digital conversion registers group is sent to data acquisition controller.
35, the cluster control method that multidimensional synchronous high-speed as claimed in claim 18 is measured, it is characterized in that: in described step k, trigger the conditioning and sampling integrated circuit board of independent and time division multiplex extended channel sampling extended channel for accurate multilevel delay control, after signal condition and sampling integrated circuit board are finished signal condition and are finished the synchronized sampling triggering of analog to digital conversion sampling channel, trigger pip after will postponing through delayer is issued sampled data and is sent controller, start sampled data and send controller, by optical fiber or radio transceiver interface, the synchronously sampled data that leaves in the analog to digital conversion registers group is sent to data acquisition controller.
36, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step 1, isochronous controller is according to the status register of synchronous bus interface in each measurement subsystem, determine whether to carry out synchronized broadcast, and obtain broadcast authorized after, realize multicast parallel data transmission control.
37, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step m, data acquisition controller is behind the address of receiving the isochronous controller issue, read the sampled measurements data that leave in the data acquisition buffer group, be put into synchronous bus according to set sequential, under the control of isochronous controller, all synchronously sampled datas are write in the double-port RAM data exchange zone of measurement subsystem correspondence separately according to sampled point.
38, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step n, isochronous controller carries out direct memory access (DMA) at double-port RAM and transmits side generation interruption by writing double-port RAM interrupt register address.
39, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18, it is characterized in that: in described step o, processor receive by described step n cause in have no progeny, enter interrupt service routine, setting up procedure p, and revise the direct memory access (DMA) transmission objectives address of depositing in the direct memory access (DMA) control register group.
40, the cluster control method of multidimensional synchronous high-speed measurement as claimed in claim 18 is characterized in that: in described step p, and under the control of direct memory access (DMA) controller, the synchronously sampled data that the transmitting synchronous measurement collects.
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