CN100557566C - The method of instruction accessing and scheduling and device thereof - Google Patents
The method of instruction accessing and scheduling and device thereof Download PDFInfo
- Publication number
- CN100557566C CN100557566C CNB2006101386866A CN200610138686A CN100557566C CN 100557566 C CN100557566 C CN 100557566C CN B2006101386866 A CNB2006101386866 A CN B2006101386866A CN 200610138686 A CN200610138686 A CN 200610138686A CN 100557566 C CN100557566 C CN 100557566C
- Authority
- CN
- China
- Prior art keywords
- instruction
- write
- writes
- reciprocity
- write registers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention provides the method and the device thereof of a kind of instruction accessing and scheduling, particularly a kind of method of instruction accessing comprises the following steps: to receive at least one instruction; Judge that this instruction is one to write instruction or and non-ly write instruction, wherein if this instruction for this write instruction then with this instruction storage in an element write registers, be that this non-ly writes instruction as if this instruction, then with this instruction storage in the non-write registers of an element; Judge whether this instruction is a reciprocity operational order, wherein, for instructing, nonequivalence operation then this instruction is sent to a processing unit as if this instruction if this instruction is a reciprocity operational order then should instruct and be sent to an instruction downstream units via a reciprocity operational order path; And receive instruction that this equity operational order path and this processing unit send and descending respectively this and write that instruction and this are non-to write instruction.The present invention can avoid the problem of system in case of system halt effectively, and makes total system successfully to operate.
Description
Technical field
The invention relates to the method and the device thereof of a kind of access and scheduling instruction, refer to the method and the device thereof of a kind of access and scheduling equity operational order especially.
Background technology
Along with improving constantly of processor and system performance, (Peripheral ComponentsInterconnect Express PCIE) more and more is applied in the computer system high speed peripheral element connecting interface of employing series connection, point-to-point connection framework.The chipset of computer system is connected with each peripheral element by the PCIE bus, and the instruction that makes each peripheral element send is sent to central processing unit by chipset and carries out computing.
In the framework of PCIE, the action that chipset is not deciphered for the board address scope (onboard address range) and the high speed peripheral element connecting interface memory range (peer-to peer address range) of up-on command, therefore all up-on commands are no matter be that substrate instruction (onboard access) or reciprocity operational order (peer-to-peer access) all are sent to central processing unit and carry out computing, and the central processing unit computing comes downwards to instruction each peripheral element after intact again.
Fig. 1 is the instruction accessing calcspar of known computer systems.Each peripheral device 121～124 is sent respectively and is instructed to chipset 10, and these instructions are stored in working storage 111～114 respectively with the form of a formation (Queue) respectively.The priority of ruling port one 20 these up-on commands of decision, that is these instructions send the sequencing of central processing unit 140 to.Instruction comes downwards to code translator 130 after central processing unit 140 computings are intact.130 pairs of these downlink commands of code translator carry out the target peripheral element of action to determine that downlink command will transmit of bit address decoding.
In above-mentioned framework, no matter be that (Peer-to-Peer P2P) all need be sent to central processing unit 140 and carry out computing for substrate instruction (onboard access) or reciprocity computing.But in fact, reciprocity operational order is the action and must be via central processing unit 140 computings mutually of 151～154 of each peripheral elements.If the equity instruction also needs to be sent to central processing unit 140, so can make the stand-by period (latency) of call instruction long.If instruction writes instruction for storer, central processing unit 140 can prolong the time of data from central processing unit 140 write stories, and prolong and to read the time of next instruction, that is postpone up memory access instruction, cause the general performance meeting to significantly decrease.
Summary of the invention
The present invention is method and the device thereof that proposes a kind of access and scheduling instruction, and it can avoid the problem of system in case of system halt in the conventional practice effectively, and makes total system successfully to operate.
The present invention proposes a kind of method of instruction accessing, in order at least one instruction of access, wherein this instruction can be one and writes instruction or and non-ly write instruction, this method comprises: if instruction is for writing instruction, then instruction being stored to an element writes temporary, if instruction is the non-instruction that writes, then instruction is stored to the non-write registers of an element.Judge that then also scheduling writes instruction and the non-precedence that writes instruction, wherein if instruction is nonequivalence operation instruction, then make call instruction by a processing unit processes,, then make call instruction be sent to an instruction downstream units via reciprocity arithmetic path if instruction is a reciprocity operational order.
The present invention proposes a kind of method of instruction scheduling again, comprising: receive and judge whether an instruction is a reciprocity operational order, if whether instruction for this equity operational order, then has a non-stand-by period that writes instruction to surpass a schedule time before the decision instruction.Surpass this schedule time if not write the stand-by period of instruction, and instruction is one to write instruction, makes then that the precedence of call instruction is leading non-to write instruction.
The present invention proposes a kind of method of instruction scheduling again, comprise: receive an instruction, wherein if instruction writes instruction for one of reciprocity computing, and there is a non-stand-by period that writes instruction of reciprocity computing to surpass a schedule time before wherein writing instruction, makes then that the precedence that writes instruction is leading non-to write instruction.
The present invention proposes quick peripheral coupling arrangement instruction accessing device again, comprise: at least one peripheral element, in order to send at least one instruction, wherein if instruction is one to write instruction, then instruction is stored in an element write registers, if instruction is one non-ly to write instruction, then instruction is stored in the non-write registers of an element.One chip is connected to peripheral element in order to this instruction of access; And a processing unit, be connected in order to processing instruction with chip.
The present invention can avoid the problem of system in case of system halt effectively, and makes total system successfully to operate.
Description of drawings
Fig. 1 illustrates the synoptic diagram into computer system chips group.
Fig. 2 illustrates the synoptic diagram into another computer system chips group.
Fig. 3 illustrates the calcspar into the device of one embodiment of the present of invention.
Fig. 4 illustrates the detailed block diagram into the device of one embodiment of the present of invention.
Fig. 5 illustrates the process flow diagram into the method for one embodiment of the present of invention.
Fig. 6 illustrates the process flow diagram into the method for another embodiment of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
In order to solve the problem of above-mentioned central processing unit 140 usefulness, Fig. 2 is provided with a reciprocity operational order path in chipset.When peripheral element 251～254 is sent when instructing to chipset 20, whether the action of last line decoder 240 pairs of described instructions carrying out address realm decoding is reciprocity operational order with decision instruction.(for example: the substrate instruction) then being sent to central processing unit 250 carries out computing, instruction is come downwards to descending ruling port 270 after central processing unit 250 computings are intact again if instruction is for the nonequivalence operation instruction; If instruction then directly will be instructed and deliver to descending ruling port 270 via reciprocity operational order path 260 for reciprocity operational order.
The sequencing that the reciprocity operational order that 270 decisions of descending ruling port transmit by the descending nonequivalence operations instruction of central processing unit 250 and by reciprocity operational order path 260 is descending also is sent to down line decoder 280.280 pairs of downlink commands of following line decoder carry out the action of address decoding, with the target peripheral element 251～254 that determines that downlink command will transmit.
In above-mentioned framework, because reciprocity operational order no longer delivers to central processing unit 250 and carry out computing, but directly transmits, so significantly save the shared resource of central processing unit 250 via reciprocity operational order path 260.In addition, by the delay of having shortened reciprocity operational order that is provided with in reciprocity operational order path 260, whole usefulness performance is promoted.
Yet problem still can take place in above-mentioned framework in some cases.For example, if peripheral element 251 sends a reciprocity computing reading command that reads the data on the peripheral element 252, and peripheral element 252 also sends a reciprocity computing that data are write peripheral element 253 and writes instruction.Because reading command must just can be performed after finishing writing instruction.Therefore can make reading command with write the vicious cycle that instruction is waited for mutually, and make total system crash.
In order to solve the above problems, the invention provides a kind of quick peripheral coupling arrangement instruction accessing device, a kind of method of instruction accessing and a kind of method of instruction scheduling, working storage is distinguished into write registers and non-write registers, and if having non-when writing instruction to be written such as instruction needs from buffer zone removing (flush) (that is etc. instruction to be written is processed finish), make that write instruction writes instruction by reciprocity operational order path is leading non-, to avoid causing system in case of system halt.
For the method for instruction accessing of the present invention is described, please refer to Fig. 3.Fig. 3 is for utilizing of the present invention one quick peripheral coupling arrangement instruction accessing device 300.As shown in Figure 3, quick peripheral coupling arrangement instruction accessing device 300 includes: processing unit 310, chip 320, and a plurality of peripheral element in the middle of present embodiment, suppose to have four peripheral elements 330,340,350 and 360.Chip 320 is connected in the instruction of being sent by peripheral element 330～360 in order to quick access between processing unit 310 and the peripheral element 330～360.And each peripheral element 330～360 includes respectively whether peripheral device 334,344,354,364, one board address scope decoding units 331,341,351 and 361 that produce instruction are reciprocity operational order in order to reception and translation instruction.An element write registers 332,342,352 and 362 is also arranged respectively in addition, and non-write registers 333,343,353 of element and 363 writes instruction (posted) and non-ly writes instruction (non-posted) in order to store respectively.Chip 320 includes an instruction upstream cell 321 and an instruction downstream units 322.Instruction upstream cell 321 receives the instruction of being uploaded by peripheral element 330～360 respectively, if instruction is not reciprocity operational order, then upload to processing unit 310 and handle,, then utilize reciprocity operational order path 370 to be sent to instruction downstream units 322 and handle if instruction is reciprocity operational order.
Please refer to Fig. 4, the detailed inside calcspar that illustrates instruction upstream cell 321 among Fig. 3 and instruction downstream units 322.
As shown in Figure 4, instruction upstream cell 321 includes: up instruction ruling port 3211, one up non-instruction ruling port 3212, one up write registers 3213, one up non-write registers 3214 and the up scheduler 3215 that write that write.Instruction downstream units 322 includes: a descending scheduler 3221, is descending to write that command decoder 3222, is descending non-ly to write that command decoder 3223, is descending to write instruction registor 3224, and a descending non-instruction registor 3225 that writes.
Below illustrate the method for instruction accessing of the present invention.After peripheral device 334～364 sent instruction respectively, board address scope decoding unit 331～361 can be deciphered these instructions respectively to judge whether being reciprocity operational order.Decision instruction afterwards is stored in respectively in the non-write registers 333～363 of element write registers 332～362 and element then for writing (posted) instruction or non-writing (non-posted) instruction.The instruction that is stored in subsequently in the non-write registers 333～363 of element write registers 332～362 and element is sent to respectively in the instruction upstream cell 321.
Up writing in the instruction upstream cell 321 instructs ruling port 3211 and the up non-instruction ruling port 3212 that writes to determine the sequencing of the instruction in element write registers 332～362 and the non-write registers 333～363 of element respectively, and is stored into respectively in up write registers 3213 and the up non-write registers 3214.And up scheduler 3215 uploads to processing unit 310 with the instruction that the nonequivalence operation in up write registers 3213 and the up non-write registers 3214 instructs, and goes further downwards to instruction downstream units 322 after being handled by processing unit 310.Up in addition scheduler 3215 is sent to instruction downstream units 322 with the instruction of the reciprocity operational order in a up write registers 3213 and the up non-write registers 3214 via reciprocity operational order path 370.
If wherein there is a non-stand-by period that writes instruction of sending earlier to surpass a preset time T (that is have send earlier non-to write (posted) instruction that writes of sending after (non-posted) instruction needs to wait for remove (flush) from the working area), the precedence of sending after then making that writes instruction surmounts send earlier non-and writes instruction.
For instance, suppose that writing instruction REQ1 as one will be sent to instruction during downstream units 322 via reciprocity operational order path 370, if there is a non-stand-by period that writes instruction REQ0 of sending earlier to surpass preset time T, then utilize the reciprocity operational order path 370 feasible leading non-instruction REQ0 that write of precedence that write instruction REQ1.So can avoid writing instruction REQ1 and the non-instruction REQ0 that writes waits for mutually and causes system in case of system halt.
And the descending scheduler 3221 in the instruction downstream units 322 receives the instruction that is sent by processing unit 310 and instruction upstream cell 321 respectively, then utilize descendingly to write command decoder 3222 and the descending non-command decoder 3223 that writes is deciphered respectively and write instruction and non-ly write instruction, be stored in one afterwards more respectively and descendingly write instruction registor 3224 and descending non-writing in the instruction registor 3225.The last peripheral element 330～360 that is sent to correspondence again.
Fig. 5 is the method flow diagram of instruction accessing of the present invention.At first, when receiving instruction REQ{REQ_P2P_WR/REQ_NONP2P_WR/REQ_P2P_RD/REQ_NONP2P_RD}, board address scope decoding unit 331～361 translation instruction REQ are reciprocity operational order (REQ_P2P) or nonequivalence operation instruction (REQ_NONP2P) with decision instruction REQ, and decision instruction REQ is for writing instruction (REQ_P2P_WR/REQ_NONP2P_WR) or non-ly writing instruction (REQ_P2P_RD/REQ_NONP2P_RD) (step S501).Then will write instruction (REQ_P2P_WR/REQ_NONP2P_WR) respectively and be stored in the element write registers 332～362, and non-ly write instruction (REQ_P2P_RD/REQ_NONP2P_RD) and be stored in the non-write registers 333～363 of element (step S502).Uply write instruction ruling port 3211 and the up non-instruction ruling port 3212 that writes determines the non-sequencing (step S503) that writes instruction (REQ_P2P_RD/REQ_NONP2P_RD) in instruction (REQ_P2P_WR/REQ_NONP2P_WR) and the non-write registers 333～363 of element of writing in the element write registers 332～362 respectively.And will write instruction (REQ_P2P_WR/REQ_NONP2P_WR) respectively and be stored into up write registers 3213, and write instruction (REQ_P2P_RD/REQ_NONP2P_RD) and be stored in the up non-write registers 3214 (step S504) non-.Then, up scheduler 3215 receives in regular turn and is stored in writing instruction (REQ_P2P_WR/REQ_NONP2P_WR) and non-ly writing instruction (REQ_P2P_RD/REQ_NONP2P_RD) in up write registers 3213 and the up non-write registers 3214, and judges whether to be reciprocity operational order (REQ_P2P) (step S 505).Wherein if instruction for nonequivalence operation instruction (REQ_NONP2P), then is sent to processing unit 310 (step S506).If instruction is reciprocity operational order (REQ_P2P_WR/REQ_P2P_RD), then be sent to instruction downstream units 322 (step S507) via reciprocity operational order path 370.Descending scheduler 3221 receives the instruction that is sent by processing unit 310 and instruction upstream cell in regular turn, and will write instruction (REQ_P2P_WR/REQ_NONP2P_WR) and be sent to the descending command decoder 3222 that writes, and write instruction (REQ_P2P_RD/REQ_NONP2P_RD) and be sent to the descending non-command decoder 3223 (step S508) that writes non-.Descendingly write command decoder 3222 and a descending non-command decoder 3223 that writes is deciphered respectively and write instruction (REQ_P2P_WR/REQ_NONP2P_WR) and non-ly write instruction (REQ_P2P_RD/REQ_NONP2P_RD) (step 509).Then, with writing instruction (REQ_P2P_WR/REQ_NONP2P_WR) and non-ly write instruction (REQ_P2P_RD/REQ_NONP2P_RD) and be stored in descending instruction registor 3224 and descending non-write (the step S510) in the instruction registor 3225 of writing in regular turn after the decoding.The instruction that to handle at last is sent to corresponding peripheral element 330～360 (step S511).
Figure 6 shows that the method flow diagram of instruction scheduling among the present invention.At first up scheduler 3215 is received an instruction REQ_1 (step S601) who is sent by up write registers 3213 or up non-write registers 3214.Then whether decision instruction REQ_1 is reciprocity operational order (step S602).If instruction REQ_1 is not reciprocity operational order, then will instruct REQ_1 to be sent to processing unit 310 (step S603).If instruction REQ_1 is reciprocity operational order, whether there is a non-stand-by period that writes instruction REQ_0 to surpass a schedule time T (step S604) before the decision instruction REQ_1.If no, then will instruct REQ_1 to be sent to descending scheduler 3221 (step S605) via reciprocity operational order path.If have, then whether decision instruction REQ_1 is one and writes instruction (step S606).If not, then skip to step S605, will instruct REQ_1 to be sent to descending scheduler 3221 via reciprocity operational order path.If then make the leading non-instruction REQ_0 (step S607) that writes of precedence of call instruction REQ_1.
For instance, will read data on the peripheral element 340, and peripheral element 340 sends a reciprocity computing and writes instruction REQ_P2P_WR and data will be write peripheral element 350 if peripheral element 330 sends a reciprocity computing reading command REQ_P2P_RE.The stand-by period of the reciprocity computing reading command REQ_P2P_RE that up scheduler 3215 meeting detecting peripheral elements 330 of the present invention are sent, if the stand-by period surpasses preset time T, the reciprocity computing that then allows peripheral element 340 be sent writes instruction REQ_P2P_WR and earlier delivers to instruction downstream units 322 via reciprocity operational order path 370, and does not need the reciprocity computing reading command REQ_P2P_RE that waits for that peripheral element 330 sends.
In addition, if desire to reach higher efficient, reciprocity operational order path 370 more can be divided into two paths, comprises that a reciprocity operand store writes command path 371 (not shown)s, writes instruction REQ_P2P_WR in order to the reciprocity operand store of special transmission; And non-command path 372 (not shown)s that write of a reciprocity operand store, in order to the non-instruction REQ_P2P_RD that writes of the reciprocity operand store of special transmission.
The disclosed chip 320 of the above embodiment of the present invention can be a north bridge chipset, can also be a South Bridge chip group.The method of instruction scheduling of the present invention and relevant apparatus can be avoided the problem of system in case of system halt effectively, and make total system successfully to operate.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
10,20: north bridge chipset
111～114,211～214: buffer
120: the ruling port
130: decoder
140,250: central processing unit
121～124,221～224,334～364: peripheral device
220: up ruling port
230: up working storage
240: go up line decoder
260,440: reciprocity operational order path
270: descending ruling port
280: following line decoder
290: descending working storage
300: quick peripheral coupling arrangement instruction accessing device
310: processing unit
320: chip
321: the instruction upstream cell
3211: the up instruction ruling port that writes
3212: the up non-instruction ruling port that writes
3213: the up instruction registor that writes
3214: the up non-instruction registor that writes
3215: up scheduler
322: the instruction downstream units
3221: descending scheduler
3222: the descending command decoder that writes
3223: the descending non-command decoder that writes
3224: the descending instruction registor that writes
3225: the descending non-instruction registor that writes
151～154,251～254,330～360: peripheral element
331,341,351,361: board address scope decoding unit
332,342,352,362: the element write registers
333,343,353,363: the non-write registers of element
S501～S511, S601～S607: method flow
Claims (14)
1. the method for an instruction accessing is characterized in that, in order at least one instruction of access, wherein this instruction can be one and writes instruction or and non-ly write instruction, and the method for described instruction accessing comprises:
If this instruction writes instruction for this, then store this instruction to one element write registers;
Write instruction as if this instruction for this is non-, then store the non-write registers of this instruction to one element; And
This writes instruction and this non-precedence that writes instruction to judge also scheduling;
Wherein, then make this instruction by a processing unit processes if this instruction is nonequivalence operation instruction; Wherein, then make this instruction be sent to an instruction downstream units via a reciprocity arithmetic path if this instruction is a reciprocity operational order.
2. the method for instruction accessing according to claim 1, it is characterized in that, more comprise and judge that earlier this instruction for this equity operational order or the instruction of this nonequivalence operation, stores this instruction respectively again to this element write registers or the non-write registers of this element.
3. the method for instruction accessing according to claim 1, it is characterized in that, if this instruction is the instruction that writes of a reciprocity computing, and there is the non-stand-by period that writes instruction of a reciprocity computing to surpass a schedule time before this instruction, then make the precedence of this instruction surpass that this equity computing is non-to write instruction, wherein utilize one first reciprocity arithmetic path to transmit that this equity computing is non-to be write instruction and instruct downstream units to this; And the instruction that writes that utilizes one second reciprocity arithmetic path to transmit this equity computing is instructed downstream units to this.
4. the method for instruction accessing according to claim 1 is characterized in that, comprises this instruction downstream units and receives and judge precedence by this processing unit and this instruction of should the equity arithmetic path transmitting.
5. the method for an instruction scheduling is characterized in that, the method for described instruction scheduling comprises:
Receive an instruction;
Wherein if this instruction is that one of a reciprocity computing writes instruction, and wherein this has a non-stand-by period that writes instruction of reciprocity computing to surpass a schedule time before writing instruction, then makes this write leading this of the precedence of instruction and non-ly writes instruction.
6. the method for instruction scheduling according to claim 5 is characterized in that, if this instruction is nonequivalence operation instruction, then this instruction is sent to a processing unit.
7. the method for instruction scheduling according to claim 5, it is characterized in that, if should non-ly not write instruction before this instruction, the stand-by period that perhaps should non-ly write instruction did not have above this schedule time, then made this instruction be sent to one via a reciprocity operational order path and instructed downstream units.
8. the method for instruction scheduling according to claim 5, it is characterized in that, utilize one first reciprocity operational order path to transmit non-ly to write instruction to instruct downstream units, and utilize one second reciprocity operational order path to transmit this to write instruction and instruct downstream units to this.
9. a quick peripheral coupling arrangement instruction accessing device is characterized in that, described quick peripheral coupling arrangement instruction accessing device comprises:
At least one peripheral element in order to send at least one instruction, wherein if this instruction is one to write instruction, then stores this and instructs in an element write registers, wherein if this instruction is one non-ly to write instruction, then stores this and instructs in the non-write registers of an element;
One chip is connected to this peripheral element in order to this instruction of access; And
One processing unit is connected in order to handle this instruction with this chip.
10. quick peripheral coupling arrangement instruction accessing device according to claim 9, it is characterized in that, each this peripheral element more comprises a board address scope decoding unit, receives and judges that this instruction is the instruction of a reciprocity operational order or a nonequivalence operation; And a peripheral device, be connected to this board address scope decoding unit, in order to send this instruction.
11. quick peripheral coupling arrangement instruction accessing device according to claim 9 is characterized in that this chip includes:
One instruction upstream cell is in order to receive this instruction of being uploaded by each this element write registers and the non-write registers of each this element respectively; And
One instruction downstream units receives this instruction that is sent by this instruction upstream cell and this processing unit, and is sent to this corresponding peripheral element.
12. quick peripheral coupling arrangement instruction accessing device according to claim 11 is characterized in that this instruction upstream cell includes:
One up write registers;
The one up instruction ruling port that writes is connected between this element write registers and this up write registers, in order to receive and to judge the precedence of this instruction that is stored in this element write registers, afterwards this instruction is stored in this up write registers;
One up non-write registers;
The one up non-instruction ruling port that writes, be connected between the non-write registers of this element and this up non-write registers, in order to receive and to judge the precedence of this instruction that is stored in the non-write registers of this element, afterwards this instruction is stored in this up non-write registers; And
One up scheduler is connected to this up write registers and this up non-write registers, is stored in writing instruction and non-ly writing instruction of this up write registers and this up non-write registers in order to scheduling.
13. quick peripheral coupling arrangement instruction accessing device according to claim 12 is characterized in that, if this instruction is the nonequivalence operation instruction, then this up scheduler transmits this instruction to this processing unit; If this instruction is reciprocity operational order, then this up scheduler transmits this instruction to this instruction downstream units via one first reciprocity operational order path; Wherein if this instruction is the instruction that writes of a reciprocity computing, and the non-stand-by period that writes instruction that a reciprocity computing arranged before this instruction surpasses a schedule time, and then this up scheduler precedence that writes instruction of making this equity computing writes instruction above this equity computing non-; Wherein utilize one second reciprocity operational order path to transmit the instruction that writes of this equity computing, make the instruction that writes of this equity computing write instruction than this equity computing non-and early be sent to this instruction downstream units.
14. quick peripheral coupling arrangement instruction accessing device according to claim 12 is characterized in that this instruction downstream units includes:
One descending scheduler is in order to receive this instruction that is sent by this processing unit and this instruction upstream cell respectively;
The one descending command decoder that writes is connected to this descending scheduler, receives and decoding is sent by this descending scheduler that this writes instruction;
One descending write registers is connected in this descending writing between command decoder and each this peripheral element, stores this descending later this of command decoder decoding that write and writes instruction, and be sent to this corresponding peripheral element;
The one descending non-command decoder that writes is connected in this descending scheduler, receives and decoding is sent by this descending scheduler that this non-ly writes instruction; And
One descending non-write registers is connected in this descending non-writing between command decoder and each this peripheral element, store this descending non-write command decoder decoding later should non-ly write instruction, and be sent to this peripheral element of correspondence.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101386866A CN100557566C (en) | 2006-11-10 | 2006-11-10 | The method of instruction accessing and scheduling and device thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101386866A CN100557566C (en) | 2006-11-10 | 2006-11-10 | The method of instruction accessing and scheduling and device thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1936832A CN1936832A (en) | 2007-03-28 |
| CN100557566C true CN100557566C (en) | 2009-11-04 |
Family
ID=37954350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101386866A Active CN100557566C (en) | 2006-11-10 | 2006-11-10 | The method of instruction accessing and scheduling and device thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100557566C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI574158B (en) * | 2014-12-01 | 2017-03-11 | 旺宏電子股份有限公司 | Data processing method and system with application-level information awareness |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4716522A (en) * | 1982-03-10 | 1987-12-29 | Hitachi, Ltd. | Microcomputer system with buffer in peripheral storage control |
| US6782456B2 (en) * | 2001-07-26 | 2004-08-24 | International Business Machines Corporation | Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism |
-
2006
- 2006-11-10 CN CNB2006101386866A patent/CN100557566C/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4716522A (en) * | 1982-03-10 | 1987-12-29 | Hitachi, Ltd. | Microcomputer system with buffer in peripheral storage control |
| US6782456B2 (en) * | 2001-07-26 | 2004-08-24 | International Business Machines Corporation | Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1936832A (en) | 2007-03-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9128920B2 (en) | Interrupt handling systems and methods for PCIE bridges with multiple buses | |
| CN102866971A (en) | Data transmission device, system and method | |
| KR101512743B1 (en) | Direct memory access without main memory in a semiconductor storage device-based system | |
| CN1394310A (en) | Inter-processor communication system | |
| EP1535169B1 (en) | Improved inter-processor communication system for communication between processors | |
| JP2010128696A (en) | Bus bridge device and bus bridge system using the same | |
| CN104239252A (en) | Data transmission method, device and system of data storage system | |
| KR102367359B1 (en) | Electronic system having serial system bus interface and direct memory access controller and method of operating the same | |
| TWI335517B (en) | Method of requests access and scheduling and related apparatus thereof | |
| CN107066413B (en) | Method for processing data of multiple bus devices and bus system thereof | |
| CN1529256A (en) | Dual-ring quene-based, non-interrupt PCI communication method | |
| CN105718396B (en) | A kind of I of big data master transmissions2C bus units and its means of communication | |
| CN100557566C (en) | The method of instruction accessing and scheduling and device thereof | |
| CN100524267C (en) | Data processing system and data processing method | |
| KR20120134918A (en) | Electronic apparatus including a plurality of processors | |
| CN111290983A (en) | USB transmission equipment and transmission method | |
| KR102645983B1 (en) | Open channel vector command execution | |
| CN111221757B (en) | Low-delay PCIE DMA data transmission method and controller | |
| CN115994115B (en) | Chip control method, chip set and electronic equipment | |
| US20080082708A1 (en) | Token hold off for chipset communication | |
| CN104615558A (en) | Data transferring method and electronic device | |
| JP4853951B2 (en) | Data processing device | |
| CN110633233A (en) | DMA data transmission processing method based on assembly line | |
| CN103744816B (en) | Universal serial bus equipment and data transmission method thereof | |
| CN206479978U (en) | A kind of bus system for being used to handle multiple bus apparatus data |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |