CN100556086C - High frame rate high definition imaging system and method - Google Patents
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Abstract
A kind of high frame rate high definition imaging system and method are disclosed.With imager (104) clock control is to be asynchronous to the output video clock of expectation (114).During the frame cycle period, the data clock that utilizes imager clock signal (102) will remain in the first of the pel array in the imager is controlled out imager (104), and walks around the data in the second portion that remains on pel array.Subsequently, exported with the video clock speed of imager data transaction Cheng Genggao and as required video data.
Description
Related application data
Present patent application has required preferential day rights and interests of No. 60/452,646, the U.S. Provisional Patent Application submitted on March 7th, 2003 according to 35USC119 (e) clause, specially the full content of this piece application is incorporated herein by reference at this.
Technical field
Present invention relates in general to imaging system and method.More specifically, the present invention relates to high-resolution imaging system and method.
Background technology
Electronic image sensor such as charge-coupled device (CCD) is well known.In the CCD imager, the image information that is associated with each pixel in the pel array is accumulated as electric charge, and described electric charge is read from imager as view data.Therefore, CCD and other electronic imaging apparatus need an accurate commutator pulse sequence to come reads image data from imageing sensor sequentially.These accurate commutator pulses are to offer electronic image sensor with specific clock frequency.This clock rate of reading will be determined the amount (number of pixel) of the view data that time per unit can be read from imager.Therefore, the image resolution ratio of this clock rate restriction designated frame speed.
The imaging system of the high frame rate of high-resolution becomes important for the many application that need high quality graphic such as HDTV camera, this class of medical imaging and other application.For such high frame rate high definition imaging, need very high readout clock speed.In fact, in order in the allowed time, send from imager can transmit the restriction of the speed of electric charge effectively with it in the middle of the CCD imager design that trends towards being close to or higher than of the needed clock frequency of electric charge of all pixels in routine.For other electronic imager such as cmos image sensor, also there is similarly restriction.In addition, when the high-resolution imageing sensor of assembling, manufacturer is especially careful to prevent issuable noise and distortion between reading duration.Consequently, the electronic imager of the high frame rate of high-resolution all needs special design usually, and this special design is very expensive for being suitable for for the imager of low clock rate work.As a specific example, typical high-resolution (HD) ccd sensor, such as the ICX204AL of Sony, it is suitable for machine vision applications and is decided to be the only speed of per second 15 frames by the readout mode line by line of standard, and this just can be with the sub-fraction of the cost of high-resolution (HD) ccd sensor of the clock rate work that is suitable for standard frame speed (per second 50 or 60 frames).
Therefore, need a kind of imager cheaply that high-definition picture can be provided with high frame rate.
Summary of the invention
In a first aspect of the present invention, a kind of imaging system is provided, comprise timing generator, it provides imager clock signal with imager clock rate and the video clock signal that has greater than the video clock speed of this imager clock rate.Described imaging system also comprises imager, and it has imager input end of clock and the data output end that receives the imager clock signal.Described imaging system also comprises rate converter, and it is coupled in the data output end and the timing generator of imager, in order to receiver, video clock signal and the signal that is synchronized with the imager clock signal.Described rate converter receives the imager data with the speed that is synchronized with the imager clock rate and with video clock speed output video data.
In the preferred embodiment of imaging system, described imager comprises pel array, the pixel data of the image that its maintenance expression imager is caught.Described pel array has first and second portion, and the sequence that described timing generator generates timing signal is skipped the second portion of pel array with the control imager and with the first of pel array from the imager clock control to rate converter.Described timing generator can generate horizontal timing pulse and vertical commutator pulse, and the horizontal timing pulse will be equivalent to the imager clock rate.Described imager clock signal and video clock signal are for being asynchronous each other.The first of described pel array can comprise the valid pixel of expectation, and the second portion of described pel array can comprise invalid optical black reference and dummy pixel.More specifically, the second portion of described pel array can comprise the valid pixel that do not expect to have and the combination of inactive pixels, and first can comprise the valid pixel of the expectation of pel array.Imager can be the ccd sensor of following type, and promptly wherein: by imager is the pixel of pel array and stored charge.The electric charge that is associated with the second portion of pel array can corresponding multirow group and shift out from imager simultaneously.For example, one or more levels can be controlled the accumulation of electric charge in the translator unit of imager with vertical commutator pulse, and the clock of horizontal transmission is simultaneously controlled the transmission corresponding to the electric charge of the multirow pixel data that comes from imager simultaneously.
In a preferred embodiment, timing generator can comprise: the imager clock generator circuit piece of output imager clock; The video clock generator circuit block of output video clock; Main synchronization circuit block; With the imager timing logic piece that is coupled in imager clock generator and main synchronization circuit block, it is used for imager clock rate output imager clock signal.Described main synchronization circuit block preferably is coupled in video clock generator circuit block and receiver, video clock.Described rate converter preferably includes memory, is used to receive and storage comes from imager temporarily view data, also comprises the rate converter control logic.Described rate converter control logic preferably includes: be used for control data to/from the memorizer control circuit of the write and read of memory.Described memorizer control circuit is coupled in timing generator and receiver, video clock signal and is synchronized with the signal of imager clock signal.Described rate converter control logic preferably also comprises: the video timing logic, it is coupled in memorizer control circuit and timing generator and receiver, video clock signal.Described video timing logic control storage control circuit interrupts reading data from memory during the blanking interval of the video data of output.Described rate converter control logic preferably also comprises: video output maker, it is coupled in memory and video timing logic.Described video output maker receives dateout and insert the blanking data during blanking interval from memory, that suspends memory during this period reads and export with video clock speed the video data with actual pixels data and blanking data.For example can provide the output video data by the VESA standard timing or by the SMPTEHDTV standard timing.
According to a further aspect in the invention, a kind of frame rate imaging system of increase is provided, comprise the imageing sensor with pel array, described pel array comprises: invalid reference and dummy pixel, be used to one or more control input ends of the output of view data being provided and being used to receive the timing controling signal of reading.The frame rate imaging system of described increase also comprises: timing generator, its control input end to imageing sensor provide commutator pulse reading so that skip at least some inactive pixels of pel array with the control chart image-position sensor; And clock output image data from the desired part of pel array; Increase the frame rate of imageing sensor whereby effectively.
In the preferred embodiment of the frame rate imaging system that increases, described commutator pulse comprises vertical and the horizontal timing pulse, and it comprises the valid pixel of a series of continuous vertical transfer pulse to skip multirow dummy pixel in the pel array and/or reference and/or not expect.Described commutator pulse can also comprise: the vertical transfer pulse before the end of the delegation of pel array expectation part with skip this row a plurality of dummy pixels at place, end and/or with reference to and/or the valid pixel do not expected.Described imageing sensor can be the CCD imager of following type, and promptly it comprises accumulation area and the transit area that is associated with pel array.Described commutator pulse can comprise vertical and the horizontal timing pulse view data is sent to transit area from the accumulation area and is sent to subsequently beyond the imager, wherein utilize vertical commutator pulse to be sent to the untapped pixel data of multirow in the horizontal transmission zone and utilize the horizontal timing pulse with they together clock export.
According to a further aspect in the invention, provide a kind of use that the method for high definition video data is provided with the imager of low clock rate operation.Described method comprises that clock control (clocking) is from the view data of imager with imager clock rate use imager clock signal.Described method also comprises with the video clock speed greater than the imager clock rate imager data transaction is become video data.
In the preferred embodiment of described method, become video data to comprise the imager data transaction: in memory, to cushion view data.With the imager clock rate or with the speed that is synchronized with the imager clock rate imager data are written in the memory, and from memory, read described data with different clock rate (being asynchronous to the clock rate of imager).Becoming video data preferably also to comprise the imager data transaction will be inserted in the imager data with the corresponding blanking data of the blanking interval of video data.Become video data preferably also to comprise the imager data transaction: in described insertion blanking data pause sense data from memory.Described imager clock signal is asynchronous to video data.Described video data for example can be exported by the VESA standard timing, or exports by SMPTE HDTV standard timing.
In another aspect of this invention, provide a kind of method that increases the frame rate of imager, described imager has the pel array with first and second parts.Described method comprises the second portion of skipping pel array, and utilizes imager control timing signal to come clock control to remain on to come from the view data in the first of pel array of imager.
In the preferred embodiment of described method, the second portion of skipping pel array comprises: provide a series of continuous vertical transfer pulse to skip the multirow view data in the second portion to imager.The second portion of skipping pel array can also comprise: provided vertical transfer pulse to skip the pixel at this place, row end before the delegation end of pel array.The first of pel array can comprise the valid pixel of expectation of this array and the inactive pixels of expectation, and the second portion of pel array can comprise inactive pixels and any valid pixel of not expecting.Described inactive pixels accords with the regularly blanking interval of scheme of normal video usually.For example, described normal video timing scheme can be VESA standard timing or SMPTE HDTV standard timing.Described imager can be the CCD imager, and described method can also comprise and the corresponding clock output charge of the second portion of pel array.
To understand these and other aspect of the present invention and feature by following detailed description.
Description of drawings
Fig. 1 is the block diagram according to high frame rate high definition imaging system of the present invention;
Fig. 2 is the flow chart according to the embodiment of the method that the high frame rate high definition image is provided of the present invention;
Fig. 3 is the graph type explanation that the effective and inactive pixels in the exemplary imager is shown;
Fig. 4 explanation is read the sequential chart of the example of sequential according to imager of the present invention;
Fig. 5 is that the explanation imager is read the sequential chart that the amplification of sequential is represented, the described sequential of reading is for example understood the horizontal timing pulse;
Fig. 6 is the sequential chart of another amplification expression of explanation sequential, and described sequential is for example understood horizontal timing pulse (having Φ SUB pulse);
Fig. 7 is the block diagram of the preferred embodiment of the timing generator that adopts in the imaging system of Fig. 1.
Fig. 8 is the block diagram of the preferred embodiment of the rate converter that adopts in the imaging system of Fig. 1;
Fig. 9 is the block diagram according to the embodiment of high-resolution camera of the present invention system.
Embodiment
With reference to Fig. 1, in the block diagram illustrated according to an embodiment of imaging system of the present invention.The present invention preferably adopts high-resolution imaging device 104 cheaply, and it has relatively low specified clock rate.For example, be suitable for the high-resolution of machine vision applications but the ccd image sensor of relatively low clock rate can relatively low cost on market have been bought and can be used it for imager 104.Yet, also can adopt other electronic imager cheaply, such as cmos imager.The present invention becomes higher video clock speed with relatively low clock rate with the imager data transaction and exports the video data of higher clock rate to video output device 118.As a result, the invention provides the high-resolution imaging system of the high frame rate of a kind of low cost.
More specifically, as shown in Figure 1, timing generator 100 provides first group of timing signal 102 with imager clock rate (imager clock) to imager 104.First group of timing signal makes imager 104 synchronous workings, and imager data 106 are outputed to rate converter 108 from imager 104 clocks.Timing generator 100 also provides second group of timing signal 114 with video clock speed (video clock).As will discussing in detail below, first and second groups of timing signals are normally nonsynchronous.This allows reading of optimization imager 104 and is not necessarily limited to the clock control scheme of video output device 118.This has been avoided the remarkable poor efficiency of the imager relevant with the video clock controlling schemes in reading.This allows the clock rate of imager clock 102 will be lower than the clock rate of video clock 114, thereby allows to use the imager 104 that hangs down clock rate of less expensive.Rate converter 108 typically increases clock rate and makes the clock control scheme of imager data sync in video-unit.Rate converter 108 comprises first input end of clock 120 that is coupled in imager clock 102 and the second clock input 122 that is coupled in video clock 114.With the speed that is synchronized with the imager clock rate imager data 106 are input to rate converter 108.This speed can be actual imager clock rate, or speed synchronous (integral multiple often) is in the imager clock rate, this may be because signal processing technology and inevitable difference to some extent, and described signal processing technology is such as being " the two sampling " of time adjustment that is used for the half-pix offset data of CCD cylinder (prism) system.Control logic in the rate converter 108 is stored imager data 106 temporarily and is become image field clock control scheme to convert visual domain clock control scheme to from this it with image data buffer memory.Then, from rate converter 108 data that are converted of output with as video data 116.In case imager data 106 are converted into video data 116, just the timing scheme with normal video clock rate and the application is transferred to video output device 118 with described video data 116.For example, video output device can be display, video tape recorder or other high-resolution video-unit.Video output device 118 will be typically to carry out work such as being used for the VESA (VESA) that the computer monitor type shows or being used for the timing standard of the high frame rate of high-resolution that the high definition TV quality shows SMPTE (SMPTE) standard definition of (HDTV).
With reference to Fig. 1 and 3, will the control of reading that imager 104 uses imager clock 102 be described in more detail at preferred embodiment.Described imager 104 has the pel array of the pixel data of catching the image of representing that imager is caught.The imager pixel array of typical case's imager comprises: the first and the unwanted second portion that comprise the application's desired images data.For example, the pel array of typical imager comprises valid pixel and inactive pixels.Inactive pixels comprises optical black reference pixel and dummy pixel, and these pixels typically are suitable for reading synchronously with video clock.More specifically, the standard method of reading the imager such as the CCD that is used for Video Applications relates to: level and vertical transfer pulse and the horizontal/vertical synchronization signals (this by video output device defined) synchronous with video pixel clock.Invalid optical black reference pixel and row and pseudo-position and row are provided in imager so as the optical black signal with reference to taking into account and participating in imager exported and be synchronized into normal video clock control scheme, described clock control scheme all has free time or the dead time that is associated with blanking interval.This causes the efficient of the time when clock is exported unnecessary, redundant or untapped optical black reference pixel and the dummy pixel that is built in the imager poor.In asynchronous clock controlling schemes of the present invention, these pseudo-row, dummy pixel and many reference pixels and provisional capital are unwanted.
Figure 3 illustrates this class has effectively and the specific example of the imager pixel array of inactive pixels.Fig. 3 shows the valid pixel 304 of typical CCD and the orientation and the size of optical black and dummy pixel part 302 with the top line of the image that is positioned at Fig. 3 bottom, and the direction V (vertically) and the H (level) that shift out data from imager.Excessive data 302 around the effective coverage of clock output normally 304.This excessive data 302 typically comprises the optical black reference and the pseudo-vertical pixel 308 of top line, the black reference of end row and pseudo-vertical pixel 306, the black reference and the pseudo-horizontal pixel 310 of the black reference of leading row and pseudo-horizontal pixel 312 (its must be always the row of expectation and exported) and end row by clock.Excessive data 306,308,310 and 312 can both be illustrated in quite a large amount of invalid, that do not expect, unnecessary or untapped " data " delivery times that occur during each frame period.
In the present invention, only clock output pixel array first the expectation part.Described first comprise expectation valid pixel 304, must come the part 312 of clock output and some extra invalid reference pixels randomly by being associated with those row.Described second portion comprises the combination of any valid pixel of not expecting (for example, the unwanted pixel owing to the aspect ratio of the picture of different video output) and some or all of remaining inactive pixels 302.The logic of first group of timing signal, 102 control imagers 104 is exported the first of its pel array with clock, and walks around most of second portion of pel array.Because the high speed that first group of timing signal is imager 104 is read and is optimised and asynchronous in video clock signal usually, so can utilize vertical and the non-standard sequence of horizontal transmission pulse is skipped and the corresponding pixel of not expecting of this second portion.A specific example of the timing signal that the optimization that is suitable for commercially available CCD imager reads is described at Fig. 4-5 below.Thus, the first that comes the output pixel array data with the frame rate of the nominal frame rate that is higher than imager 104 in fact is with as imager data 106.In addition, by imager manufacturer is that the specified timing that level or vertical register transmit defined may not be the most effective, for example suppose that peak pulse duration is necessary and will grow, and if in addition further frame rate increase the speech needs then this speed can off-rating and be increased to higher rate.
Next, will the work of rate converter 108 be described.Video output device 118 will have the particular video frequency timing form of particular application.The acceptable video of all these classes regularly form all has and blanking interval corresponding significant free time.As mentioned above, reading the CCD that is used for Video Applications or the standard method of cmos imager relates to: use with the synchronous level of video pixel clock and vertical transfer pulse and horizontal/vertical synchronization signals and generally use video clock signal.According to the present invention, imager 104 is not to be synchronized with this output video clock control scheme ground to carry out work.Yet, must make video output data 116 synchronizations in being the video clock controlling schemes of video output device 118 uses.This needs rate converter 108 to make the video clock controlling schemes synchronization of view data and expectation.Control logic in the rate converter and buffering memory convert imager territory clock rate the visual domain clock rate to and are video blanking interval insertion blanking data.Thus, the clock rate in (asynchronous) visual domain will become the normal video clock rate of the clock rate that is higher than in the imager territory.Be provided for video output device 118 (it can also come clock control by video clock 114) with this normal video clock rate and clock control scheme from the video data 116 of rate converter 108 clocks output.Clock control scheme in imager territory is worked again successively independently and continuously, that is to say even also be so that this has maximized speed from imager transmitted image data for the imager clock rate of appointment during the idle blanking interval of video display clock control scheme (visual domain clock).
Use the advantage of rate converter 108 to be exactly: to allow independently imager, and can understand the video clock controlling schemes better by two specific example of normal video clock control scheme.As first example, supposing has 1280 * 720p HDTV standard.The clock control scheme that is used for 720p HDTV is to formulate at the technical specification SMPTE 296M that delivers, and the disclosure thing is incorporated in this with as a reference.According to the scheme (system 1 of the table 1 of SMPTE296M) of a permission in this standard, each frame has 750 row altogether, and each row has the horizontal pixel clock of 1650 74.25MHz altogether.In addition, it also stipulates to have only 720 row to comprise effective video (or image information), and in each row of this 720 row, has only 1280 clock cycle to comprise valid pixel.In view of the above, can calculate 30 row (750 subtract 720) vision signals and not comprise image information.(for example, 1-25 is capable and 746-750 behavior blank).In addition, for each row that comprises valid pixel, the individual clock cycle of 370 (1650 subtract 1280) is synchronous or be blank time (referring to SMPTE 296M publication).Therefore, exist 1280 * 720=921600 to work the clock cycle of picture and the clock cycle of (750 * 1650)-(1280 * 720)=315900 no picture.This obtains active area efficient only is 74.47%.The vision signal of remainder relates to blanking and information synchronizing signal.Active area output during this time is " idle ".
Now for the benefit of utilizing independently imager clock control scheme and rate converter to reduce this poor efficiency is described, suppose have imaginary not with " " imager just comprises 1280 * 720 pixels to puppet " information or invalid information " ideal, and all pixels all are effective.This imager still may be with 74.25MHz clock control in addition, its have with vision signal in corresponding drive clock of blanking time in the timing crack, and synchronously be driven with vision signal thus.Now, suppose such situation, wherein: this " ideal " imager is the imager of the low clock rate of relatively low cost, and because its intrinsic physical characteristic, it for example has serious decreased performance during clock control when being higher than with 60MHz with 74.25MHz in addition, and this may can't produce spendable picture at all.Be used for clock and export the theoretic low-limit frequency of all these pixels, it is 1280 * 720 * 60 when per second 60 frames (number of pictures per second), or 55.296MHz (this is identical with the value that active area efficient multiply by video clock speed).This frequency suitably is lower than 60MHz, thereby allows imager still to be used to the video that quality is 60fps.Yet this clock is the clock that is asynchronous to the 74.25MHz of vision signal.In order to allow that the imager data are used as video data, data and outputting video signal that storage device of implementing in the rate converter 108 and data stream management make imager are synchronous again, and are added on the blanking of necessity or " free time is " in the middle of the time.Therefore, by eliminating being synchronized with the needs of poor efficiency video clock controlling schemes ground operation imager, the present invention allows to use the imager of low-cost low clock rate simply.
Another example is exactly: the VESA technical specification that is used for standard computer monitor sequential.Being used for standard computer monitor VESA technical specification regularly is the file of having delivered, and this piece file is incorporated in this with as a reference.Such standard VESA monitor regularly is that to be used for 60Hz be the monitor resolution 1024 * 768 resolution or that be used for " XGA " popularized of frequency.The clock of each frame of corresponding XGA standard adds up to 1344 * 806=1083264.Yet having only 1024 * 768=786432 in the middle of these is effective pixel data.This causes the active area time efficiency is 72.60%.Will be applied to " ideal " in the said method of XGA transducer, and can reduce the pixel clock of 60fps then from the vision signal clock rate of the 65.00MHz of regulation.Resulting clock frequency will be 1024 * 768 * 60=47.186MHz (or 65.00MHz 0.7260 times).Equally, provide the remarkable reduction of required imager clock speed aspect, thereby allowed the much lower imager of use cost.
Although these examples have all been supposed one " ideal image device ", the imager minimum timing demand of transmission that needs some extra references and fake information really and also have other in fact.This gives, and " " situation has increased poor efficiency to ideal.Yet these can both obtain handling and minimizing, and the General Result that active area efficient increases still exists, and are significant for the imager of reality.In this, previously about the argumentation of reading of imager 104 described a kind of be used for handling read and eliminate the poor efficiency that is associated with the inactive pixels of being read so that more approach the ad hoc approach of ideal image device with " ideal " imager that situation greatly differs from each other.Approach the imager of ideal (than poor efficiency) by utilization, can adopt simpler and more direct imager clock control scheme and still will obtain significant advantage.
Fig. 2 schematically illustrates the combined method that is used to provide the high frame rate high definition view data according to of the present invention.More specifically, 200, reading by imager clock 102 of imager Frame starts.202, skip data in the second portion that (not clock control) remain on the imager pixel array by suitable commutator pulse.This may comprise and utilizes vertical transfer pulse to skip the initial lines of pixel data of not expecting.204, will remain on the speed that is synchronized with the imager clock rate desired view data in the first of imager pixel array from the imager clock control to rate converter.When reading first, repeat 202 and 204 when skipping the pixel of not expecting.206, rate converter converts the imager data to video clock speed and visual domain clock control scheme from imager territory clock control scheme.208, rate converter comes clock output video numeric field data with as the video output data that is suitable for using with video clock speed.Read at imager in (202,204), 206 and 208 will continue.Video frame rate may be faster than imager frame rate, but also may be identical with the imager frame rate.In addition, imager reading method when 202 and 204 will be when its rated value increases the frame rate of imager, as mentioned above, for better imager, needn't adopt this class reading method 202,204 and all or all basically imager data to be exported by clock 204.
Next, with reference to Fig. 3-5, will describe the specific embodiment of imager readout clock controlling schemes based on the ICX204AL CCD of Sony, the described ICX204AL CCD of Sony is the imager of a kind of VESA1024 * 768 standards.This imager is poor efficiency very, and preferably may adopt above-mentioned reading method such as 202,204 (Fig. 2).For this specific imager, excessive data 302 among Fig. 3 (it has the top line of the image that is positioned at the figure bottom) comprising: the reference pixel 308 of one (1) leading pseudo-row and seven (7) leading row, the reference pixel 306 of two (2) end row, the reference pixels 310 of the pixel 312 of the leading dummy pixel of two nineteens (29) and three (3) leading reference columns (its must be always the row of expectation and exported) and 40 (40) end row by clock.(technical specification of ICX204AL CCD imager is that the public can use, and the publication of these technical specifications is incorporated in this with as a reference).Therefore, the efficient of the ICX204AL CCD system regularly of the recommendation in the operation technique standard is owing to this invalid view data is about 72.60%.The present invention uses entire frame cycle clock output active data only, is inconjunction with the least possible optical black area of clock output.This has been increased to time efficiency and approaches 100%, thereby has realized maximum frame rate with floor level transmission clock frequency.
Specifically, Fig. 4 at length shows typical sequential, has wherein skipped the lines of pixel data of not expecting at the section start of frame.V1, V2A/B and V3 represent the vertical register transmission clock, and H1 and H2 represent the horizontal register transmission clock, and RG represents reset gate platform (dock).These are equivalent to the clock control signal input pin of ICX204AL imager.The clock control scheme with the pulsewidth of recommending from XSG (frame transmission pulse).And then be that continuous V Φ transmits pulse train below, and do not have the horizontal transmission clock control.These all will be capable 308 by any pseudo-position and optical black, and the first capable video is put in the horizontal displacement register of CCD.The pulsewidth that XSG and V Φ transmit pulse can be such according to what stipulate for specific CCD, maybe can shorten to seeking the minimum value that the fastest implementation is determined with experimental technique.Thus, the required pixel during first effective video is capable is exported by clock, and vertical transfer pulse is sent out immediately, begins next line then immediately.
Figure 5 illustrates typical case's timing of other corresponding subsequent rows, wherein SUB represents base clock.Note, illustrate in greater detail the pulsewidth among Fig. 5, so that outstanding horizontal clock H1 and H2 are in the timing pause of the single vertical transfer pulse sequence of clock V1, V2 and V3.Repeat this to the last one effectively last necessary valid pixel of row by clock output till, in the time will sending XSG immediately, begin this cycle period and do not have time delay.Just will pass through the frame period of single exposure.
Another feature of the present invention relates to: handle the residual charge that is associated with the second portion of pel array.During the exposure cycle of imager 104, second part of not expecting of pel array will still be gathered the electric charge that need delete from imager, maybe will destroy the electric charge of resulting image.Typically, when at exposure cycle end end exposure, the electric charge that comes from the array of photodiode (collection region) is sent in the middle of the parallel array (transit area) of analog storage locations.Transit area uses shift-register circuit to receive regularly and transmits pulse so that transmit electric charge at inter-stage, and finally leaves register.As mentioned above, to shift out be the second portion of walking around pel array to normal electric charge.Multirow or the pixel group that the present invention is associated with the second portion of pel array by combination in transit area also shifts out imager 104 with them and overcomes the potential problems that electric charge gathers, and saved the time thus.More specifically, this residual charge of sending out may be corresponding to the initiation sequence of the horizontal transmission pulse shown in the Figure 4 and 5 after the vertical transfer pulse sequence.In case in each image duration, these vertical transfer pulse just will be sent to all lines of pixel data of not expecting in the translator unit of CCD, the translator unit of described CCD is then by the clock output simultaneously in addition of the sequence of one or more horizontal transmission pulse H1 and H2, thereby eliminates electric charge.In addition, the present frame of the previous frame of the last row do not expected and initial row can be combined and carry out clock output together.Equally, as shown in Figure 5, desired place, lines of pixel data end has the pixel of not expecting all can be moved to together in the translator unit of CCD and by in addition clock output of a series of horizontal transmission pulses of next line section start.Various other execution mode that can provide this residual charge to transmit for different specific CCD imager designs.
Another feature of the present invention relates to: handle Φ SUB or " electronic shutter " pulse, it wipes electric charge in the accumulation area of CCD or imager to reduce accumulation or time for exposure, and this is useful under the situation of high light intensity, thereby can cause saturated output.With reference to Fig. 6, preferable methods is to send the Φ SUB pulse that is synchronized with V Φ sequence.If as shown in Figure 6, wish that (2 specified microsecond width) Φ SUB pulse exceeds the time of V Φ sequence, can make horizontal pulse by the hold off of timing (held off) then, do not destroy dateout to keep Φ SUB pulse.Another kind of potential method can be to suspend the horizontal transmission pulse sending Φ SUB pulse Anywhere in the imager output stream of the definite time for exposure that expectation is provided, and is not only during V Φ sequence.
Next with reference to Fig. 7, the preferred embodiment of timing generator 100 has been described in block schematic form.Described timing generator 100 comprises that () video clock 700 for example, SMPTE or VESA standard, it provides the video clock signal on the line 716 for the video standard that is synchronized to expectation.Imager clock 702 provides the independent imager clock signal on the line 710.The imager clock signal is offered imager timing logic 706.Imager timing logic 706 generates the sequence (with reference to Fig. 1) of the timing signal that is used to read imager 104, and these timing signals all provide as first group of timing signal 102.For example, imager timing logic 706 can be created on the sequence of the timing signal of explanation among Fig. 4-5 for the described ICX204AL CCD of Sony imager.Although the imager clock is asynchronous in video clock usually, make the imager data sync in video in order to utilize rate converter 108, desirable is the reference clock with basis.This is provided by main synchronization circuit block 704.This circuit block will preferably adopt the highest available clock rate, and described clock rate can be the video clock in the major applications.Therefore, as shown in the figure, main synchronization circuit block provides synchronizing signal along line 708 receiver, video clocks and along line 712 and 714.Signal along line 712 is that imager timing logic 706 is used for making selected imager clock edges and synchronization signal/video clock to align, and preferably realizes as each frame " frame synchronization " once.Along with exporting together along the video clock signal of line 716 along the synchronizing signal of line 714 with as second group of above-mentioned clock signal 114.
With reference to Fig. 8, for example understand the preferred embodiment of rate converter 108.As shown in the figure, described rate converter comprises memory 800, it receives imager data 106 and its adhoc buffer is arrived the video clock controlling schemes to allow the imager data syncization, and the rate converter control logic comprises circuit block 802,804 and 806 in the embodiment of certain illustrated.Memory 800 can be any suitable memory, such as RAM independently, perhaps can be incorporated in memory available in the video output device.In addition, memory 800 can have and equals the entire video data frame or less than the capacity of video data frame, as long as can provide seamless video output by rate converter 108.Data are to/reading in and reading by memorizer control circuit piece 802 and control from memory 800.This circuit block had not only received imager clock 102 but also receiver, video clock 114, and with the speed that is synchronized with imager speed described data clock was controlled in the memory 800 and with asynchronous video speed and to carry out clock output.So that fill the blanking time that is associated with particular video frequency timing form, the data transaction that will export from memory 800 becomes video format by inserting suitable blanking data for video output maker 804 and video timing logic 806.During this blanking cycle, video timing logic 806 provides control signal 808 to interrupt actual pixels data reading from memory 800 to circuit block 802.The result is, can be to come output video data 116 than view data 106 higher clock rates.In addition, to make video data 116 be synchronized to the video output clock control scheme of expectation, comprise the blanking interval of blanking data, and can not make imager data 106 be synchronized to this scheme, and can not comprise will clock control puppet or reference pixel data in the rate converter 108.
Fig. 9 is the block diagram as the embodiment of the system of Fig. 1 of high-resolution camera.System synchronization is from timing generator 100.Timing generator 100 provides first group of timing signal 102 (CCD clock signal) to CCD 104, so that CCD 104 timing function synchronizations, described timing function is such as being vertical clock, horizontal clock and RG clock.Then, CCD 104 outputs comprise the signal of encode video image 106 of reference voltage and data voltage.These voltages are present in output in each horizontal clock pulse output of CCD 104.Signal 906 is fed to relevant two samplers 908, and the described pair of sampler comes computed image signal 910 by the reference voltage and the data voltage of comparison signal 906.Optional analog processor 912 received signals 910.Analog processor 912 can be carried out any common analog function, such as amplification, white balance, filtration or the like.Then, the output of analog processor 912 is fed to analog to digital converter 916, described analog to digital converter is sampled with output as DID 918 to signal 914 with expected frequency.View data 918 is input to optional digital signal processor 920, and described digital signal processor can be carried out any common Digital Signal Processing function, such as the typical enhancing that realizes, filtration, conversion or the like in digital camera.Digital signal processor 920 comes the view data 922 handled to rate converter output with the speed of the CCD clock signal that is synchronized with timing generator 100, and described rate converter comprises rate converter control logic 924 and memory 926.Described memory 926 can comprise the RAM piece, and described RAM piece is controlled by control logic 924 in logic, and it is coupled in this control logic via data/address bus 928.RAM piece 926 comes work as data buffer when logic 924 converts the view data 922 that is received to be synchronized with video clock speed 114 video output data 923 with the CCD clock rate.Therefore, RAM piece 926 all is with carrying out work with the method as previous rate converter 108 in greater detail with control logic 924.
Then, can make other optional processing of dateout 923 experience digital signal processors 932.At this moment, depend on whether want it is used in numeral or the simulation camera, the video data 934 that comes from processor 932 can be outputed to two any delegation in the data line.For numeral output, data 934 flow to digit driver 936, and it is exaggerated and is coupled in numeral output 938 therein.For simulation output, data 934 at first flow to digital to analog converter 940.After conversion, amplify described video data and it is coupled in simulation output 944 by analog driver 942.
So the execution mode of Fig. 9 provides the high-resolution camera of the high frame rate of a kind of low cost, it can be used in HDTV or other high-resolution applications.
According to top described, what will recognize that is, the invention provides a kind of imaging system and method, and it has adopted low-cost imager to come to generate video with the frame rate faster than manufacturer defined, until the standard that reaches per second 60 frames, can also exceed this standard in case of necessity.The present invention also provides a kind of electronic imager, and its use helps the most effective clock control method of data output, increases its frame rate whereby.The present invention also provides a kind of data synchronization system and method for making when the imager clock rate is asynchronous to the video outputting standard.The present invention also provides a kind of system and method, and it is used to adopt the HD CCD of standard or other imager and by eliminating free time, walking around the unnecessary clock control of not using row and pixel and use and help the mode of the efficient clock control method of data output to carry out clock control.The present invention also provides a kind of system and method that is used for eliminating the residual data electric charge of being walked around and do not send out from imager.The present invention also provides a kind of low cost, high-quality, high-resolution video camera, and it is particularly suitable for use in the middle of medical science, industry, amusement, scouting and the broadcasted application.Those skilled in the art will appreciate that others of the present invention and feature.
Though when having described different embodiments of the invention, will it will be apparent to those of ordinary skill in the art that a lot of embodiment and the execution mode that fall in the scope of the invention all are possible.Should be appreciated that under the situation that does not break away from spirit of the present invention, shown in can making within the scope of the claims and described ad hoc structure on this variation.In addition, although because of the reason of grammer flowability and soon describe described equipment and method with functional explanation, but should obviously be understood that, unless specially use " be used for ... device " such term, otherwise according to 35USC 112 final stages, should not understand claim become " device " structure or ", and step is " last limited.In addition, according to the judicial criterion of equivalence, at this without any thing will limit or the withdraw a claim abundant scope of the implication that requires or the equivalent scope of restriction claim.
Claims (27)
1. imaging system comprises:
Timing generator, it provides imager clock signal with imager clock rate and the video clock signal that has greater than the video clock speed of this imager clock rate;
Imager, it has imager input end of clock and the data output end that receives described imager clock signal; With
Rate converter, it is coupled in the described data output end and the described timing generator of described imager, in order to receiving described imager clock signal and described video clock signal, described rate converter receives the imager data with the speed that is synchronized with described imager clock rate and with described video clock speed output video data.
2. imaging system according to claim 1, wherein said imager comprise the pel array of the pixel data of the image that this imager of maintenance expression is caught, and described pel array has first and second portion.
3. imaging system according to claim 2, wherein said timing generator generate the timing signal sequence and skip the described second portion of described pel array and the described first of the described pel array from described imager to described rate converter is carried out clock control to control described imager.
4. imaging system according to claim 3, wherein said timing generator generates horizontal timing pulse and vertical commutator pulse, and wherein said horizontal timing pulse is corresponding to described imager clock rate.
5. imaging system according to claim 1, wherein said imager clock signal and video clock signal are asynchronous each other.
6. imaging system according to claim 3, the described first of wherein said pel array comprises the valid pixel of expectation.
7. imaging system according to claim 6, the described second portion of wherein said pel array comprises inactive pixels or dummy pixel.
8. imaging system according to claim 3, the described second portion of wherein said pel array comprise the valid pixel do not expected and the combination of inactive pixels, and described first comprises the valid pixel of the expectation of described pel array.
9. imaging system according to claim 3, wherein said imager is a ccd sensor, and by described imager is the pixel of described pel array and stored charge, and wherein the described electric charge that is associated with the described second portion of described pel array side by side shifts out from described imager, wherein, the group of the multirow that is associated with the described second portion of described pel array is combined.
10. imaging system according to claim 9, wherein one or more levels and the accumulation of vertical commutator pulse control electric charge in the translator unit of described imager, and the transmission corresponding to the electric charge of the multirow pixel data that comes from described imager is controlled in described horizontal timing pulse simultaneously.
11. imaging system according to claim 1, wherein said timing generator comprises:
The imager clock generator circuit piece of output imager clock;
The video clock generator circuit block of output video clock;
Main synchronization circuit block; With
Be coupled in the imager timing logic piece of described imager clock generator and main synchronization circuit block, it is used for exporting described imager clock signal with described imager clock rate.
12. imaging system according to claim 11, wherein said main synchronization circuit block are coupled in described video clock generator circuit block and receive described video clock.
13. imaging system according to claim 1, wherein said rate converter comprises memory, is used to receive and storage comes from described imager temporarily view data, also comprises the rate converter control logic.
14. imaging system according to claim 13, wherein said rate converter control logic comprise be used for control data to/from the memorizer control circuit of the write and read of memory.
15. imaging system according to claim 14, wherein said memorizer control circuit are coupled in described timing generator and receive the signal that is synchronized with described imager clock signal and described video clock signal.
16. imaging system according to claim 15, wherein said rate converter control logic also comprises: the video timing logic, it is coupled in described memorizer control circuit and described timing generator and receives described video clock signal, and wherein said video timing logic is controlled described memorizer control circuit and interrupted reading data from described memory during the blanking interval of the video data of output.
17. imaging system according to claim 16, wherein said rate converter control logic also comprises: video output maker, it is coupled in described memory and described video timing logic, wherein said video output maker receives the output video data and insert the blanking data during blanking interval from described memory, suspends the video data of reading and having actual pixels data and blanking data with the output of video clock speed of memory during this period.
18. imaging system according to claim 17 wherein provides described output video data by the VESA standard timing.
19. imaging system according to claim 17 wherein provides described output video data by SMPTE HDTV standard timing.
20. a use provides the method for high definition video data with the imager of lower clock rate work, comprising:
Use the imager clock signal to come the view data of clock control with the imager clock rate from imager; And
With video clock speed described imager data transaction is become video data greater than described imager clock rate.
21. method according to claim 20 wherein becomes described imager data transaction video data to comprise the described view data of buffering in memory.
22. method according to claim 21, wherein described imager data transaction is become video data to comprise that also the speed to be synchronized with described imager clock rate is written to view data in the described memory, and from described memory, read described data with different clock rates.
23. method according to claim 22, wherein described imager data transaction being become video data also to comprise will be inserted in the described imager data with the corresponding blanking data of the blanking interval of described video data.
24. method according to claim 23 wherein becomes described imager data transaction video data also to be included in described insertion blanking pixel data pause sense data from described memory.
25. method according to claim 20, wherein said imager clock signal and described video clock signal are asynchronous each other.
26. method according to claim 25, wherein said video data is exported by the VESA standard timing.
27. method according to claim 25, wherein said video data is exported by the SMPTEHDTV standard timing.
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| US60/452,646 | 2003-03-07 | ||
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| CN110248102B (en) * | 2019-07-22 | 2021-01-15 | 中国大恒(集团)有限公司北京图像视觉技术分公司 | Industrial camera buffering method |
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| US4910599A (en) * | 1987-03-20 | 1990-03-20 | Canon Kabushiki Kaisha | Imaging apparatus having electronic zooming with high and low speed readout |
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| US4910599A (en) * | 1987-03-20 | 1990-03-20 | Canon Kabushiki Kaisha | Imaging apparatus having electronic zooming with high and low speed readout |
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