CN100555865C - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- CN100555865C CN100555865C CNB2006101317832A CN200610131783A CN100555865C CN 100555865 C CN100555865 C CN 100555865C CN B2006101317832 A CNB2006101317832 A CN B2006101317832A CN 200610131783 A CN200610131783 A CN 200610131783A CN 100555865 C CN100555865 C CN 100555865C
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Abstract
The semiconductor device that the electricity consumption of the circuit part that the clock signal clk of using from the working at high speed of outside input drives will be lowered is provided when carrying out the low speed running under a kind of driving of the 1st clock signal clk 1 that generates in inside.Wherein, when NAND circuit 6 selected signal SEL to be high level, the signal level of the clock signal clk of input overturn, and is output in the frequency dividing circuit 2.The frequency dividing ratio of frequency dividing circuit 2 usefulness regulations generates the 2nd clock signal clk 2 with the signal of input frequency division in addition, and the input IN1 of input selection circuit 4.In addition, when NAND circuit 6 was low-level at selection signal SEL, its output rested on high level, and frequency dividing circuit 2 stops with regard to the output that makes the 2nd clock signal clk 2.
Description
Technical field
The present invention relates to a kind of semiconductor device that the clock signal that can select a signal from the clock signal of plural number is selected circuit that has.Particularly, the present invention relates to a kind of like this semiconductor device, promptly in this device, have the semiconductor device that the clock signal of selecting a clock signal from the clock signal of a plurality of PLL of being input to circuit is selected the economize on electricity of circuit.
Background technology
As prior art, for example have, Japan Patent open (spy opens) put down into put down in writing among the 8-272478 as shown in Figure 3 from the clock signal of plural number, select a power save circuit that is used.In the circuit of Fig. 3, dispose generate and export frequency for example be 32.768KHz low speed with the low speed of clock signal CLK1 with oscillating circuit 101, generate and for example frequency of output is high speed oscillating circuit 102, selection circuit 103, CPU104, CPU peripheral circuit 105 and the clock signal control circuit 106 of the high speed of 10MHz with clock signal CLK2.
Clock signal control circuit 106 is pressed the indication of CPU104, carries clock selection signal CLKSEL to selector 103, and allows selector 103, and output low speed clock signal CLK1 exports high speed clock signal CLK2 when working at high speed when low speed operate.In addition, clock signal control circuit 106 is being chosen as selected signal SYSCLK with low speed with clock signal CLK1 and with the occasion of its output, oscillation control signal CLK2BEN0 makes at a high speed and decommissions with oscillating circuit 102.Further, when clock signal control circuit 106 will be chosen as selection signal SYSCLK with clock signal CLK2 at a high speed and it is exported, oscillation control signal CLK1BEN0 made low speed decommission with oscillating circuit 101.So, do not have selecteed oscillating circuit to stop action, just can make the current drain step-down of oscillating circuit self by making.
Summary of the invention
But, be from the semiconductor device of outside input only having the low speed clock signal that working at high speed is used with oscillating circuit, the partial circuit that the clock signal of being imported by the outside drives will operate always.Thus, only use even do not need working at high speed from itself with the occasion that operates with the clock signal of oscillating circuit output of low speed, the problem of the power consumption of the partial circuit that drives by the clock signal that outside input also can take place.
The present invention produces in order to overcome the above problems.Purpose of the present invention just provides a kind of can making in the clock signal that is produced by inside and drives and when operating, the semiconductor device that the power consumption of the partial circuit that is driven with clock signal by the working at high speed of outside input reduces.
Content of the present invention will be narrated following.
A kind of semiconductor device wherein, is used for selecting a clock signal to be used from first clock signal of plural number and second clock signal, it is characterized in that, it comprises,
The vibration oscillating circuit of first clock signal of generation and output regulation,
With the input external timing signal with the regulation frequency dividing ratio carry out frequency division and with its frequency dividing circuit of exporting as the second clock signal,
According to the output control circuit of control signal to controlling to the output of frequency dividing circuit from the external timing signal of outside input from the outside input, and
Make either party to above-mentioned first clock signal or second clock signal exclusively select the selection circuit of exporting according to above-mentioned control signal;
The control signal that said external is imported so is input to above-mentioned output control circuit, promptly to make the clock signal of winning transport to above-mentioned selection circuit, and a control signal that said external is come is input to above-mentioned input/output control circuit, and above-mentioned output control circuit stops to the output of aforementioned frequency dividing circuit with regard to making the said external clock signal.
In addition, the control signal that said external is come so is input to above-mentioned output control circuit, promptly to make the second clock signal transport to above-mentioned selection circuit, and a control signal that above-mentioned outside is come so is input to above-mentioned control circuit, and above-mentioned output control circuit just makes the said external clock signal transport to aforementioned frequency dividing circuit.
Another kind of semiconductor device of the present invention, this device are used for selecting a clock signal to be used from first clock signal and second clock signal, it is characterized in that it comprises
The oscillating circuit of first clock signal of generation and output regulation,
Will from the external timing signal of outside input with the frequency dividing ratio of regulation carry out frequency division and with its frequency dividing circuit of exporting as the second clock signal and
According to the selection circuit of from the control signal of outside input the either party of described first clock signal or second clock signal exclusively being selected to export;
The control signal of said external input is input to described selection circuit, make the clock signal output of winning, and as long as one import described selection circuit with the control signal of said external input, described frequency dividing circuit makes the output of above-mentioned second clock signal stop with regard to decommissioning.
The control signal that said external is come so is input to described selection circuit, promptly to make the output of second clock signal, and as long as a control signal that said external is come so is input to described selection circuit, described frequency dividing circuit just makes the second clock signal generate and output.
In addition, the frequency height of above-mentioned first clock signal of the frequency ratio of described external timing signal.
Described semiconductor device disposes the PLL circuit, and the clock signal of described selection circuit output is used as input clock signal and imports this PLL circuit.
Semiconductor device of the present invention, be that the control signal that said external is come is so imported, promptly will make first clock circuit import described selection circuit, and a control signal that said external is come so imports, the clock signal that said external is come just stops to export to frequency dividing circuit.Thus, just can only dispose the oscillating circuit of first clock signal of the clock signal that generation uses as low speed, and be to supply with from the outside of semiconductor device as the external timing signal of the clock signal of high speed usefulness.Even under this occasion, do not using external timing signal, and be to use the clock signal that produces by inside to drive and when carrying out the low speed running, just stop external timing signal being carried out the frequency dividing circuit running of frequency division.So, the power consumption of the partial circuit that is driven with clock signal by the working at high speed of outside input will be reduced significantly.
For example in the system of mobile phone etc., the clock signal of high speed usefulness is in radio-circuit and pay attention to using in the sound circuit of sound effect usually.But in the occasion that radio-circuit does not operate, when perhaps sound circuit operated under not too paying attention to the sound effect occasion, just becoming with clock signal did not at a high speed need, as long as and the clock signal that has low speed to use.Under this occasion, according to the present invention, the electric power of being consumed by the circuit that drives with clock signal at a high speed just can lower.
In addition, the control signal that said external is come so is input to above-mentioned selection circuit, promptly will make the output of first clock signal, and a control signal that said external is next is so imported described selection circuit, just decommission, the output of above-mentioned second clock letter is stopped.In this case, also can obtain and above-mentioned same effect.
Description of drawings
Fig. 1 is the structural representation of the semiconductor device of the first embodiment of the present invention.
Fig. 2 is the structural representation of the semiconductor device of the second embodiment of the present invention.
Fig. 3 is the structural representation of the semiconductor device of prior art.
Embodiment
Embodiment 1
Fig. 1 is the structural representation of the semiconductor device of the first embodiment of the present invention.
In the semiconductor device of Fig. 1, the terminal X1 and the X2 that are connected usefulness with the outside couple together the quartz crystal 11 between it; On the terminal T1 of usefulness that the selection signal SEL from the outside is imported into and continue in the outside; The clock signal clk that comes from the outside is imported into the outside and continues with on the terminal T2.
Semiconductor device 1 comprises frequency dividing circuit 2, oscillating circuit 3, selects circuit 4, PLL circuit 5 and NAND circuit 6.And, select signal SEL to constitute control signal; Clock signal clk constitutes external timing signal; NAND circuit 6 constitutes output control circuit.Semiconductor device 1 is integrated among the IC.
In the oscillating circuit 3, continue and join with terminal X1 in input Xi1 and outside; Continue and join with terminal X2 in input Xi2 and outside.Oscillating circuit 3 is that crystal vibration is encouraged, and makes it produce first clock signal clk 1, and it is transported to the input IN2 that selects circuit 4.The frequency of quartzy vibration is the low frequency of about 32.8kHz.This frequency becomes the frequency of first clock signal clk 1.In addition, first clock signal clk 1 also can be used as real-time clock (RTC).Be input to the selection signal SEL that continues with terminal T1 the outside from the outside and transported to an input end of NAND circuit 6 and the input SE that selects circuit respectively.Continue from the outside and to be passed to another input of NAND circuit with the clock signal clk of terminal T2 input.The frequency of clock signal clk is compared with the first clock signal clk I and is wanted high many, for example can be 20MHz.
When selecting signal SEL to be high level (High Level), NAND circuit 6 overturns the signal level of the clock signal clk of input, and it is passed in the frequency dividing circuit 2.The frequency dividing ratio of frequency dividing circuit 2 usefulness regulations generates the signal of input frequency division in addition the 2nd clock signal clk 2, and it is passed to the input IN1 that selects circuit 4.In addition, when selecting signal SEL to be low-level (LowLevel), NAND circuit 6 makes its output be high level always.Frequency dividing circuit 2 stops the output of the 2nd clock signal clk 2.
When selecting signal SEL to be high level, select circuit 4 to make the 2nd clock signal clk 2 that is input to input IN1 transport to PLL circuit 5; When to select signal SEL be low-level, the 1st clock signal clk 1 of selecting circuit 4 will be input to input IN2 was transported to PLL circuit 5.
That is, when the 1st clock signal clk 1 selected signal SEL selected, NAND circuit 6 did not make outside input clock signal CLK transport to frequency dividing circuit 2.So frequency dividing circuit 2 does not operate, thereby reach the purpose of economize on electricity.So, when carrying out the low speed running under the driving of the 1st clock signal clk 1 that generates in inside, the power consumption of the partial circuit of using from the working at high speed of outside input that clock signal clk drove will be lowered.
In addition, be when constituting at semiconductor device by CMOS, the consumption electric power of circuit is directly proportional with running speed, so the consumption electric power of the frequency dividing circuit 2 that is operated by the high-frequency clock signal as clock signal clk can become very big.So the present invention can reach very big power savings.
In addition, in Fig. 1, the 1st clock signal clk 1 has the RTC function, so even selecting circuit 4 to select the occasion of the 2nd clock signal clk 2, oscillating circuit 3 also can operate.But, the frequency of oscillating circuit 3 as described above, only be about clock signal clk frequency 1/600th, the consumption electric current of oscillating circuit 3 is compared minimum with frequency dividing circuit 2, therefore, the current loss that produces owing to the running of oscillating circuit 3 can not become problem.
In aforesaid embodiment 1, because when the 1st clock signal clk 1 was selected, clock signal clk was not input in the frequency dividing circuit 2, so can reduce the electric power that frequency dividing circuit 2 is consumed.But frequency dividing circuit 2 also can decommission by the input initiating signal.The second embodiment of the present invention that Here it is.
Fig. 2 is the structure chart of the semiconductor device of the 2nd embodiment of the present invention.In addition, in Fig. 2, represented with same symbol with the part that Fig. 1 is same, and omitted its explanation.Only be illustrated at this with regard to the part different among Fig. 2 with Fig. 1.
The difference of Fig. 2 and Fig. 1 is to have saved NAND circuit 6, and appended turner (inverter) 15, and disposed initiating signal input EN on the frequency dividing circuit 2 of Fig. 1, as importing low-level signal at this initiating signal input, the running of frequency dividing circuit 2 will stop.Thus, the frequency dividing circuit 2 with Fig. 1 becomes 2a; Semiconductor device 1a is made in semiconductor device 1 change of Fig. 1.
In Fig. 2, semiconductor device 1a comprises frequency dividing circuit 2a, oscillating circuit 3, selects circuit 4, PPL circuit 5 and turner 15.In addition, semiconductor device 1a is integrated among the IC.
The selection signal SEL that imports with terminal T1 that continues from the outside is passed to the initiating signal input EN of frequency dividing circuit 2a and the input SE that selects circuit 4 respectively.The clock signal clk of importing with terminal T2 that continues from the outside is that media is passed to the frequency dividing circuit 2a with turner 15.
When selecting signal SEL to be high level, frequency dividing circuit 2a running.With turner 15 be the clock signal clk that is transfused to of media by frequency division with the frequency dividing ratio of regulation, and be transported to the input IN1 that selects circuit 4 as the 2nd clock signal clk 2.And when to select signal SEL be low-level, thereby frequency dividing circuit 2a decommissions and does not consume electric current.So, just can reach the purpose that reduces frequency dividing circuit 2a institute consumed current amount.
That is, when selecting signal SEL to select the 1st clock signal clk 1, frequency dividing circuit 2a does not operate, thereby can reduce the electric current consumption of frequency dividing circuit 2a.Thus, just can obtain the effect identical with embodiment 1, when promptly carrying out the low speed running under the driving of the 1st clock signal clk 1 that generates in inside, the power consumption of the partial circuit that is driven by the clock signal clk of using from the working at high speed of outside input will be lowered.
Claims (6)
1. semiconductor device is used for selecting a clock signal to be used from first clock signal and second clock signal, it is characterized in that, it comprises,
The oscillating circuit of first clock signal of generation and output regulation,
With the input external timing signal with the regulation frequency dividing ratio carry out frequency division and with its frequency dividing circuit of exporting as the second clock signal,
According to the output control circuit of control signal to controlling to the output of frequency dividing circuit from the external timing signal of outside input from the outside input, and
According to above-mentioned control signal the either party of above-mentioned first clock signal or second clock signal is exclusively selected the selection circuit exported;
The control signal of said external input is input to above-mentioned output control circuit, make the clock signal of winning transport to above-mentioned selection circuit, and a control signal that said external is come is input to above-mentioned output control circuit, and above-mentioned output control circuit stops to the output of aforementioned frequency dividing circuit with regard to making the said external clock signal.
2. semiconductor device according to claim 1, it is characterized in that, the control signal of said external input is input to above-mentioned output control circuit, make the second clock signal transport to above-mentioned selection circuit, and a control signal with above-mentioned outside input is input to above-mentioned control circuit, and above-mentioned output control circuit just makes the said external clock signal transport to aforementioned frequency dividing circuit.
3. semiconductor device, this device are used for selecting a clock signal to be used from first clock signal and second clock signal, it is characterized in that it comprises
The oscillating circuit of first clock signal of generation and output regulation,
Will from the external timing signal of outside input with the frequency dividing ratio of regulation carry out frequency division and with its frequency dividing circuit of exporting as the second clock signal and
According to the selection circuit of from the control signal of outside input the either party of described first clock signal or second clock signal exclusively being selected to export;
The control signal of said external input is input to described selection circuit, make the clock signal output of winning, and as long as one import described selection circuit with the control signal of said external input, described frequency dividing circuit makes the output of above-mentioned second clock signal stop with regard to decommissioning.
4. semiconductor device according to claim 3, it is characterized in that the control signal of said external input is input to described selection circuit, make the second clock signal export, and as long as a control signal that said external is come is input to described selection circuit, described frequency dividing circuit just makes the second clock signal generate and output.
5. according to claim 1,2,3 or 4 described semiconductor devices, it is characterized in that the frequency height of above-mentioned first clock signal of the frequency ratio of described external timing signal.
6. according to claim 1 or 3 described semiconductor devices, it is characterized in that disposing the PLL circuit, the clock signal of described selection circuit output is used as input clock signal and imports this PLL circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP305251/05 | 2005-10-20 | ||
| JP2005305251A JP2007114989A (en) | 2005-10-20 | 2005-10-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1956332A CN1956332A (en) | 2007-05-02 |
| CN100555865C true CN100555865C (en) | 2009-10-28 |
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ID=38063473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101317832A Expired - Fee Related CN100555865C (en) | 2005-10-20 | 2006-10-12 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2007114989A (en) |
| CN (1) | CN100555865C (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08255034A (en) * | 1995-03-17 | 1996-10-01 | Hitachi Ltd | Low power consumption type data processor |
| JPH11143574A (en) * | 1997-11-10 | 1999-05-28 | Nec Ic Microcomput Syst Ltd | Clock generation circuit and clock generation method |
| JP2000207381A (en) * | 1999-01-20 | 2000-07-28 | Mitsubishi Electric Corp | Reset device for microcomputer |
| KR100420116B1 (en) * | 2000-08-31 | 2004-03-02 | 삼성전자주식회사 | Circuit and method for generating processor clock for low power consumption cdma modem chip design |
| JP2003303887A (en) * | 2002-04-09 | 2003-10-24 | Matsushita Electric Ind Co Ltd | Integrated circuit |
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2005
- 2005-10-20 JP JP2005305251A patent/JP2007114989A/en active Pending
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2006
- 2006-10-12 CN CNB2006101317832A patent/CN100555865C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007114989A (en) | 2007-05-10 |
| CN1956332A (en) | 2007-05-02 |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: RICOH MICROELECTRONICS CO., LTD. Free format text: FORMER OWNER: RICOH CO. LTD. Effective date: 20150403 |
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| TR01 | Transfer of patent right |
Effective date of registration: 20150403 Address after: Osaka Patentee after: Ricoh Microelectronics Co., Ltd. Address before: Tokyo, Japan, Japan Patentee before: Ricoh Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091028 Termination date: 20151012 |
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| EXPY | Termination of patent right or utility model |