CN100555204C - Storage arrangement and relevant memory module, Memory Controller and method thereof - Google Patents

Storage arrangement and relevant memory module, Memory Controller and method thereof Download PDF

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Publication number
CN100555204C
CN100555204C CNB2005100913311A CN200510091331A CN100555204C CN 100555204 C CN100555204 C CN 100555204C CN B2005100913311 A CNB2005100913311 A CN B2005100913311A CN 200510091331 A CN200510091331 A CN 200510091331A CN 100555204 C CN100555204 C CN 100555204C
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data
integrated circuit
mode register
signal
memory devices
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CN1722078A (en
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李起薰
庆桂显
俞昌植
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A kind of memory module that comprises a plurality of storage arrangements.The method of control store module, it is included in during the mode register setting operation, and by instruction/address bus, to each integrated circuit memory devices, the register that supplies a pattern is provided with instruction from Memory Controller.By signal line, first one of from the Memory Controller to the integrated circuit memory devices provides inhibit signal that the execution of instruction is set with the mode register of forbidding first integrated circuit memory devices.By signal line, one of from the Memory Controller to the integrated circuit memory devices second provides enable signal that the execution of instruction is set with the mode register that enables second integrated circuit memory devices.And during the mode register setting operation, described inhibit signal does not offer second integrated circuit memory devices, and described enable signal does not offer first integrated circuit memory devices.Discussed relevant system, device and additional method simultaneously.

Description

Storage arrangement and relevant memory module, Memory Controller and method thereof
The cross reference of related application
The application is 10/199 as the application number of application on July 19th, 2002, the part continuity application of 857 U.S. Patent applications also requires its right of priority, and it is the right of priority of 10-2001-0043789 Korean application that above-mentioned U.S. Patent application requires the application number of application on July 20 calendar year 2001.It is the right of priority of 10-2004-0032500 Korean application that the application also requires the application number of application on May 8th, 2004.Laid-open U.S. Patents application 10/199,857, Korean application 10-2001-0043789, and therefore Korean application 10-2004-0032500 is here merged as a reference in full.
Technical field
The present invention relates to the electronic device field, particularly relate to electronic memory device, memory module, Memory Controller, and relevant method
Background technology
In the number storage system, Memory Controller 10 may command comprise the operation of the memory module 20 of a plurality of storage arrangements 30 that are designated M1-M9 respectively.More specifically, each storage arrangement 30 can be the integrated circuit dynamic random access memory means.
Utilize independent data signal bus circuit, data-signal DATA1-DATA9 can be in Memory Controller 10 and independent 30 transmission of storage arrangement.During read operation, by independent data bus line, can simultaneously data-signal DATA1-DATA9 be read the Memory Controller 10 from storage arrangement M1-M9, and during write operation, can simultaneously data-signal DATA1-DATA9 be write the storage arrangement M1-M9 from Memory Controller.In addition, between Memory Controller 10 and each storage arrangement M1-M9, be provided for the independent circuit and the independent circuit that is used for data mask (mask) signal DM1-DM9 of data strobe signal DQS1-DQS9.Therefore, data-signal DATA1-DATA9, data strobe signal DQS1-DQS9, and the propagation delay of data mask DM1-DM9 between Memory Controller 10 and each storage arrangement M1-M9 is roughly the same.Layout with Fig. 1 of data bus independent between Memory Controller 10 and each storage arrangement M1-M9 can be called as to be provided point-to-point and is connected.
On the contrary, from Memory Controller 10 to each storage arrangement M1-M9, but same control/address/clock bus 12 Coupling Control/address signal CA and clock signal of system CK.Therefore, for each storage arrangement M1-M9, the length difference of clock signal C K transmission line, so that clock signal C K propagation delay is for each storage arrangement M1-M9 and difference.If storage arrangement M1-M9 along control/address/clock bus 12 is evenly spaced apart, and then may experience the propagation delay T (be also referred to as is to differ or phase shift) that increases progressively for each storage arrangement M1-M9 clock signal C K in the module.Arbitrarily propagation delay 0 is distributed to first memory device M1, for example, may be created in the clock signal C K propagation delay T of second memory device M2, may produce propagation delay 2T meeting at the 3rd storage arrangement M3, may produce propagation delay 3T at the 4th storage arrangement M4, may produce propagation delay 4T at the 5th storage arrangement M5, may produce propagation delay 5T at the 6th storage arrangement M6, may produce propagation delay 6T at the 7th storage arrangement M7, may in the 8th storage arrangement M8, produce propagation delay 7T, and may produce propagation delay 8T at the 9th storage arrangement M9.The layout that will have Fig. 1 of the clock signal C K that is provided for each storage arrangement M1-M9 is called to provide and leaps (fly-by) clock.
The data-signal DATA1-DATA9 that the Point-to-Point Data bus of read and write by separately provides can be provided for by identical systems clock signal circuit each storage arrangement to leap clock signal of system CK synchronous.But with high relatively operating speed, by Point-to-Point Data bus separately, the different memory device M1-M9 that wherein has different propagation delays provides clock signal of system CK, is difficult to the transmission of synchronized data signal DATA1-DATA9.
Fig. 2 shows and comprises nine memory modules 20 that are designated the storage arrangement 30 of M1-M9 respectively.As shown in the figure, each storage arrangement 30 comprises eight data pin PDQ1-PDQ8, data mask pin PDM, and data strobe pin PDQS, is connected respectively on the Memory Controller.As shown in the figure, data-signal DQ1-8 (DATA1 just) be provided to/from the data pin PDQ1-PDQ8 of storage arrangement M1; Data-signal DQ9-DQ16 (DATA2 just) is provided to/from the data pin PDQ1-PDQ8 of storage arrangement M2; Data-signal DQ17-DQ24 (DATA3 just) is provided to/from the data pin PDQ1-PDQ8 of storage arrangement M3; Data-signal DQ25-DQ32 (DATA4 just) is provided to/from the data pin PDQ1-PDQ8 of storage arrangement M4; Data-signal DQ33-DQ40 (DATA5 just) is provided to/from the data pin PDQ1-PDQ8 of storage arrangement M5; Data-signal DQ41-DQ48 (DATA6 just) is provided to/from the data pin PDQ1-PDQ8 of storage arrangement M6; Data-signal DQ49-DQ56 (DATA7 just) is provided to/from the data pin PDQ1-PDQ8 of storage arrangement M7; Data-signal DQ57-DQ64 (DATA8 just) is provided to/from the data pin PDQ1-PDQ8 of storage arrangement M8; And data-signal DQ65-DQ72 (DATA9 just) be provided to/from the data pin PDQ1-PDQ8 of storage arrangement M9.By data mask circuit independently, data mask signal DM1-DM9 is provided for each storage arrangement M1-M9 data mask pin PDM separately, and passing through independently data strobe circuit, data strobe signal DQS1-DQS9 is provided for each storage arrangement M1-M9 data strobe pin PDQS separately.
As used herein such, the term pin is defined as comprising the structure that inputs or outputs of any integrated circuit memory devices, and the electric connection with other devices, substrate and/or circuit board is provided.For example, the term pin can comprise: dual inline type assembling (DIP), single-row direct insertion assembling (SIP), pin grid array (PGA), the assembling of quadrilateral low profile (quad small outline package, QSOP) or the like lead-in wire; Flip-chip solder bump (solder bumps ofa flip-chip), baii grid array, or the like; Wire-bonded; Bond pad; Or the like.In addition, each storage arrangement M1-M9 comprises a plurality of clock/instructions/address pin PCA, and it is coupled on identical clock/instruction/address bus 12.Clock signal of system CK and instruction/address signal CA is passed through clock/instruction/address bus 12, offers clock/instruction/address pin of storage arrangement M1-M9.By the memory location of clock/address signal define storage device M1-M9 that instruction/address bus 12 is transmitted, data-signal DATA1-DATA9 will be written to this storage arrangement or read from this storage arrangement.More particularly, address signal can define memory bank (bank) address and row/column address.Storage arrangement for example, can comprise four memory banks of memory cell, and each memory bank can be operated independently with the row and column address of selecting.
Operation by the command signal define storage device M1-M9 execution that clock/instruction/address bus 12 is transmitted.The instruction of command signal definable, for example capable effective instruction (ACTIVE), read instruction (READ), write command (WRITE), refreshing instruction (REF), cut-offing instruction (PWDN), mode register are provided with instruction (MRS), or the like.The instruction pin can comprise clock enable pin, chip selection pin, row address strobe pin, column address strobe pin, and writes enable pin.Fig. 3 A shows the synoptic diagram of integrated circuit dynamic random access memory means pin, and Fig. 3 B is a chart of having described Fig. 3 A storage arrangement pin function.
Fig. 4 shows the block diagram of storage arrangement functional block.As shown in the figure, storage arrangement 30 comprises instruction decoder 34, address buffer 35, internal clock generator 36, data I/O impact damper 37, row decoder 32, column decoder 33, memory cell array 31, and sensor amplifier 38.As shown in the figure, the command signal CMD of clock/instruction/address signal CA is provided for instruction decoder 34, the address signal ADD of clock/instruction/address signal CA is provided for address buffer 35, and the clock signal of system CK of clock/instruction/address signal CA is provided for internal clock generator 36.Internal clock generator 36 produces the internal clock signal iCLK of responding system clock signal C K.
Therefore, instruction decoder 34 decoding instruction signal CMD are to determine being performed special operational (for example read operation, write operation or mode register setting operation).During the mode register setting operation, the value of writing is to the operator scheme of mode register with the define storage device.During write operation, be received in data I/O impact damper 37 from the data-signal DATA of Memory Controller, and be written to the position by the memory cell array 31 of the address signal ADD definition that receives from Memory Controller as iDATA.During read operation, the iDATA that is come by the position of the memory cell array of the address signal ADD definition that receives from Memory Controller is by data I/O impact damper 37 retrievals, and is provided for Memory Controller as data-signal DATA.As shown in Figure 4, data I/O impact damper 37 responds the iCLK signal of internal clock generators 36 generations and operates.
Fig. 5 shows the sequential chart of the read operation of the memory module 20 that comprises a plurality of storage arrangements 30, and the READ that reads instruction that wherein responds by clock/instruction/address data bus 12 receives starts read operation.Because along the different propagation delays of clock/instruction/address bus 12, clock signal of system CK can be in each storage arrangement M1-M9 same phase shift.In Fig. 5, signal CK1 is the clock signal of system CK that storage arrangement M1 receives, and signal CK5 is the clock signal of system CK that storage arrangement M5 receives, and signal CK9 is the clock signal of system CK that storage arrangement M9 receives.The internal clock signal iCLK1 that the internal clock signal iCLK5 of storage arrangement M5 comes to this with respect to storage arrangement M1 has been delayed 4T at interval, and the internal clock signal iCLK9 of storage arrangement M9 has been delayed 4T at interval with respect to storage arrangement M5 internal clock signal iCLK5.Because internal clock signal is asynchronous, and because the data I of storage arrangement/O impact damper response separately internal clock signal and operate, at the different times that produces data time lags (skew), data-signal DATA1-DATA9 comes from storage arrangement separately.As shown in Figure 5, the data-signal DATA9 that comes from storage arrangement M9 comes to this and is delayed 4T at interval with respect to the data-signal DATA5 that comes from storage arrangement M5, and the data-signal DATA5 that comes from storage arrangement M5 is delayed 4T at interval with respect to the data-signal DATA1 that comes from storage arrangement M1.During write operation, the operating speed of data time lag meeting limits storage module.
Fig. 6 is the write operation sequential chart that the memory module 20 that comprises a plurality of storage arrangements 30 has been described, wherein response starts write operation by the write command WRITE that clock/instruction/address data bus 12 receives.Because along the different propagation delays of clock/instruction/address bus 12, clock signal of system CK can be in each storage arrangement M1-M9 same phase shift.In Fig. 6, signal CK1 is the clock signal of system CK that storage arrangement M1 receives, and signal CK5 is the clock signal of system CK that storage arrangement M5 receives, and signal CK9 is the clock signal of system CK that storage arrangement M9 receives.The internal clock signal iCLK1 that the internal clock signal iCLK5 of storage arrangement M5 comes to this with respect to storage arrangement M1 is delayed 4T at interval, and the internal clock signal iCLK9 of storage arrangement M9 is delayed 4T at interval with respect to the internal clock signal iCLK5 of storage arrangement M5.Because internal clock signal is asynchronous, and because the data I of storage arrangement/O impact damper response separately internal clock signal and operate, external data signal DATA1-DATA9 will be provided by Memory Controller simultaneously, but at the different times that produces the data time lag, internal data signal iDATA1-iDATA9 will be produced by data input/output (i/o) buffer separately.As shown in Figure 6, the internal data signal iDATA5 that the internal data signal iDATA9 of storage arrangement M9 comes to this with respect to storage arrangement M5 is delayed 4T at interval, and the internal data signal iDATA5 of storage arrangement M5 is delayed 4T at interval with respect to the internal data signal iDATA1 of storage arrangement M1.During write operation, the operating speed of data time lag meeting limits storage module.
Summary of the invention
According to embodiments of the invention, accumulator system can comprise the instruction/address bus with a plurality of instruction/address lines, first and second integrated circuit memory devices, and Memory Controller.First integrated circuit memory devices can comprise a plurality of first instruction/address pin on the instruction/address lines that is coupled to instruction/address bus, be configured to first mode register of the information of area definition first memory device operation characteristic, and first instruction decoder.The mode register that instruction decoder can be configured to receive with the response of the enable signal that receives on first predetermined pins of first integrated circuit memory devices is provided with instruction, and refusal is provided with instruction with the mode register that the inhibit signal that receives responds on first predetermined pins.Therefore, when during the mode register setting operation, when receiving enable signal on first predetermined pins, the information that mode register is provided with instruction can be stored in first mode register.
Similarly, second integrated circuit memory devices can comprise a plurality of second instruction/address pin on the instruction/address lines that is coupled to instruction/address bus, second mode register is configured to the information of area definition second memory device operation characteristic, and second instruction decoder.The mode register that second instruction decoder can be configured to receive with the enable signal response that receives in second predetermined pins of second integrated circuit memory devices is provided with instruction, and refusal is provided with instruction with the mode register that the inhibit signal that receives in second predetermined pins responds.Therefore, during the mode register setting operation, when second predetermined pins received enable signal, the information that mode register is provided with instruction can be stored in second mode register.
Memory Controller can be coupled to instruction/address bus, wherein during the first mode register setting operation, Memory Controller is configured to by instruction/address bus, transmits the first mode register setting and instructs a plurality of first and second instruction/address pin of first and second integrated circuit memory devices.Memory Controller can be further configured to transmitting first predetermined pins of first enable signal to first integrated circuit memory devices, and during the first mode register setting operation, be configured to transmit first inhibit signal in second predetermined pins of second integrated circuit memory devices.
The additional embodiments according to the present invention provides a kind of control to comprise the method for memory module that is coupled to a plurality of storage arrangements of Memory Controller by same instruction/address bus.More particularly, during the mode register setting operation, by instruction/address bus, the register that supplies a pattern from Memory Controller to each integrated circuit memory devices is provided with instruction.During the mode register setting operation, by the signal line between the Memory Controller and first integrated circuit memory devices, therefore first provided inhibit signal in one of from the Memory Controller to the integrated circuit memory devices forbids that the mode register of first integrated circuit memory devices is provided with the execution of instruction.During the mode register setting operation, by the signal line between the Memory Controller and second integrated circuit memory devices, second in one of from the Memory Controller to the integrated circuit memory devices can provide enable signal, and the mode register that therefore enables second integrated circuit memory devices is provided with the execution of instruction.And during the mode register setting operation, inhibit signal can not be provided for second integrated circuit memory devices, and during the mode register setting operation, enable signal can not be provided for first integrated circuit memory devices.Another embodiment according to the present invention, integrated circuit memory devices can comprise memory cell array, mode register, instruction decoder, and the data input/output (i/o) buffer.Mode register can be configured to the information of area definition storage arrangement operation characteristic.The preference pattern register that instruction decoder can be configured to receive the enable signal response that receives on the predetermined pins with integrated circuit memory devices is provided with instruction.During preference pattern register setting operation, the preference pattern register that instruction decoder further is configured to refuse the inhibit signal response that receives on the predetermined pins with integrated circuit memory devices is provided with instruction.Therefore, during preference pattern register setting operation, when the scheduled pin of enable signal received, the information that the preference pattern register is provided with instruction can be stored in the mode register.Operation characteristic according to the definition of mode register canned data, during write operation, the data input/output (i/o) buffer can be configured to control data write store cell array, and during read operation, the data input/output (i/o) buffer can be configured to control from the memory cell array reading of data.
According to still another embodiment of the invention, a kind of method of operating integrated circuit memory devices can be included in during the first preference pattern register setting operation, reception is provided with instruction with the first preference pattern register of the enable signal response that has first logical value of the predetermined pins reception of integrated circuit memory devices, consequently is provided with the first preference pattern register and instructs corresponding information to be stored in the mode register.During the second preference pattern register setting operation, the inhibit signal response that has second logical value that receives with the predetermined pins of integrated circuit memory devices, the second preference pattern register is provided with instruction and can be refused, and consequently with the second preference pattern register the corresponding information of instruction is set and is not stored in the mode register.In addition, first and second logical values can be opposite logical values.According to the operation characteristic of mode register canned data definition, during write operation, but write data to the memory cell array Be Controlled of integrated circuit memory devices, with and/or during read operation, but from memory cell array reading of data Be Controlled.
The more embodiment according to the present invention provides a kind of operation to comprise the method for the memory module of a plurality of integrated circuit memory devices.A plurality of storage arrangements can be coupled to Memory Controller by same instruction/address bus, and the data input/output bus of a plurality of storage arrangement by separately can be coupled to Memory Controller respectively.More particularly, utilize the first data input/output bus be coupling between Memory Controller and first memory device, first the mode register of one of storage arrangement can be set, thereby defined the operation characteristic of first memory device.Utilization is coupling in the second data input/output bus between Memory Controller and second memory device, and second the mode register of one of storage arrangement can be set, thus the operation characteristic of definition second memory device.In addition, by the first data input/output bus, first data-signal can be written into the memory cell array of first memory device, and by the second data input/output bus, second data-signal can be written into the memory cell array of second memory device.
More again embodiment according to the present invention, integrated circuit memory devices can comprise memory cell array, a plurality of data I/O pin, and mode register.During data write operation, a plurality of data I/O pins can be configured to receive data and be written to memory cell array from Memory Controller, and during data reading operation, data I/O pin can be further configured to providing data to Memory Controller from memory cell array.Mode register can be configured to the information of area definition storage arrangement operation characteristic, and utilizes the data input/output bus to come the configuration mode register.
According to more embodiment of the present invention, a kind of method of operational store module is provided, this memory module comprises a plurality of storage arrangements that are coupled to Memory Controller by same instruction/address bus.More particularly, during the mode register setting operation,, instruction is set from the Memory Controller receiving mode register of each integrated circuit memory devices by instruction/address bus.During the mode register setting operation, by the signal line between the Memory Controller and first integrated circuit memory devices, receive inhibit signal from first the Memory Controller of one of integrated circuit memory devices, thereby forbid that the mode register of first integrated circuit memory devices is provided with the execution of instruction.During the mode register setting operation, by the signal line between the Memory Controller and second integrated circuit memory devices, receive enable signal from second of one of integrated circuit memory devices Memory Controller, thereby the mode register that enables second integrated circuit memory devices is provided with the execution of instruction.In addition, during the mode register setting operation, inhibit signal will not received by second integrated circuit memory devices, and during the mode register setting operation, enable signal will not received by first integrated circuit memory devices.
Description of drawings
Fig. 1 shows the block diagram of the conventional memory system that comprises memory module and Memory Controller;
Fig. 2 shows the block diagram of the storage arrangement of conventional memory module;
Fig. 3 A shows the synoptic diagram of the pin configuration of conventional memory device;
Fig. 3 B is the table of pin mark that has defined the conventional memory device of Fig. 3 A;
Fig. 4 shows the block diagram of conventional memory device;
Fig. 5 shows the sequential chart of the read operation of conventional memory system;
Fig. 6 shows the sequential chart of the write operation of conventional memory system;
Fig. 7 shows the block diagram according to the accumulator system that comprises memory module and Memory Controller of the embodiment of the invention;
Fig. 8 A shows the block diagram according to the storage arrangement of the embodiment of the invention;
Fig. 8 B shows the table that instruction is set according to the mode register of the embodiment of the invention;
Fig. 9 A shows the block diagram according to the internal clock signal control module of the embodiment of the invention;
Fig. 9 B shows the table that the mode register of regularly adjusting according to the internal clock signal of the embodiment of the invention is provided with instruction;
Figure 10 shows during the read operation according to the embodiment of the invention, internal clock signal sequential chart regularly;
Figure 11 shows during the write operation according to the embodiment of the invention, internal clock signal sequential chart regularly;
Figure 12 shows coupled mode register according to the embodiment of the invention block diagram that instruction and mode register are provided with the enable/disable signal is set;
The mode register that utilizes that Figure 13 shows according to the embodiment of the invention is provided with the dedicated line and the pin of enable/disable signal, the sequential chart of execution pattern register setting operation;
Figure 14 shows the sequential chart according to the data strobe of the embodiment of the invention and internal clock signal operation;
The mode register that utilizes that Figure 15 shows according to the embodiment of the invention is provided with the data mask circuit and the pin of enable/disable signal, the sequential chart of execution pattern register setting operation;
The mode register that utilizes that Figure 16 shows according to the embodiment of the invention is provided with the data strobe circuit and the pin of enable/disable signal, the sequential chart of execution pattern register setting operation;
The mode register that utilizes that Figure 17 shows according to the embodiment of the invention is provided with the data-signal circuit and the pin of enable/disable signal, the sequential chart of execution pattern register setting operation;
Figure 18 shows the block diagram according to the topology of the memory module of the embodiment of the invention;
Figure 19 shows the block diagram according to the additional topological of the memory module of the embodiment of the invention;
Figure 20 shows the block diagram according to the additional topological again of the memory module of the embodiment of the invention;
Figure 21 shows the block diagram according to the additional topological again of the memory module of the embodiment of the invention;
Figure 22 shows the block diagram according to more topologys of the memory module of the embodiment of the invention;
Figure 23 shows the block diagram according to more topologys again of the memory module of the embodiment of the invention;
Figure 24 shows the synoptic diagram according to the output driver of the embodiment of the invention;
Figure 25 is the block diagram of accumulator system 1900 in accordance with another embodiment of the present invention;
Figure 26 is accumulator system 2100 block diagrams of another embodiment according to the present invention;
Figure 27 is the block diagram of the accumulator system 2200 of another embodiment according to the present invention; With
Figure 28 is the block diagram of the accumulator system 2300 of another embodiment according to the present invention.
Embodiment
The present invention will be according to the accompanying drawing that the embodiment of the invention is shown more detailed description hereinafter.But the present invention should not regard as and was limited to the embodiment that lists here.On the contrary, these embodiment that provide so that above-mentioned comprehensively open and complete, and for a person skilled in the art, will pass on the scope of the invention comprehensively.In the accompanying drawings, for clear and thickness and zone that amplified layer.Identical Reference numeral is indicated components identical in the text.Term as used herein " and/or " comprise one or more relevant any and whole combinations of listing.
At this term of using only is that the purpose of describing special embodiment is not used for limiting the present invention.As using at this, singulative " a ", " an " and " the " also comprise plural form, unless context spells out in addition.Can further understand term " comprises " and/or " comprising ", in the time of in being used in instructions, the existence of the feature of specified, integer, step, operation, unit and/or element, thus but do not get rid of the existence of one or more other features, integer, step, operation, unit, element and/or its combination or additional.
Be understandable that when relating to the unit to be " connected " or " coupled " other unit that it can be connected directly or be coupled to other unit maybe can exist middle unit.On the contrary, the unit will be " directly connected " or to other unit, there is not middle unit in " directly coupling " when relating to.Be understandable that although first, second grade of term can be used for describing various unit at this, these unit should not be subjected to the restriction of these terms.These terms only are used for a unit and other unit are differentiated.Like this, under the situation that does not break away from the present invention's instruction, first module can be called as Unit second.
Unless otherwise defined, has same implication at these all terms of using (comprising technology and scientific terminology) as the field of the invention those of ordinary skill common sense.Further understand described term, for example usually use in the dictionary defined those, should be interpreted as having and the consistent implication of connotation in the correlation technique context, and not should in Utopian or excessively formal meaning, understanding, unless so clearly defined at this.
In the system of number storage according to an embodiment of the invention shown in Fig. 7, Memory Controller 100 may command comprise the operation of the memory module 200 of a plurality of storage arrangement 300M1-300M9.More especially, each storage arrangement 300 can be the integrated circuit dynamic random access memory means.
Utilize independently data signal bus circuit, data-signal DATA1-DATA9 can be at Memory Controller 100 and is independently transmitted between storage arrangement 300M1-300M9.During read operation, pass through independently data bus line simultaneously, data-signal DATA1-DATA9 can be read the Memory Controller 100 from storage arrangement 300M1-300M9, and during write operation, data-signal DATA1-DATA9 can be written into storage arrangement 300M1-300M9 from Memory Controller 100 simultaneously.In addition, be used for the separate lines and the separate lines that is used for data mask signal DM1-DM9 of data strobe signal DQS1-DQS9, between Memory Controller 100 and each storage arrangement 300M1-300M9, be provided.
In addition, be used for the separate lines that mode register is provided with enable/disable signal ID1-ID9, between Memory Controller 100 and each storage arrangement 300M1-300M9, be provided.For example, independent dedicated line can be provided with between the enable/disable pin at Memory Controller and at the dedicated mode register on each storage arrangement and be provided.Perhaps, at the circuit that is used for Data transmission gating signal DQS1-DQS9 during the read/write operation, during read/write operation, be used for the circuit of communicated data signal DATA1-DATA9, or during read/write operation, be used for the circuit of Data transmission shielded signal DM1-DM9, during the mode register setting operation, can being used to independently, the transfer mode register is provided with enable/disable signal ID1-ID9 in each storage arrangement 300M1-300M9.
Therefore, the propagation delay between Memory Controller 100 and each storage arrangement 300M1-300M9 is provided with enable/disable signal ID1-ID9 about equally for data-signal DATA1-DATA9, data strobe signal DQS1-DQS9, data mask signal DM1-DM9 and mode register.The configuration that has Fig. 1 of independent data bus between Memory Controller 100 and each storage arrangement 300M1-300M9 can b referred to as and provide point-to-point and be connected.
On the contrary, clock/instruction/address bus 112 control/address signal CA and clock signal of system CK that can be coupled from Memory Controller 100 to each storage arrangement 300M1-300M9.Therefore, the length of clock signal C K transmission lines is for the difference of each storage arrangement 300M1-300M9, so that the propagation delay of clock signal C K is for the difference of each storage arrangement 300M1-300M9.If along control/address/clock bus 112, storage arrangement 300M1-300M9 is evenly separated, and then clock signal C K can experience for the propagation delay each storage arrangement 300M1-300M9, that increase progressively in the memory module 200 (be also referred to as and differ or phase shift).Distribute to first memory device 300M1 propagation delay 0 arbitrarily, for example, clock signal C K propagation delay T can be created among the second memory device 300M2, propagation delay 2T can be created among the storage arrangement 300M3, propagation delay 3T can be created among the storage arrangement 300M4, propagation delay 4T can be created among the storage arrangement 300M5, propagation delay 5T can be created among the storage arrangement 300M6, propagation delay 6T can be created among the storage arrangement 300M7, propagation delay 7T can be created among the storage arrangement 300M8, and propagation delay 8T can be created among the storage arrangement 300M9.Layout with Fig. 7 of the clock signal C K that offers each storage arrangement 300M1-300M9 can be described as to have provided and leaps clock.
What the identical systems clock signal circuit of utilization by clock/instruction/address bus 112 was provided to each storage arrangement 300M1-300M9 leaps clock signal of system CK, can be synchronously the read and write data-signal DATA1-DATA9 that provides of Point-to-Point Data bus by correspondence.According to embodiments of the invention, but, each storage arrangement 300M1-300M9 can comprise the internal clock signal generator that is configured to adjust the internal clock signal timing, so that the internal clock signal of different memory device 300M1-300M9 can be roughly synchronous, is received on the different memory device even have the clock signal of system of different propagation delays.More particularly, the timing of each internal clock signal can be adjusted with respect to clock signal of system CK, and the numerical value of storing in the mode register of this clock signal of system CK response storage device is received at each storage arrangement.Therefore, the mode register of different memory device can be programmed to different value to compensate the propagation-delay differences of the clock signal of system CK that is received by the different memory device.
When the address lines by clock/instruction/address bus 112 is provided with same mode register application of instruction in all storage arrangement 300M1-300M9 the time, during preference pattern register setting operation, for example mode register is provided with enable/disable signal ID1-ID9, can be used to enable or forbidden storage apparatus 300M1-300M9 in independent one.For example, during the first preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID1 and can be applied among the storage arrangement 300M1, and the prohibited mode register is provided with enable/disable signal ID2-ID9 and can be applied among the storage arrangement 300M2-300M9.During the second preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID2 and can be applied among the storage arrangement 300M2, and the prohibited mode register is provided with enable/disable signal ID1 and ID3-ID9 can be applied among storage arrangement 300M1 and the 300M3-300M9.During the 3rd preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID3 and can be applied among the storage arrangement 300M3, and the prohibited mode register is provided with enable/disable signal ID1-ID2 and ID4-ID9 can be applied among storage arrangement 300M1-300M2 and the 300M4-300M9.During the 4th preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID4 and can be applied among the storage arrangement 300M4, and the prohibited mode register is provided with enable/disable signal ID1-ID3 and ID5-ID9 can be applied among storage arrangement 300M1-300M3 and the 300M5-300M9.During the 5th preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID5 and can be applied among the storage arrangement 300M5, and the prohibited mode register is provided with enable/disable signal ID1-ID4 and ID6-ID9 can be applied among storage arrangement 300M1-300M4 and the 300M6-300M9.During the 6th preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID6 and can be applied among the storage arrangement 300M6, and the prohibited mode register is provided with enable/disable signal ID1-ID5 and ID7-ID9 can be applied among storage arrangement 300M1-300M5 and the 300M7-300M9.During the 7th preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID7 and can be applied among the storage arrangement 300M7, and the prohibited mode register is provided with enable/disable signal ID1-ID6 and ID8-ID9 can be applied among storage arrangement 300M1-300M6 and the 300M8-300M9.During the 8th preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID8 and can be applied among the storage arrangement 300M8, and the prohibited mode register is provided with enable/disable signal ID1-ID7 and ID9 can be applied among storage arrangement 300M1-300M7 and the 300M9.During the 9th preference pattern register setting operation, the enable mode register is provided with enable/disable signal ID9 and can be applied among the storage arrangement 300M9, and the prohibited mode register is provided with enable/disable signal ID1-ID8 and can be applied among the storage arrangement 300M1-300M8.
Therefore, a series of nine preference pattern register setting operations different memory device of nine different operation modes that can be used for programming.For example, different several adjustment that are programmed with the different timing that the separately internal clock signal relevant with the clock signal of system CK that is received by separately storage arrangement is provided among the storage arrangement 300M1-300M9.Like this, the internal clock signal of different memory device can be roughly synchronous, although the propagation delay difference of the clock signal of system CK that quilt storage arrangement separately receives.Perhaps/in addition, different several being programmed among the storage arrangement 300M1-300M9 so that the different driving device output characteristics (for example driver intensity) of the data-signal DATA1-DATA9 that Memory Controller 100 reads to be provided.Again or/in addition, different several among the storage arrangement 300M1-300M9 are programmed with the difference setting that the data-signal DATA1-DATA9 that is written into the corresponding stored apparatus is provided and/or support characteristics.If a plurality of storage arrangement 300M1-300M9 are programmed the characteristic (for example same driver intensity) that provides same, during same preference pattern register setting operation, the enable mode register is provided with the enable/disable signal can be applied to above-mentioned a plurality of storage arrangement.
Shown in Fig. 8 A, can comprise internal clock signal generator 310, instruction decoder 320, data I/O (I/O) impact damper 330, memory cell array 340, address buffer 350, row decoder 360, column decoder 380 and sensor amplifier 370 with timing control unit 315 according to embodiment of the invention storage arrangement 300.As mentioned above, clock signal of system CK, command signal CMD and address signal ADD can be provided for the clock/instruction/address pin of storage arrangement 300 by the circuit of clock/instruction/address bus 112.Clock signal of system CK can offer the dedicated pin of storage arrangement 300 by the dedicated line of bus 112.Command signal CMD for example chip select (/CS) signal, row address strobe (/RAS) signal, column address strobe (/CAS) signal and writing enable (/WE) signal can offer storage arrangement 300 dedicated pin and instruction decoder 320 by the dedicated line of bus 112.Address signal ADD (comprising column address signal, row address signal and/or bank address signals) can be during read and/or write, and the address lines by bus 112 offers address buffer.But during the mode register setting operation, mode register is provided with instruction and can be provided by the address lines of bus 112.As mentioned above, the circuit of address bus 112 can be connected to a plurality of storage arrangements in the memory module.
Data bus line only is connected between Memory Controller and the storage arrangement 300.More particularly, data-signal DATA, data strobe signal DQS and data mask signal DM can offer I/O, data strobe and the data mask pin of correspondence by the circuit of data bus during reading and/or writing.For example mode register is provided with enable/disable signal ID, and during the mode register setting operation, the dedicated mode register that can be provided for storage arrangement 300 is provided with the enable/disable pin, and in read and write operating period, this dedicated pin is inoperative.Perhaps, mode register is provided with enable/disable signal ID during the mode register setting operation, can be provided for data I/O, data strobe or data mask pin one of them.
During read operation, data are read from the memory cell of the memory cell array 340 that the address signal ADD that provides by address buffer 350 is identified.More particularly, sensor amplifier 370 is read the data in the address of row decoder 360 and column decoder 380 signs, and these data are offered data I/O impact damper 330 as internal data signal iDATA.Impact damper 330 provides the data-signal DATA corresponding with internal data signal iDATA, and provides data-signal DATA synchronously with internal clock signal iCLK that internal clock generator 310 produces.
During write operation, data-signal DATA is provided for the data I/O pin of storage arrangement 300 from Memory Controller, and is synchronized with internal clock signal iCLK and is latched at data input/output (i/o) buffer 330.Data-signal DATA in the impact damper 330 is provided for memory cell array 340 as internal data signal iDATA then.By the address pin of storage arrangement 300, the address signal ADD definition that address buffer 350 receives will be written into the memory cell position of the memory cell array 340 of internal data signal iDATA.
By providing the command signal CMD corresponding, start-up mode register setting operation with the mode register setting operation.For example, chip select (/CS) signal, row address strobe (/RAS) signal, column address strobe (/CAS) signal and writing enable (/WE) signal is all by clock/instruction/address bus 112, offer instruction decoder 320 as low signal, with start-up mode register setting operation.In case start-up mode register setting operation, mode register are provided with the address lines of instruction by clock/instruction/address bus 112, are provided for address pin and address buffer 350.Because the mode register setting operation is activated, regard that by the signal that address lines receives the mode register opposite with storage address is provided with instruction as.
Offer the signal definable of address pin such as the various modes register shown in Fig. 8 B table instruction is set.Bank-address pin BA2, for example, can be used for normal mode register setting operation (logical value " 0 ") difference and preference pattern register setting operation according to an embodiment of the invention, in preference pattern register setting operation according to an embodiment of the invention, depend on that mode register is provided with the logical value of enable/disable signal ID, preference pattern register setting operation be enable or forbid.If conventional mode register setting operation selected (by providing logical value 0) at bank-address pin BA2, bank-address pin BA1 can be preserved for following use (RFU), by the logical value 0 selectable modes register that is provided on the bank-address pin BA0 (MRS) circulation is set, and (EMRS) circulation is set by the logical value 1 selectable extension function mode register that is provided on the bank-address pin BA0.In the MRS circulation, address pin A9-A12 can be preserved for following use (RFU), but address pin A8 receive delay locked loop (DLL) reset instruction, but address pin A7 acceptance test pattern (TM) instruction, address pin A4-A6 can receive the CAS instruction of hiding, and address pin A3 can receive burst (burst) type (BT) instruction and address pin A0-A3 can receive the burst-length instruction.Conventional MRS and EMRS circulation can be passed through the Memory Controller of the address lines of clock/instruction/address bus 112, are provided for a plurality of storage arrangements of memory module.In addition, a plurality of storage arrangements that are connected to clock/instruction/address bus 112 are all implemented by conventional MRS that provides by bus or EMRS instruction.
When the preference pattern register setting operation carried out according to the embodiment of the invention, same preference pattern register is provided with instruction and is provided for a plurality of storage arrangements on the address lines of clock/instruction/address bus, but mode register is provided with instruction and can implements on some storage arrangement, and does not implement other are provided with the storage arrangement of enable/disable signal ID according to the mode register that is applied to each storage arrangement on.As mentioned above, can be by logical value " 1 " be provided on bank-address pin BA2, sign is provided with instruction according to the preference pattern register of the embodiment of the invention.
Command signal CMD by associative mode register setting operation is provided (for example promising low/CS ,/RAS ,/CAS and/WE), and provide logical value " 1 " at bank-address pin BA2, can start mode register setting operation according to the embodiment of the invention.When by clock/instruction/address bus 112, when command signal and bank address signals were offered in the module all storage arrangements, all storage arrangements can receive above-mentioned instruction and address signal in the module.But each storage arrangement in the module can pass through from the different signal line of Memory Controller, and the receiving mode register is provided with enable/disable signal ID.In addition, the special pattern register of special memory device reception is provided with enable/disable signal ID and can determines whether to carry out described mode register setting operation in this device.
When the command signal CMD of associative mode register setting operation is provided for the instruction decoder 320 of storage arrangement 300, and when comprising that logical value is the address signal ADD of 1 bank address signals BA2 when being provided for address buffer 350, storage arrangement can be discerned preference pattern register setting operation according to an embodiment of the invention.Storage arrangement 300 determines whether to be provided with according to the mode register that is offered other storage arrangement in storage arrangement 300 rather than the module by selectivity the value of enable/disable signal ID, carries out described preference pattern register setting operation.ID is provided for storage arrangement 300 if the enable mode register is provided with the enable/disable signal, according to the embodiment of the invention, the mode register that receives according to the address lines by address buffer 350 is provided with instruction, carries out this preference pattern register setting operation.More especially, the partial mode register is provided with instruction and is written into mode register (for example being provided) in control module 315, to realize the operator scheme of expection.ID is provided for storage arrangement 300 if the prohibited mode register is provided with the enable/disable signal, and according to the embodiment of the invention, this preference pattern register setting operation can be left in the basket.
Clock signal of system CK can be provided as the input of the control module among Fig. 8 A, and internal clock signal can be provided as the output of iCLK control module 315, shown in Fig. 9 A.More especially, the control module 315 among Fig. 8 A can comprise a plurality of delay circuit 401a-h, and each delay circuit can comprise buffer circuits 403a-h separately.One of them output of the input of circuit 405 selectable delay circuit 401a or delay circuit 401a-h is selected in tap, with the timing of adjustment internal clock signal iCLK, and tap tap selection can be confirmed as responding the preference pattern register setting operation according to the embodiment of the invention.More especially, the mode register that the mode register MR that provides in the tap selection circuit 405 can be set to receive during preference pattern register setting operation with described storage arrangement is provided with commanded response, therefore can realize the expection timing of internal clock signal.
For example, the tap of delay circuit 401d can be selected arbitrarily and as default tap, be exported so that default timing to be provided.The tap that is different from default tap can selectedly come in advance or delayed internal clock signal with respect to default tap.Therefore, tap selects circuit 405 can select special tap, and definition is with respect to the timing of the internal clock signal iCLK of clock signal of system CK.In addition, tap selects circuit 405 can select special tap, with the preference pattern register setting operation of response according to the embodiment of the invention.Therefore, with respect to the delay of the internal clock signal iCLK of clock signal of system CK, be different, with the different propagation delay of the clock signal of system CK of compensation in the different memory device with respect to storage arrangements different in the memory module.
Therefore, can carry out preference pattern register setting operation for storage arrangement 300, to adjust timing with respect to the internal clock signal iCLK of clock signal of system CK.By providing to command signal CMD that should the mode register setting operation, and instruction is set to address buffer 350 is provided by mode register, and by providing the enable mode register enable/disable signal ID to be set, for storage arrangement 300 starts this preference pattern register setting operation to storage arrangement 300.Mode register is provided with instruction and can be identified as the preference pattern register instruction is set, for example, and by logical value " 1 " being offered the bank-address circuit BA2 of clock/instruction/address bus 112.
Have nine different 315, nine different timing command M of control module RS1-MRS9 that postpone taps can be used to define by shown in the tap tap of selecting circuit 405 to select, in Fig. 9 B.In addition, during preference pattern register setting operation,, provide four bit code to be used for defining different time-of-the-day order MRS1-MRS9 by four predetermined address lines of clock/instruction/address bus 112.For example, each delay circuit 401a-h can provide along and the adjacent memory device of clock/instruction/address bus 112 between clock signal of system CK propagation delay differences about equally in advance/delay T.With reference to figure 9A and 9B, time-of-the-day order MRS1 can pass through the tap of the output of selection delay circuit 401h, and relative delay+4T of internal clock signal iCLK is provided; Time-of-the-day order MRS2 can pass through the tap of the output of selection delay circuit 401g, and relative delay+3T of internal clock signal iCLK is provided; Time-of-the-day order MRS3 can pass through the tap of the output of selection delay circuit 401f, and relative delay+2T of internal clock signal iCLK is provided; Time-of-the-day order MRS4 can pass through the tap of the output of selection delay circuit 401e, and relative delay+1T of internal clock signal iCLK is provided; Time-of-the-day order MRS5 can pass through the tap of the output of selection delay circuit 401d, and reference or default (0 shifts to an earlier date or delay) of internal clock signal iCLK is provided; Time-of-the-day order MRS6 can pass through the tap of the output of selection delay circuit 401c, and shifting to an earlier date relatively-1T of internal clock signal iCLK is provided; Time-of-the-day order MRS7 can pass through the tap of the output of selection delay circuit 401b, and shifting to an earlier date relatively-2T of internal clock signal iCLK is provided; Time-of-the-day order MRS8 can pass through the tap of the output of selection delay circuit 401a, and shifting to an earlier date relatively-3T of internal clock signal iCLK is provided; And time-of-the-day order MRS9 can be by selecting delay circuit 401a the tap of input, provide an internal clock signal iCLK relatively in advance-4T.
Memory module 200 and Memory Controller 100 with reference to figure 7, the same memory device 300M1-300M9 can be provided on the module 200, module 200 has support each storage arrangement according to the preference pattern register setting operation of the embodiment of the invention, therefore can support the adjustment of the timing of its internal clocking.Memory Controller 100 can carry out nine preference pattern register setting operations, with the operation of the internal clock generator that defines each storage arrangement.For example, Memory Controller 100 can provide the preference pattern register that instruction is set, with the position according to each storage arrangement 300M1-300M9, and supposition is adjusted the timing of internal clock signal in the propagation delay of the clock signal of system CK of each memory means locations.Perhaps, Memory Controller 100 can provide the preference pattern register that instruction is set, to adjust internal clocking according to the measured performance of single memory device in the module 200 regularly.
According to a particular embodiment of the invention, the preference pattern register among Fig. 9 B is provided with command M RS1-MRS9 and can be applied to separately storage arrangement 300M1-300M9 selectively.In the first preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS1 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID1 can be applied to storage arrangement 300M1, and the prohibited mode register is provided with enable/disable signal ID2-ID9 and can be applied to storage arrangement 300M2-300M9.In the second preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS2 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID2 can be applied to storage arrangement 300M2, and the prohibited mode register is provided with enable/disable signal ID1 and ID3-ID9 can be applied to storage arrangement 300M1 and 300M3-300M9.In the 3rd preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS3 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID3 can be applied to storage arrangement 300M3, and the prohibited mode register is provided with enable/disable signal ID1-ID2 and ID4-ID9 can be applied to storage arrangement 300M1-300M2 and 300M4-300M9.In the 4th preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS4 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID4 can be applied to storage arrangement 300M4, and the prohibited mode register is provided with enable/disable signal ID1-ID3 and ID5-ID9 can be applied to storage arrangement 300M1-300M3 and 300M5-300M9.
In the 5th preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS5 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID5 can be applied to storage arrangement 300M5, and the prohibited mode register is provided with enable/disable signal ID1-ID4 and ID6-ID9 can be applied to storage arrangement 300M1-300M4 and 300M6-300M9.In the 6th preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS6 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID6 can be applied to storage arrangement 300M6, and the prohibited mode register is provided with enable/disable signal ID1-ID5 and ID7-ID9 can be applied to storage arrangement 300M1-300M5 and 300M7-300M9.In the 7th preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS7 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID7 can be applied to storage arrangement 300M7, and the prohibited mode register is provided with enable/disable signal ID1-ID6 and ID8-ID9 can be applied to storage arrangement 300M1-300M6 and 300M8-300M9.In the 8th preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS8 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID8 can be applied to storage arrangement 300M8, and the prohibited mode register is provided with enable/disable signal ID1-ID7 and ID9 can be applied to storage arrangement 300M1-300M7 and 300M9.In the 9th preference pattern register setting operation, along clock/instruction/address bus 112, mode register is provided with command M RS9 can be applied to all storage arrangement 300M1-300M9, the enable mode register is provided with enable/disable signal ID9 can be applied to storage arrangement 300M9, and the prohibited mode register is provided with enable/disable signal ID1-ID8 and can be applied to storage arrangement 300M1-300M8.
Sequential chart shown in Figure 10 and 11, above-mentioned preference pattern register setting operation can provide roughly synchronous internal clock signal iCLK to storage arrangement 300M1-300M9 different in the memory module shown in Figure 7 200.As shown in figure 10 during read operation, owing to different propagation delay, in the difference moment, the transmission of different storage arrangement receiving system clock signal C K in the memory module along clock/instruction/address bus 112.More especially, shown in signal CK1 and CK5, the rising edge of clock signal of system can be stored apparatus 300M1 reception before it is stored apparatus 300M5 reception, and shown in signal CK5 and CK9, the rising edge of clock signal of system can be stored apparatus 300M5 reception before it is stored apparatus 300M9 reception.Owing to utilize the timing of the internal clock signal of preference pattern register setting operation storage arrangement to be adjusted by selectivity, so internal clock signal iCLK1, iCLK5 and iCLK9 can be roughly synchronous.More especially, the clock signal C K1 that the delay of internal clock signal iCLK1 can receive with respect to first memory device 300M1 and increasing, the clock signal C K5 that the default delay of internal clock signal iCLK5 can receive with respect to the 5th storage arrangement 300M5 and being held, and the delay of the internal clock signal iCLK9 clock signal C K9 that can receive with respect to storage arrangement 300M9 and reducing.
Therefore, the internal signal iDATA that latchs each storage arrangement 300M1-300M9 can be determined with respect to roughly synchronous internal clock signal iCLK1-9 to the timing in the input/output (i/o) buffer separately.Pass through data bus separately like this, it also is roughly synchronous to the timing of Memory Controller 100 that data-signal DATA1-DATA9 is provided.Therefore, during data reading operation, data-signal DATA1-DATA9 can offer data bus separately in the roughly the same moment, thereby the data time lag can reduce.
During the write operation shown in Figure 11, owing to different propagation delays along clock/instruction/address bus 112, in difference constantly, the transmission of the different storage arrangement receiving system clock signal C K in the memory module.As mentioned above, internal clock signal iCLK1-iCLK9 is roughly synchronous.Therefore, the timing of the latch data signal DATA from the Memory Controller of each storage arrangement 300M1-300M9 to separately input/output (i/o) buffer can be determined with respect to roughly synchronous internal clock signal iCLK1-9.Data bus by separately like this, it also is roughly synchronous that the timing of 340 internal data iDATA1-iDATA9 is provided from the input/output (i/o) buffer to the memory cell array.Therefore, during data write operation, data-signal DATA1-DATA9 can be received in the roughly the same moment in the input/output (i/o) buffer separately of the storage arrangement in the module, and the data time lag can reduce like this.
In the memory module 200 that comprises a plurality of storage arrangement 300M1-300Mn, by the clock/instruction/address bus 112 that is coupled to all storage arrangement 300M1-300Mn, the register that supplies a pattern is provided with instruction.But mode register is provided with enable/disable signal ID1-IDn, can independently be provided between Memory Controller 100 and storage arrangement 300M1-300Mn separately.As mentioned above, according to embodiments of the invention, but some mode registers are provided with instruction identification selection mode register instruction are set, the enable mode register is provided with the enable/disable signal can discern the storage arrangement separately that the application choice mode register is provided with instruction, and the prohibited mode register is provided with the enable/disable signal and can discerns the storage arrangement separately that application choice mode register not is provided with instruction.Iff mode register enable/disable signal ID1 is set and enables, and mode register is provided with enable/disable signal ID2-IDn and forbids that the preference pattern register is provided with instruction and only is applied to storage arrangement 300M1.Perhaps, during preference pattern register setting operation, the enable mode register is provided with the enable/disable signal can be applied to a plurality of storage arrangements, so that preference pattern register setting operation can be applied to a plurality of storage arrangements that enable simultaneously.Preference pattern register setting operation can be applicable in the storage arrangement, module in the module all storage arrangements in a plurality of storage arrangements or the module so according to an embodiment of the invention.
As mentioned above, can think the part, the more particularly part of tap selection circuit 405 of internal clock generator 310 according to the mode register MR of the embodiment of the invention.Perhaps, can think the part of instruction decoder 320, address buffer 350, data I/O impact damper 330 and/or other parts of storage arrangement 300 according to the mode register of the embodiment of the invention.As above further described, mode register MR can store with the preference pattern register of define storage device operation characteristic (for example internal clock signal shifts to an earlier date/postpones) the corresponding information of instruction is set.In addition, a plurality of operation characteristics that can utilize single preference pattern register that instruction is set storage arrangement is set (for example internal clock signal in advance/delays, output driver intensity, the time is set in the data input and/or data are imported the retention time).Therefore, can store with the preference pattern register of a plurality of operation characteristics of define storage device according to the monotype register of the embodiment of the invention the corresponding information of instruction is set.Perhaps, utilize single preference pattern register that instruction is set, can provide different operation characteristics to be provided with to a plurality of mode registers.
The sequential chart of Figure 13 shows the preference pattern register setting operation of the storage arrangement 300M1-300Mn among Figure 12.In the example of Figure 13, mode register is provided with enable/disable signal ID1-IDn and by the dedicated mode register enable/disable circuit is set, and the dedicated mode register that offers among the storage arrangement 300M1-300Mn separately is provided with the enable/disable pin.In other words, the dedicated mode register is provided with the enable/disable circuit and pin is inoperative during the data read and/or write.
As shown in figure 13, can use first mode register by clock/instruction/address bus 112 command M RS1 is set, the enable mode register is provided with enable/disable signal ID1 (logical value 0) and can be applicable to first memory device 300M1, and during the first mode memory setting operation C1, the prohibited mode register is provided with enable/disable signal ID2-IDn (logical value 1) and can be applicable to storage arrangement 300M2-300Mn.Therefore, the first mode register setting operation C1 internal clock signal iCLK1 that can be storage arrangement 300M1 provides and postpones to adjust.
During the second mode register setting operation C2, can use second mode register by clock/instruction/address bus 112 command M RS2 is set, the enable mode register is provided with enable/disable signal ID2 (logical value 0) and can be applicable to second memory device 300M2, and the prohibited mode register is provided with enable/disable signal ID1 and ID3-IDn (logical value 1) can be applicable to storage arrangement 300M1 and 300M3-300Mn.Therefore, the second mode register setting operation C2 internal clock signal iCLK2 that can be storage arrangement 300M2 provides and postpones to adjust.
During n mode register setting operation Cn, can use the n mode register by clock/instruction/address bus 112 command M RSn is set, the enable mode register is provided with enable/disable signal IDn (logical value 0) and can be applicable to n storage arrangement 300Mn, and the prohibited mode register is provided with enable/disable signal ID1-ID (n-1) (logical value 1) and can be applicable to storage arrangement 300M1-300M (n-1).Therefore, the n mode register setting operation Cn internal clock signal iCLKn that can be storage arrangement 300Mn provides and postpones to adjust.
Independently the different memory device that can be in the memory module of mode register setting operation provides different internal clockings regularly to adjust.In addition/or, independently the mode register setting operation can be the different memory device different driver intensity is provided, for the different memory device provides different setting and/or the retention times, with and/or other characteristics that change along with the storage arrangement of the same memory module are provided.
Figure 14 shows during the write operation, comprises the sequential chart of write operation of the memory module 200 of storage arrangement 300M1-300M9.As shown in the figure, shown in signal CK1 and CK5, the transmission of first memory device 300M1 acceptable system clock signal before the 5th storage arrangement 300M5, and shown in signal CK5 and CK9, the conversion of the 5th storage arrangement 300M5 acceptable system clock signal before the 9th storage arrangement 300M9.As mentioned above, preference pattern register setting operation can provide the adjustment of internal clock signal iCLK1-iCLK9, so that internal clock signal can be roughly synchronous.
During write operation, the data strobe signal DQS of each storage arrangement can be from high impedance (Hi-Z) state exchange to logic low state, and before data-signal DATA was arranged on separately data bus, data strobe signal remained on the DQS preamble low state in period.Data strobe signal conversion subsequently can signal indication provide new data D1-D4 at each storage arrangement of separately data bus.Therefore, the time lag between the clock signal of system rising edge of conversion from the high impedance status to the low impedance state and the reception of each storage arrangement can limit the high-frequency storage operation.By internal clock signal roughly synchronous in the different memory device, data strobe signal is roughly synchronous with respect to the internal clock signal of different memory device, so that operating frequency can improve.
The sequential chart of Figure 15 shows the preference pattern register setting operation of each storage arrangement 300M1-300Mn among Figure 12.In the example of Figure 15, during preference pattern register setting operation, mode register is provided with enable/disable signal ID1-IDn by the data mask circuit, offers the data mask pin of storage arrangement 300M1-300M9 separately.During read and/or write, data mask circuit and pin are used for providing the data mask signal to separately storage arrangement.Because mode register is provided with enable/disable signal ID1-ID9 and is provided by data mask circuit and pin, therefore the mode register in Figure 15 is provided with the enable/disable signal and is marked as DM1-DMn.
As shown in figure 15, during the first preference pattern register setting operation C1, use the first preference pattern register by clock/instruction/address bus 112 command M RS1 is set, the enable mode register is provided with enable/disable signal ID1 and can be used as DM1 and be applied to first memory device 300M1, and the prohibited mode register is provided with enable/disable signal ID2-IDn and can be used as DM2-DMn and be applied to storage arrangement 300M2-300Mn.Therefore, the first mode register setting operation C1 can be internal clock signal iCLK1 among the storage arrangement 300M1 provides and postpones to adjust.
During the second preference pattern register setting operation C2, use the second preference pattern register by clock/instruction/address bus 112 command M RS2 is set, the enable mode register is provided with enable/disable signal ID2 and can be used as DM2 and be applied to second memory device 300M2, and enable/disable signal ID1 is set the prohibited mode register and ID3-IDn can be used as DM1 and DM3-DMn is applied to storage arrangement 300M1 and 300M3-300Mn.Therefore, the second preference pattern register setting operation C2 can be internal clock signal iCLK2 among the storage arrangement 300M2 provides and postpones to adjust.
During n preference pattern register setting operation Cn, use n preference pattern register by clock/instruction/address bus 112 command M RSn is set, the enable mode register is provided with enable/disable signal IDn and can be used as DMn and be applied to n storage arrangement 300Mn, and the prohibited mode register is provided with enable/disable signal ID1-ID (n-1) and can be used as DM1-DM (n-1) and be applied to storage arrangement 300M1-300M (n-1).Therefore, n preference pattern register setting operation Cn can be internal clock signal iCLKn among the storage arrangement 300Mn provides and postpones to adjust.
According to embodiment shown in Figure 15, the enable/disable circuit is set additional dedicated mode register and pin does not need, and is because ready-made data mask circuit and pin is used.Therefore preference pattern register setting operation according to the embodiment of the invention can be provided, and not need to increase the number of pins of the storage arrangement of supporting described preference pattern register setting operation.
The sequential chart of Figure 16 shows the preference pattern register setting operation of each storage arrangement 300M1-300Mn among Figure 12.In the example of Figure 16, during preference pattern register setting operation, by the data strobe circuit mode register is provided with enable/disable signal ID1-IDn and offers data strobe pin among separately the storage arrangement 300M1-300M9.During read and/or write, data strobe circuit and pin are used to provide data strobe signal to separately storage arrangement.Owing to the register that supplies a pattern by data strobe circuit and pin is provided with enable/disable signal ID1-ID9, the mode register in Figure 15 is provided with the enable/disable signal and is marked as DQS1-DQSn.
As shown in figure 16, during the first mode register setting operation C1, use first mode register by clock/instruction/address bus 112 command M RS1 is set, the enable mode register is provided with enable/disable signal ID1 and can be used as DQS1 and be applied to first memory device 300M1, and the prohibited mode register is provided with enable/disable signal ID2-IDn and can be used as DQS2-DQSn and be applied to storage arrangement 300M2-300Mn.Therefore, the first mode register setting operation C1 can be internal clock signal iCLK1 among the storage arrangement 300M1 provides and postpones to adjust.
During the second mode register setting operation C2, use second mode register by clock/instruction/address bus 112 command M RS2 is set, the enable mode register is provided with enable/disable signal ID2 and can be used as DQS2 and be applied to second memory device 300M2, and enable/disable signal ID1 is set the prohibited mode register and ID3-IDn can be used as DQS1 and DQS3-DQSn is applied to storage arrangement 300M1 and 300M3-300Mn.Therefore, the second mode register setting operation C2 can be internal clock signal iCLK2 among the storage arrangement 300M2 provides and postpones to adjust.
During n mode register setting operation Cn, use the n mode register by clock/instruction/address bus 112 command M RSn is set, the enable mode register is provided with enable/disable signal IDn and can be used as DQSn and be applied to n storage arrangement 300Mn, and the prohibited mode register is provided with enable/disable signal ID1-ID (n-1) and can be used as DQS1-DQS (n-1) and be applied to storage arrangement 300M1-300M (n-1).Therefore, n mode register setting operation Cn can be internal clock signal iCLKn among the storage arrangement 300Mn provides and postpones to adjust.
According to embodiment shown in Figure 16, the enable/disable circuit is set additional dedicated mode register and pin does not need, and is because ready-made data strobe circuit and pin is used.According to the preference pattern register setting operation of the embodiment of the invention therefore not needs increase the number of pins of the storage arrangement of supporting described preference pattern register setting operation.
The sequential chart of Figure 17 shows the preference pattern register setting operation of each the storage arrangement 300M1-300Mn among Figure 12.In the example of Figure 17, during preference pattern register setting operation, mode register is provided with enable/disable signal ID1-IDn by the data-signal circuit, offers the data signal pin among the storage arrangement 300M1-300M9 separately.During read and/or write, data-signal circuit and pin are used to transmit from storage arrangement separately reads and writes the data of storage arrangement separately.Owing to the register that supplies a pattern by data-signal circuit and pin is provided with enable/disable signal ID1-ID9, the mode register among Figure 15 is provided with the enable/disable signal and is marked as DQ1-DQn.A plurality of data signal pin are provided on each storage arrangement, but during preference pattern register setting operation, and single one is used to the receiving mode register enable/disable signal is set in the data signal pin in each storage arrangement.
As shown in figure 17, during the first mode register setting operation C1, use first mode register by clock/instruction/address bus 112 command M RS1 is set, the enable mode register is provided with enable/disable signal ID1 and can be used as DQ1 and be applied to first memory device 300M1, and the prohibited mode register is provided with enable/disable signal ID2-IDn and can be used as DQ2-DQn and be applied to storage arrangement 300M2-300Mn.Therefore, the first mode register setting operation C1 can be internal clock signal iCLK1 among the storage arrangement 300M1 provides and postpones to adjust.
During the second mode register setting operation C2, use second mode register by clock/instruction/address bus 112 command M RS2 is set, the enable mode register is provided with enable/disable signal ID2 and can be used as DQ2 and be applied to second memory device 300M2, and enable/disable signal ID1 is set the prohibited mode register and ID3-IDn can be used as DQ1 and DQ3-DQn is applied to storage arrangement 300M1 and 300M3-300Mn.Therefore, the second mode register setting operation C2 can be internal clock signal iCLK2 among the storage arrangement 300M2 provides and postpones to adjust.
During n mode register setting operation Cn, use the n mode register by clock/instruction/address bus 112 command M RSn is set, the enable mode register is provided with enable/disable signal IDn and can be used as DQn and be applied to n storage arrangement 300Mn, and the prohibited mode register is provided with enable/disable signal ID1-ID (n-1) and can be used as DQ1-DQ (n-1) and be applied to storage arrangement 300M1-300M (n-1).Therefore, n mode register setting operation Cn can be internal clock signal iCLKn among the storage arrangement 300Mn provides and postpones to adjust.
According to embodiment shown in Figure 17, the enable/disable circuit is set additional dedicated mode register and pin does not need, and is because ready-made data strobe circuit and pin is used.According to the preference pattern register setting operation of the embodiment of the invention therefore not needs increase the number of pins of the storage arrangement of supporting described preference pattern register setting operation.
As mentioned above, can be used for the timing of internal clock signal that the different memory device of same clock/instruction/address bus is shared in the selectivity adjustment according to the preference pattern register setting operation of the embodiment of the invention.In addition/or, can be used for selectivity setting, adjustment and/or change the operation characteristic of removing internal clock signal storage arrangement regularly, shared same clock/instruction/address bus according to the preference pattern register setting operation of the embodiment of the invention.
In addition, provide the layout that is different from memory module shown in Figure 7 according to the embodiment of the invention.As shown in figure 18, at first end of the row of storage arrangement 300M1-300M9, clock/instruction/address bus 112A can enter memory module 200A, and at second end of the row of storage arrangement, terminal 400A can be provided for the circuit of bus 112.More especially, terminal can comprise and is coupling in the resistance between line end and reference voltage (for example power source voltage Vcc) separately.By terminal 400A is provided, the quality of a plurality of clocks, instruction and/or the address signal that provides along clock/instruction/address bus 112 will be improved.
As shown in figure 19, between the capable memory storage of storage arrangement 300M1-300M9, clock/instruction/address bus 112B can enter memory module 200B, and bus 112 can in the opposite direction be expanded.In addition, in the capable opposite ends of storage arrangement 300M1-300M9, terminal 400B can be provided for bus 112.Utilize a pair of resistance like this, each circuit of bus 112 can be terminated, and at first end of memory device row first resistance that stops circuit is arranged, and at second end of memory device row this second right resistance that stops circuit is arranged.In this bus of row middle part supply of storage arrangement, the time lag of the clock signal of system that the different memory device in being expert at receives can reduce by roughly.In the example of Fig. 7, the 8T time period after storage arrangement 300M1 receives transmission, the transmission of storage arrangement 300M9 acceptable system clock signal.Suppose among Figure 19 that along the additional propagation delay of each storage arrangement of bus 112B be T, receive 4T time period after transmitting, the transmission of storage arrangement 300M1 acceptable system clock signal at storage arrangement 300M5.Therefore, the maximum time lag of the clock signal of system of the different memory device of module 200B reception can be roughly 2 coefficient and reduce.
As shown in figure 20, independently clock/instruction/address bus 112C and 114C be provided for the storage arrangement of memory module 200C in capable not on the same group.For example, storage arrangement 300M1-300M5 can be provided, and storage arrangement 300M6-300M9 can be provided along bus 114C along bus 112C.In addition, can provide terminal 400C at each bus 112C and 114C end.Have bus 112C and the 114C that the row middle part of the storage arrangement of terminal 400C enters though show at the capable end at storage arrangement, the memory device row opposite end of the terminal that provides at the memory device row middle part also can be provided for bus 112C and 114C.The maximum time lag of the transmission of the clock signal of system that receives of different memory device can reduce like this, as in the above with reference to as described in Figure 19.
By independently bus 112C and 114C are provided, can be storage arrangements different among the module 200C and carry out preference pattern register setting operation simultaneously according to the embodiment of the invention.If carry out independently preference pattern register setting operation for each storage arrangement 300M1-300M9, for example, five of storage arrangement 300M1-300M5 continuous mode register setting operations can with four continuous mode register setting operation executed in parallel of storage arrangement 300M6-300M9.Like this, with utilize single clock/instruction/address bus to carry out nine continuous mode register setting operations to compare, utilize two independently clock/instruction/address bus carry out the independently required time decreased of preference pattern register setting operation from nine storage arrangements.
As shown in figure 21, on bus 504A and 504B, can supply with from the clock/instruction/address bus 112D of Memory Controller independently provides the register of buffered clock/instruction/address signal 500A.Provide phaselocked loop (PLL) circuit 502 to improve the clock signal of system that receives from Memory Controller, and can provide terminal 400D at the end of bus 504A-B.By the independent bus line 504A-B that supplies with from register 500A is provided, the maximum time lag of the transmission of the clock signal of system that the different memory device receives can reduce.As shown, can provide register 500A and phase-locked loop circuit 502 simultaneously.Perhaps, register 500A can be provided and phase-locked loop circuit 502 is not provided, or phase-locked loop circuit 502 is provided and register 500A is provided.
As shown in figure 22, clock/instruction/the address signal and the data-signal of all storage arrangements among the memory module 200E, can offer register 500B from Memory Controller, and clock/instruction/address signal can and be provided on the bus 604A-B, as described above with reference to Figure 21 by independent buffer memory.In addition, pass through to the independent bus line of each storage arrangement 300M1-300M9, register 500B can provide independently data-signal DATA, independently data mask signal DM and data strobe signal DQS independently.In addition, terminal 400E can be provided for each bus 604A-B.Though Figure 22 is not shown, phaselocked loop (PLL) circuit can be provided for clock signal of system, as described above with reference to Figure 21.
As shown in figure 23, with entering memory module 2000F between the clock/storage arrangement of instruction/address bus 112 in storage arrangement 300M1-300M9 is capable, provide the topology that leaps of clock/instruction/address bus 112.Such topology can be the coupled memory controller favourable layout is provided.
As mentioned above, can be used for selecting to adjust internal clock signal timing in the different memory device of sharing same clock/instruction/address bus according to the preference pattern register setting operation of the embodiment of the invention.In addition/or, can be used for optionally being provided with, adjusting and/or change operation characteristic according to the preference pattern register setting operation of the embodiment of the invention except that internal clock signal storage arrangement regularly, shared same clock/instruction/address bus.For example, can be used for being provided with the different driving device intensity of the different memory device of sharing same clock/instruction/address bus according to the preference pattern register setting operation of the embodiment of the invention.
For example, each the storage arrangement 300M1-300M9 in the memory module 200 can comprise data I/O impact damper 330 separately, as top with reference to as described in Fig. 7 and 8.In addition, the data-signal DATA of each storage arrangement 300 can comprise a plurality of data bit DQ, and the internal data signal iDATA of each storage arrangement 300 can comprise a plurality of internal datas position iDQ separately.Therefore, data I/O impact damper 330 can comprise a plurality of output drivers 150, and this driver 150 is provided to change each internal data position iDQ into provide on the pin of I/O separately 152 on the storage arrangement the DQ of data bit separately, for example, and as shown in figure 24.
More especially, output driver 150 can have the basic drive circuit that comprises transistor 130 and 140, and the auxiliary actuator circuit that comprises transistor 132,134,142 and 144.During read operation, have logical value " 1 " but internal data position iDQ turn-on transistor 140 and "off" transistor 130 so that I/O pin 152 is coupled to ground voltage VSS by transistor 140, and data bit DQ has logical value " 0 ".During read operation, have the internal data position iDQ "off" transistor 140 and the turn-on transistor 130 of logical value " 0 ", so that I/O pin 152 is coupled to supply voltage VDD by transistor 130, and data bit DQ has logical value " 1 ".The basic drive circuit comprises transistor 130 and 140, can carry out the logic function of output driver 150 like this.The auxiliary actuator circuit comprises transistor 132,134,142 and 144, signal CON that can be by logical value " 0 " is provided and be under an embargo by inverse signal/CON that logical value " 1 " is provided, so that transistor 132 and 142 is cut off.
The intensity of output driver 150 can be by logical value " 1 " be provided signal CON and provide the inverse signal/CON of logical value " 0 " to increase so that transistor 132 and 142 is switched on and the auxiliary actuator circuit is enabled.Along with the auxiliary actuator circuit is enabled during read operation, have logical value " 1 " but internal data position iDQ turn-on transistor 140 and 144, and "off" transistor 130 and 134, so that I/O pin 152 is coupled to ground voltage VSS by transistor 140 and 144, and data bit DQ has logical value " 0 ".Along with the auxiliary actuator circuit is enabled during read operation, have logical value " 0 " but internal data position iDQ "off" transistor 140 and 144, and turn-on transistor 130 and 134, so that I/O pin 152 is coupled to supply voltage VDD by transistor 130 and 134, and data bit DQ has logical value " 1 ".Along with the auxiliary actuator circuit is enabled, fundamental sum auxiliary actuator circuit parallel is carried out the logic function of output driver 150, has therefore increased the driver intensity of output driver 150.
Can carry out preference pattern register setting operation for each storage arrangement 300M1-300M9 like this, so that the different output driver characteristics of the different memory storages of sharing same clock/instruction/address bus 112 to be set.As mentioned above, during the mode register setting operation, can pass through the address lines of clock/instruction/address bus 112, provide the preference pattern register that instruction is set, the enable mode register is provided with the enable/disable signal and can offers and be employed the storage arrangement that mode register is provided with instruction.In addition, whether mode register all output drivers that the logical value definable storage arrangement of the single position in the instruction is set should provide driver intensity increase or that reduce.Perhaps, the first preference pattern register is provided with instruction manipulation can carry out more than first storage arrangement that is used for the needs first output driver intensity, and the second preference pattern register is provided with instruction manipulation and can carries out more than second storage arrangement that is used for the needs second output driver intensity.
Again or, the preference pattern register manipulation can be supplied with the different driving device intensity of the output driver in the same storage arrangement.For example, the data-signal DATA of storage arrangement can comprise eight data bit DQ, and each storage arrangement can comprise eight output drivers separately.Therefore, the preference pattern register of storage arrangement eight of eight definables driver intensity of output driver separately that instruction is set.
Though the present invention is illustrated especially and has been described with reference to its exemplary embodiments, one of ordinary skill in the art will appreciate that under the situation of the spirit and scope that do not break away from claim definition of the present invention, can carry out the multiple variation on form and the content.
Figure 25 is the block diagram of accumulator system 1900 in accordance with another embodiment of the present invention.With reference to Figure 25, accumulator system 1900 comprises Memory Controller 1910 and comprises the memory module 1920 of a plurality of storage arrangement 1930M1 to 1930M9.Memory Controller 1910 utilizes clock signal C K and instruction address signal CA control store apparatus 1930M1 to 1930M9, and generation selects control store apparatus 1930M1 enable/disable signal ID1 to be set to ID9 to the mode register of 1930M9.
In first pattern, storage arrangement 1930M1 is set to different operator schemes respectively to 1930M9, enable/disable signal ID1 is set to ID9 and instruction address signal CA with the response modes register.In second pattern, storage arrangement 1930M1 operates in the setting operation pattern to 1930M9, with response predetermined instruction address signal CA.
At this, before the 1930M9 normal running, first pattern is that the pattern of storage arrangement 1930M1 to 1930M9 to the respective operations pattern is set, and second pattern is the pattern of normal running storage arrangement 1930M1 to 1930M9 at storage arrangement 1930M1.
That is to say that in first pattern, storage arrangement 1930M1 is set to corresponding operator scheme respectively to 1930M9, with response instruction address signal CA.At that time, whether the operator scheme of each storage arrangement should be set up, and depended on that the associative mode register is provided with the activation of enable/disable signal ID1 to ID9.
In other words, ID1 is activated to ID9 if the associative mode register is provided with the enable/disable signal, and each storage arrangement 1930M1 is set to the respective operations pattern to 1930M9, with response instruction address signal CA.If the associative mode register is provided with enable/disable signal ID1 and stops using to ID9, storage arrangement 1930M1 is to 1930M9 response instruction address signal CA not.Therefore, utilize mode register enable/disable signal ID1 to be set to ID9, mutually storage arrangement 1930M1 is set is possible to the operator scheme of 1930M9 in difference.
For example, when application instruction address signal CA, if to the corresponding mode register of 1930M5 enable/disable signal ID1 being set with storage arrangement 1930M1 is activated to ID5, and to the corresponding mode register of 1930M9 enable/disable signal ID6 is set with storage arrangement 1930M6 and stops using to ID9, then only there is storage arrangement 1930M1 to be set to operator scheme to 1930M5, with response instruction address signal CA, and storage arrangement 1930M6 is to 1930M9 response instruction address signal CA not.
After this, if mode register is provided with enable/disable signal ID1 and stops using to ID5, mode register is provided with enable/disable signal ID6 and is activated to ID9, and the instruction address signal CA that is used to be provided with different operation modes, storage arrangement 1930M6 can be set to be different from the operator scheme of storage arrangement 1930M1 to 1930M5 to the operator scheme of 1930M9.
In first pattern, after storage arrangement 1930M1 is set to different operator schemes to 1930M9, in second pattern, use predetermined instruction address signal CA, operation store apparatus 1930M1 is to 1930M9 in different operation modes.
According to the embodiment of the invention, be activated to ID5 if to the corresponding mode register of 1930M5 enable/disable signal ID1 is set with storage arrangement 1930M1, response instruction address signal CA, storage arrangement 1930M1 is set to refresh mode to 1930M5.If to the corresponding mode register of 1930M9 enable/disable signal ID6 being set with storage arrangement 1930M6 is activated to ID9, response instruction address signal CA, storage arrangement 1930M6 is set to degree of depth power-down mode (deeppower down mode) to 1930M9.
In degree of depth power-down mode, the builtin voltage power supply of storage arrangement is closed, and the external voltage power supply of storage arrangement is held open.Therefore, in the storage arrangement under degree of depth power-down mode, do not carry out refresh operation.That is to say, when application is used to the instruction address signal CA of refresh mode is set, to the corresponding mode register of 1930M5 enable/disable signal ID1 is set with storage arrangement 1930M1 and is activated, and to the corresponding mode register of 1930M9 enable/disable signal ID6 is set with storage arrangement 1930M6 and stops using to ID9 to ID5.
Therefore, the instruction address signal CA of response application in storage arrangement 1930M1 to 1930M5, storage arrangement 1930M1 is set to refresh mode to 1930M5, and remaining storage arrangement 1930M6 is not set to refresh mode to 1930M9.After this, if mode register is provided with enable/disable signal ID1 and stops using to ID5, mode register is provided with enable/disable signal ID6 and is activated to ID9, and the instruction address signal CA that is used to be provided with degree of depth power-down mode, storage arrangement 1930M6 can be set to degree of depth power-down mode to 1930M9.
The response modes register is provided with enable/disable signal ID1 to ID9 and instruction address signal CA, be set to the internal configurations of each storage arrangement of refresh mode or degree of depth power-down mode, be that those of ordinary skills know, therefore, omitted its detailed description.Second pattern in memory module 1920 normal runnings, if be used for the instruction address signal CA of order refresh operation, storage arrangement 1930M1 carries out refresh operation to 1930M5, and storage arrangement 1930M6 operates in degree of depth power-down mode to 1930M9.
Here, may use the instruction address signal CA that is used for order degree of depth power operation, rather than be used for the instruction address signal CA of order refresh operation.That is to say that in second pattern, the instruction address signal CA that is used to operate in the storage arrangement of different operation modes can be set arbitrarily.Therefore, be set to refresh mode and will store the memory of data device that can be wiped free of and be set to degree of depth power-down mode by storing the memory of data device that should be saved, it is possible reducing the loss of power.
Technological concept of the present invention is not subjected to memory module shown in Figure 25 1920 restrictions, and according to embodiments of the invention, technological concept of the present invention can be applied to the various memory module structures shown in Figure 18 to 23.The instruction address signal CA that produces from storage control 1910 can be MRS (mode register setting) instruction.This will describe in detail hereinafter with reference to figure 8B.
Usually, the MRS instruction comprises address code part (A0 is to A12) and two bank-address parts (BA0 and BA1).A0 is to A12 and BA0 and BA1 presentation address code and bank-address respectively, but but A0 to A12 and BA0 and BA1 presentation address pin.According to the logical value of address code decision address code, for example burst-length and CAS stand-by period.
Whether the MRS circulation is the logical value decision of current circulation according to bank-address.Address code and bank-address are called as " MRS key (key) address code " together.The MRS instruction that present embodiment uses further comprises the 3rd bank-address BA2.
Whether this enable mode register is provided with enable/disable signal ID according to the 3rd bank-address BA2 decision Memory Controller 1910 of the MRS key address code of MRS instruction.If the 3rd bank-address BA2 is low, Memory Controller 1910 shutdown mode registers are provided with enable/disable signal ID.This with in the conventional MRS of the 3rd bank-address BA2 that does not have MRS key address code instruction, be identical.
On the contrary, if the 3rd bank-address BA2 of MRS key address code is high, Memory Controller 1910 activates and the output mode register is provided with enable/disable signal ID.In the present embodiment, if the 3rd bank-address BA2 of instruction address signal CA (MRS instruction just) is high, to A12, storage arrangement 1930M1 can be set to refresh mode or degree of depth power-down mode to 1930M9 according to address code A0.MRS instruction definable multiple modes of operation is shown in Fig. 8 B.For example, if the 3rd bank-address BA2 is low, the second bank-address BA1 is saved, so that it can be used (RFU) afterwards.If the first bank-address BA0 is low, choose mode register setting (MRS) circulation.
If the first bank-address BA0 is high, choose extended mode register setting (EMRS) circulation.In MRS circulation, address code A9 is saved to A12, so that it can be used (RFU) afterwards, and address code A8 control lag locking ring (DLL) reset instruction.Address code A7 can control test instruction TM, and address code A4 can control the CAS stand-by period to A6 and instruct, and address code A3 can control demblee form BT instruction, and address code A0 can control the burst-length instruction to A3.
As mentioned above, the storage arrangement 1930M1 of accumulator system 1900 shown in Figure 25 can carry out refresh operation and degree of depth power operation respectively to 1930M9 response predetermined instruction address signal CA.That is to say that respond same instruction address signal CA, storage arrangement 1930M1 can carry out different operating to 1930M9.Each mode register is provided with enable/disable signal ID1 can be imported into storage arrangement 1930M1 one of them in corresponding one data pin, data mask pin and the data strobe pin in the 1930M9 to ID9, shown in embodiment among Fig. 8 A.
Figure 26 is accumulator system 2100 block diagrams of another embodiment according to the present invention.With reference to Figure 26, accumulator system 2100 comprises first memory device M1 and second memory device M2.Response instruction address signal CA, first memory device M1 and second memory device M2 can carry out different operating.In more detail, in first pattern, response chip select signal CS1 or CS2 and predetermined instruction address signal CA, first memory device M1 can be set to be different from the operator scheme of second memory device M2.
Accumulator system 2100 further comprises Memory Controller 2110, is used to utilize clock signal C K and instruction address signal CA, controls the operation of the first and second storage arrangement M1 and M2, and produces chip select signal CS1 and CS2.The storage arrangement 1930M1 of similar memory module 1920 as shown in figure 25 is to 1930M9, and in accumulator system shown in Figure 26 2100, according to instruction address signal CA, the first and second storage arrangement M1 are set to different operator schemes respectively with M2.
Usually, mobile device comprises storage chip rather than memory module.Accumulator system 2100 shown in Figure 26 is examples that the technology of the present invention notion are applied to mobile device.Here, chip select signal CS1 and CS2 are used, rather than mode register as shown in figure 25 is provided with enable/disable signal ID.In first pattern, if chip select signal CS1 and CS2 are activated, response instruction address signal CA, the first and second storage arrangement M1 and M2 are set to the respective operations pattern.If chip select signal CS1 and CS2 stop using, the first and second storage arrangement M1 and M2 be response instruction address signal CA not.
More detailed description, in first pattern, if chip select signal CS1 is activated, response instruction address signal CA, first memory device M1 is set to refresh mode.At this moment, if chip select signal CS2 keeps stopping using.And in instruction address signal CA, as mentioned above, the 3rd bank-address BA2 is high, and address code A0 stores the information of the refresh operation that is used to control first memory device M1 to A12.
If chip select signal CS1 stops using, and the chip select signal CS2 that is applied to second memory device M2 is activated, response instruction address signal CA, and second memory device M2 is set to degree of depth power-down mode.Like this, since in first pattern, the operator scheme of first memory device M1 and second memory device M2 is set to different pattern mutually, in normal manipulation mode, respond same instruction address signal CA, the first and second storage arrangement M1 can carry out different operations with M2.
Therefore, be saved the memory of data device and be set to refresh mode by storing, and will store and can be wiped free of the memory of data device and be set to degree of depth power-down mode, it is possible reducing power supply power consumption.First memory device M1 and second memory device M2 are directly from Memory Controller 2110 receive clock signal CK and instruction address signal CA.But, response instruction address signal CA, memory device operation is bright right at the memory system architecture of different operator schemes for those of ordinary skills, is not subjected to the restriction of accumulator system shown in Figure 26 2100.
Figure 27 is the block diagram of the accumulator system 2200 of another embodiment according to the present invention.In accumulator system 2200, first memory device M1 is directly from Memory Controller 2210 receive clock signal CK and instruction address signal CA, and second memory device M2 is by first memory device M1 receive clock signal CK and instruction address signal CA.Therefore accumulator system 2200, omits its detailed description to operate with the identical mode of accumulator system 2100 shown in Figure 26.
Figure 28 is the block diagram of the accumulator system of another embodiment according to the present invention.Accumulator system is the situation that the technology of the present invention notion that reference Figure 19 to 22 describes is applied to a plurality of memory modules.Accumulator system comprises first memory module MM11 and MM12, and second memory module MM21 and MM22, and wherein each memory module comprises a plurality of storage arrangements.
At normal manipulation mode, response instruction address signal CA, the first and second memory module MM11, MM12, MM21 and MM22 can carry out different operations.Respond the activation of the first chip select signal CS1, first memory module MM11 and MM12 are set to refresh mode according to instruction address signal CA.At this moment, the second chip select signal CS2 keeps stopping using.
And in instruction address signal CA, as mentioned above, the 3rd bank-address BA2 is high, and address code A0 stores the information of the refresh operation that is used to control first memory module MM11 and MM12 to A12.Afterwards, if the first chip select signal CS1 stops using, and the second chip select signal CS2 that is applied to second memory module MM21 and MM22 activates, response instruction address signal CA then, and second memory module MM21 and MM22 are set to degree of depth power-down mode.
Like this, if the operator scheme of first memory module MM11 and MM12 is set to be different from the operator scheme of second memory module MM21 and MM22 in first pattern, in normal manipulation mode, respond identical instruction address signal CA, first memory module MM11 and MM12 carry out the operation that is different from second memory module MM21 and MM22.
Therefore, be set to refresh mode by storing the memory of data module that be saved, and will store the memory of data module that can be wiped free of and be set to degree of depth power-down mode, it is possible reducing power supply power consumption.
Accumulator system shown in Figure 28 with the accumulator system 1900,2100 shown in Figure 25 to 27, the mode identical with 2200 operated, and therefore, omits its detailed description.

Claims (50)

1, a kind of accumulator system comprises:
Instruction/address bus with a plurality of instruction/address lines;
First integrated circuit memory devices, it comprises the instruction/address pin of more than first on the instruction/address lines that is coupled to instruction/address bus, first mode register is configured to the information of the operation characteristic of area definition first memory device, and first the instruction decoder mode register that is configured to receive the enable signal response that first predetermined pins with first integrated circuit memory devices receives instruction is set, and the mode register of the inhibit signal response of refusal and the reception of first predetermined pins is provided with instruction, so that when first predetermined pins during the mode register setting operation received enable signal, the information that mode register is provided with instruction was stored in first mode register;
Second integrated circuit memory devices, it comprises the instruction/address pin of more than second on the instruction/address lines that is coupled to instruction/address bus, second mode register is configured to the information of the operation characteristic of area definition second memory device, and second the instruction decoder mode register that is configured to receive the enable signal response that second predetermined pins with second integrated circuit memory devices receives instruction is set, and the mode register of the inhibit signal response of refusal and the reception of second predetermined pins is provided with instruction, so that when second predetermined pins during the mode register setting operation received enable signal, the information that mode register is provided with instruction can be stored in second mode register; And
Be coupled to the Memory Controller of instruction/address bus, wherein during the first mode register setting operation, described Memory Controller is configured to by instruction/address bus, transmit the first mode register setting and instruct more than first and second instruction/address pin of first and second integrated circuit memory devices, described Memory Controller is further configured to during the first mode register setting operation, transmit first predetermined pins of first enable signal, and transmit second predetermined pins of first inhibit signal to second integrated circuit memory devices to first integrated circuit memory devices;
Wherein during the second mode register setting operation, described Memory Controller further is configured to by instruction/address bus, transmitting the second mode register setting instructs on more than first and second instruction/address pin of first and second integrated circuit memory devices, during the second mode register setting operation, described Memory Controller further is configured to transmit first predetermined pins of second inhibit signal to first integrated circuit memory devices, and transmit second predetermined pins of second enable signal to second integrated circuit memory devices, wherein during the second mode register setting operation, the information that second mode register is provided with instruction is written into second mode register, rather than during the second mode register setting operation, the information that second mode register is provided with instruction is written to the operation of first mode register.
2, accumulator system according to claim 1, wherein during the first mode register setting operation, the information that first mode register is provided with instruction is written in first mode register, rather than during the first mode register setting operation, the information that first mode register is provided with instruction is written in second mode register.
3, accumulator system according to claim 1 further comprises:
The first data input/output bus, it comprises more than first the data I/O circuit that is coupling between described Memory Controller and described first integrated circuit memory devices, wherein during write operation, described Memory Controller is configured to provide first data-signal of the first memory cell array that is written to described first integrated circuit memory devices by the first data input/output bus; And
The second data input/output bus, it comprises more than second the data I/O circuit that is coupling between described Memory Controller and described second integrated circuit memory devices, wherein during write operation, described Memory Controller is configured to provide second data-signal of the second memory cell array that is written to described second integrated circuit memory devices by the second data input/output bus.
4, accumulator system according to claim 3, wherein said first integrated circuit memory devices comprises more than first the data I/O pin that is coupled to more than first data I/O circuit, wherein said second integrated circuit memory devices comprises more than second the data I/O pin that is coupled to more than second data I/O circuit, wherein said first predetermined pins comprises in more than first the data I/O pin, and wherein said second predetermined pins comprises one in more than second the data I/O pin.
5, accumulator system according to claim 1, wherein in read and write operating period, described first and second predetermined pins are inoperative.
6, accumulator system according to claim 1, wherein said first integrated circuit memory devices comprises the first data strobe pin, the first data input/output (i/o) buffer, and first memory cell array, second integrated circuit memory devices comprises the second data strobe pin, the second data input/output (i/o) buffer, and second memory cell array, wherein during write operation, respond the data strobe signal that the described first and second data strobe pins separately receive, the first data input/output (i/o) buffer is configured to data are write in the first memory cell array, and the second data input/output (i/o) buffer is configured to data are write in its second memory cell array, wherein first predetermined pins comprises the first data strobe pin, and second predetermined pins comprises the second data strobe pin.
7, accumulator system according to claim 1, wherein said first integrated circuit memory devices comprises the first data mask pin, the first data input/output (i/o) buffer, and first memory cell array, described second integrated circuit memory devices comprises the second data mask pin, the second data input/output (i/o) buffer, and second memory cell array, wherein the first data input/output (i/o) buffer is configured to during write operation the non-activation shielded signal that the response first data mask pin receives data is write in the first memory cell array, and the activation shielded signal that the response first data mask pin receives during write operation is forbidden writing data in the first memory cell array, wherein the second data input/output (i/o) buffer is configured to during write operation the non-activation shielded signal that the response second data mask pin receives data is write in the second memory cell array, and the activation shielded signal that the response second data mask pin receives during write operation is forbidden writing data in the second memory cell array, wherein first predetermined pins comprises the first data mask pin, and second predetermined pins comprises the second data mask pin.
8, accumulator system according to claim 1, wherein said first integrated circuit memory devices comprises the first data input/output (i/o) buffer, the first memory cell array, and first internal clock signal generator, described second integrated circuit memory devices comprises the second data input/output (i/o) buffer, the second memory cell array, and second internal clock signal generator, the clock signal of system that first internal clock signal generator is configured to the generation of response storage controller produces first internal clock signal, the clock signal of system that second internal clock signal generator is configured to the generation of response storage controller produces second internal clock signal
Wherein respond first internal clock signal, described first data input/output (i/o) buffer control read and write, respond second internal clock signal, described second data input/output (i/o) buffer control read and write, first internal clock signal generator is further configured to responding the information of first mode register, adjust the timing of first internal clock signal relevant with system clock, and second internal clock signal generator be further configured to responding the information of second mode register, adjust the timing of second internal clock signal relevant with system clock.
9, accumulator system according to claim 1, wherein said first integrated circuit (IC) apparatus comprises more than first data I/O pin, the first memory cell array, and be coupling in the first data input/output (i/o) buffer between more than first data I/O pin and first memory cell array, described second integrated circuit (IC) apparatus comprises more than second data I/O pin, the second memory cell array, and be coupling in the second data input/output (i/o) buffer between more than second data I/O pin and second memory cell array, wherein first input/output (i/o) buffer is configured to during read operation, data are read more than first data I/O pin from the first memory cell array, wherein second input/output (i/o) buffer is configured to during read operation, data are read more than second data I/O pin from the second memory cell array, wherein first input/output (i/o) buffer comprises more than first output driver that is coupled to one of more than first correspondence in the data I/O pin, and wherein more than first output driver information of being configured to respond first mode register is adjusted its intensity, and wherein second input/output (i/o) buffer comprises more than second output driver that is coupled to one of more than second correspondence in the data I/O pin, and wherein more than second output driver information of being configured to respond second mode register is adjusted its intensity.
10, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices are coupled in proper order along instruction/address bus.
11, accumulator system according to claim 11, wherein said instruction/address bus is from intersecting.
12, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices are coupling between Memory Controller and the terminating circuit in proper order along instruction/address bus.
13, accumulator system according to claim 1, wherein said first and second integrated circuit memory devices are along the parallel coupling of instruction/address bus, and this instruction/address bus has a supply that is arranged between first and second integrated circuit memory devices.
14, accumulator system according to claim 1, wherein said first integrated circuit memory devices is along instruction/address bus, be coupling between the Memory Controller and first terminating circuit, and wherein said second integrated circuit memory devices is coupling between the Memory Controller and second terminating circuit along instruction/address bus.
15, accumulator system according to claim 1 further comprises:
Register, it is configured to receive instruction from Memory Controller/address bus and supplies with, and this register comprises the impact damper of the instruction/address lines that is configured to drive described instruction/address bus.
16, accumulator system according to claim 16, wherein said register further is configured to receive data-signal from the Memory Controller of first and second integrated circuit (IC) apparatus, and register comprises the data buffer of the data-signal that is configured to drive first and second integrated circuit (IC) apparatus.
17, accumulator system according to claim 1 further comprises:
Be coupled to the system clock circuit of first and second integrated circuit (IC) apparatus; And
Be coupling in the phase-locked loop circuit between the clock signal of system output of system clock circuit and Memory Controller.
18, a kind of method of control store module, this memory module comprise a plurality of storage arrangements that are coupled to Memory Controller by identical instruction/address bus, and this method comprises:
During the first mode register setting operation,, to each integrated circuit memory devices, provide first mode register that instruction is set from Memory Controller by instruction/address bus;
By at Memory Controller and comprise signal line between first integrated circuit memory devices of first mode register, provide first inhibit signal from Memory Controller to first integrated circuit memory devices of a plurality of integrated circuit memory devices, during the first mode register setting operation, forbid that first mode register of first integrated circuit memory devices is provided with the execution of instruction thus;
By at Memory Controller and comprise signal line between second integrated circuit memory devices of second mode register, provide first enable signal from Memory Controller to second integrated circuit memory devices of a plurality of integrated circuit memory devices, therefore during the first mode register setting operation, first mode register that enables second integrated circuit memory devices is provided with the execution of instruction, wherein said first inhibit signal is during the first mode register setting operation, do not offer second integrated circuit memory devices, and wherein said first enable signal does not offer first integrated circuit memory devices during the first mode register setting operation;
During the second mode register setting operation,, to each integrated circuit memory devices, provide second mode register that instruction is set from Memory Controller by instruction/address bus;
Between the Memory Controller and first integrated circuit memory devices, pass through signal line, from Memory Controller to first integrated circuit memory devices, second enable signal is provided, therefore during the second mode register setting operation, second mode register that enables first integrated circuit memory devices is provided with the execution of instruction; And
Between the Memory Controller and second integrated circuit memory devices, pass through signal line, from Memory Controller to second integrated circuit memory devices, second inhibit signal is provided, therefore during the second mode register setting operation, forbid that second mode register of second integrated circuit memory devices is provided with the execution of instruction, wherein said second enable signal is during the second mode register setting operation, do not offer second integrated circuit memory devices, and wherein said second inhibit signal does not offer first integrated circuit memory devices during the second mode register setting operation.
19, method according to claim 18, this method further comprises:
During the first mode register setting operation, to the corresponding information of instruction be set with first mode register writes in second mode register of second integrated circuit memory devices, rather than during the first mode register setting operation, will the corresponding information of instruction be set with first mode register and write in first mode register.
20, method according to claim 18 further comprises:
During write operation,, first data-signal that write is offered the first memory cell array of first integrated circuit memory devices by the first data input/output bus; And
During write operation,, second data-signal that write is offered the second memory cell array of second integrated circuit memory devices by the second data input/output bus.
21, method according to claim 20, wherein said first data-signal is provided for more than first data I/O pin of first integrated circuit memory devices, wherein said second data-signal is provided for more than second data I/O pin of second integrated circuit memory devices, wherein said first inhibit signal is provided in more than first the data I/O pin, and wherein said enable signal is provided for one in more than second the data I/O pin.
22, method according to claim 18, wherein said first inhibit signal is provided for first predetermined pins of first integrated circuit memory devices, wherein said enable signal is provided for second predetermined pins of second integrated circuit memory devices, and wherein in read and write operating period, first and second predetermined pins are inoperative.
23, method according to claim 18, wherein said first integrated circuit memory devices comprises the first data strobe pin and first memory cell array, described second integrated circuit memory devices comprises the second data strobe pin and second memory cell array, and this method further comprises:
When writing data into the first memory cell array, during write operation, provide data strobe signal to the first data strobe pin, when writing data into the second memory cell array, during write operation, provide data strobe signal to the second data strobe pin, wherein said forbidding is provided for the first and second data strobe pins with enable signal.
24, method according to claim 18, wherein said first integrated circuit memory devices comprises first data mask pin and the memory cell array, described second integrated circuit memory devices comprises second data mask pin and the memory cell array, and this method further comprises:
During first write operation, non-activation shielded signal is offered the first data mask pin, during first write operation, to enable to write data in the first memory cell array;
During second write operation, the shielded signal that activates is offered the first data mask pin, during second write operation, to forbid writing data in the first memory cell array;
During first write operation, the shielded signal that activates is offered the second data mask pin, during first write operation, to forbid writing data to the second memory cell array; And
During second write operation, non-activation shielded signal is offered the second data mask pin, during second write operation, to enable to write data to the second memory cell array;
Wherein will forbid offering the first and second data mask pins with enable signal.
25, method according to claim 18 further comprises:
Provide clock signal of system to first and second integrated circuit (IC) apparatus, responding system clock signal wherein, first integrated circuit memory devices produces first internal clock signal, responding system clock signal wherein, second integrated circuit memory devices produces second internal clock signal, and wherein the response modes register is provided with instruction, with respect to clock signal of system, adjusts the timing of second internal clock signal.
26, method according to claim 18 further comprises:
During read operation, by more than first output driver and more than first data I/O pin, from the first memory cell array reception data of first integrated circuit memory devices; And
During read operation, by more than second output driver and more than second data I/O pin, from the second memory cell array reception data of second integrated circuit memory devices; And
Wherein the response modes register is provided with instruction, adjusts the intensity of more than second output driver.
27, a kind of integrated circuit memory devices comprises:
Memory cell array;
Mode register is configured to store the operation characteristic information of define storage device of being used for;
Instruction decoder, be configured to during preference pattern register setting operation, the enable signal that receives on the predetermined pins of response integrated circuit memory devices, receive the preference pattern register instruction is set, and the inhibit signal that receives on the predetermined pins of response integrated circuit memory devices, refusal preference pattern register is provided with instruction, so that during preference pattern register setting operation, when the scheduled pin of enable signal received, the information that the preference pattern register is provided with instruction was stored in mode register; And
The data input/output (i/o) buffer is configured to according to the defined operation characteristic of the information of mode register stored, and during write operation, control writes data to memory cell array, and during read operation, sense data from memory cell array.
28, integrated circuit memory devices according to claim 27, wherein during the mode register setting operation, when the scheduled pin of inhibit signal received, the information that described preference pattern register is provided with instruction was not stored in the mode register.
29, integrated circuit memory devices according to claim 27 further comprises:
The data mask pin, wherein said data input/output (i/o) buffer is configured to during write operation, the non-activation shielded signal that response data shielding pin receives, write data in the memory cell array, and during the write operation, the shielded signal of the activation that response data shielding pin receives is forbidden writing data in the memory cell array, and wherein said predetermined pins comprises the data mask pin.
30, integrated circuit memory devices according to claim 27 further comprises:
A plurality of data I/O pins, wherein said data input/output (i/o) buffer is configured to during write operation, write data to memory cell array from data I/O pin, and during read operation, to data I/O pin, wherein said predetermined pins comprises in the data I/O pin from the memory cell array read data.
31, integrated circuit memory devices according to claim 27, wherein predetermined pins is inoperative in read and write operating period.
32, integrated circuit memory devices according to claim 27 further comprises:
The data strobe pin, wherein said data input/output (i/o) buffer is configured to during write operation, and the data strobe signal that the response data strobe pin receives write data in the memory cell array, and wherein said predetermined pins comprises the data strobe pin.
33, integrated circuit memory devices according to claim 27 further comprises:
Internal clock signal generator, the clock signal of system that its clock input that is configured to respond integrated circuit memory devices receives, produce internal clock signal, wherein said data input/output (i/o) buffer response internal clock signal, control writes and reads, this internal clock generator is further configured the information that instruction is set for the preference pattern register of response modes register-stored, with respect to clock signal of system, adjusts the timing of internal clock signal.
34, integrated circuit memory devices according to claim 27 further comprises:
A plurality of data I/O pins, wherein said data input/output (i/o) buffer is configured to during read operation, from the memory cell array reading of data to data I/O pin, wherein said data input/output (i/o) buffer comprises a plurality of output drivers, and each described output driver is coupled to one in the data I/O pin respectively, and the information that the wherein said output driver preference pattern register that is configured to the response modes register-stored is provided with instruction is adjusted its intensity.
35, a kind of method of operating integrated circuit memory devices, this method comprises:
During the first preference pattern register setting operation, the predetermined pins of response integrated circuit memory devices enable signal that receive, that have first logical value, receive the first preference pattern register instruction is set, consequently the corresponding information of instruction is set and is stored in the mode register with the first preference pattern register;
During the second preference pattern register setting operation, inhibit signal that receive, that have second logical value on the predetermined pins of response integrated circuit memory devices, refuse the second preference pattern register instruction is set, so that with the second preference pattern register the corresponding information of instruction is set and is not stored in the mode register, wherein first and second logical values are opposite logical values; And
According to the defined operation characteristic of mode register canned data, during write operation, control write data in the memory cell array of integrated circuit memory devices, with and/or during read operation, from the memory cell array sense data.
36, method according to claim 35, wherein said predetermined pins comprises the data mask pin, this method further comprises:
During first write operation, the shielded signal of the activation that response data shielding pin receives is forbidden writing in the memory cell array; And
During second write operation, the non-activation shielded signal that response data shielding pin receives enables to write in the memory cell array.
37, method according to claim 35, wherein said predetermined pins comprise data I/O pin, and this method further comprises:
During write operation, write data to the memory cell array from data I/O pin; And
During read operation, from the memory cell array read data to data I/O pin.
38, method according to claim 35, wherein said predetermined pins is inoperative in read and write operating period.
39, method according to claim 35, wherein said predetermined pins comprises the data strobe pin, this method further comprises:
During write operation, the data strobe signal that the response data strobe pin receives writes data in the memory cell array.
40, method according to claim 35 further comprises:
The clock signal of system that the clock input of response integrated circuit memory devices is received produces internal clock signal, and wherein the data control that writes and/or read comprises the response internal clock signal, writes and/or sense data; And
The information of response modes register-stored with respect to clock signal of system, is adjusted the timing of internal clock signal.
41, method according to claim 35 further comprises:
During read operation, pass through output driver, the output pin of data separately from the memory cell array reading of data to integrated circuit memory devices, wherein the output driver preference pattern register that is configured to the response modes register-stored information that instruction is set is adjusted its intensity.
42, a kind of method of operational store module, this memory module comprise a plurality of storage arrangements that are coupled to Memory Controller by identical instruction/address bus, and this method comprises:
During the first mode register setting operation,, receive first mode register from Memory Controller instruction is set at each integrated circuit memory devices by instruction/address bus;
By the signal line between the Memory Controller and first integrated circuit memory devices, receive inhibit signal from first the Memory Controller of one of integrated circuit memory devices, during the first mode register setting operation, forbid that first mode register of first integrated circuit memory devices is provided with the execution of instruction thus;
By the signal line between the Memory Controller and second integrated circuit memory devices, receive enable signal from second the Memory Controller of one of integrated circuit memory devices, thus during the first mode register setting operation, first mode register that enables second integrated circuit memory devices is provided with the execution of instruction, wherein during the first mode register setting operation, second integrated circuit memory devices does not receive inhibit signal, and wherein during the first mode register setting operation, first integrated circuit memory devices does not receive enable signal;
During the second mode register setting operation,, receive second mode register from the Memory Controller of each integrated circuit memory devices instruction is set by instruction/address bus;
By the signal line between the Memory Controller and first integrated circuit memory devices, receive second enable signal from the Memory Controller of first integrated circuit memory devices, during the second mode register setting operation, second mode register that enables first integrated circuit memory devices is provided with the execution of instruction thus; And
By the signal line between the Memory Controller and second integrated circuit memory devices, receive inhibit signal from the storage control of second integrated circuit memory devices, thus during the second mode register setting operation, forbid that second mode register of second integrated circuit memory devices is provided with the execution of instruction, wherein during the second mode register setting operation, second integrated circuit memory devices does not receive second enable signal, and wherein during the second mode register setting operation, first integrated circuit memory devices does not receive second inhibit signal.
43, according to the described method of claim 42, wherein said first integrated circuit memory devices comprises first mode register, and described second integrated circuit memory devices comprises second mode register, and this method further comprises:
During the first mode register setting operation, to the corresponding information of instruction be set with first mode register is written in second mode register of second integrated circuit memory devices, rather than during the first mode register setting operation, will the corresponding information of instruction be set with first mode register and be written in first mode register.
44, according to the described method of claim 42, further comprise:
During write operation, by the first data input/output bus, reception will be written to first data-signal of the first memory cell array of first integrated circuit memory devices; And
During write operation, by the second data input/output bus, reception will be written to second data-signal in the second memory cell array of second integrated circuit memory devices.
45, according to the described method of claim 44, wherein said first data-signal is received by more than first data I/O pin of first integrated circuit memory devices, wherein said second data-signal is received by more than second data I/O pin of second integrated circuit memory devices, wherein said inhibit signal is by a reception in more than first the data I/O pin, and wherein said enable signal is by a reception in more than second the data I/O pin.
46, according to the described method of claim 42, wherein said inhibit signal is received by first predetermined pins of first integrated circuit memory devices, wherein said enable signal is received by second predetermined pins of second integrated circuit memory devices, and wherein first and second predetermined pins are inoperative in read and write operating period.
47, according to the described method of claim 46, wherein said first integrated circuit memory devices comprises the first data strobe pin and first memory cell array, described second integrated circuit memory devices comprises the second data strobe pin and second memory cell array, and this method further comprises:
During write operation, the data strobe signal that the response first and second data strobe pins separately receive writes data in first and second memory cell arrays separately, and wherein said forbidding received by the first and second data strobe pins with enable signal.
48, according to the described method of claim 42, wherein said first integrated circuit memory devices comprises the first data mask pin and first memory cell array, described second integrated circuit memory devices comprises the second data mask pin and second memory cell array, and this method further comprises:
During first write operation, respond the non-activation shielded signal that the first data mask pin receives, enable to write data in the first memory cell array;
During second write operation, respond the shielded signal of the activation of first data mask pin reception, forbid writing data in the first memory cell array;
During first write operation, respond the activation shielded signal that the second data mask pin receives, forbid writing data in the second memory cell array; And
During second write operation, respond the nonactivated shielded signal that the second data mask pin receives, enable to write data in the second memory cell array;
Wherein forbid being received by the first and second data mask pins with enable signal.
49, according to the described method of claim 42, further comprise:
Provide clock signal of system to first and second integrated circuit (IC) apparatus;
Respond described clock signal of system, produce first internal clock signal at the first integrated circuit memory devices place;
Respond described clock signal of system, produce second internal clock signal at the second integrated circuit memory devices place;
Respond described mode register instruction is set,, adjust the timing of second internal clock signal with respect to clock signal of system.
50, according to the described method of claim 42, further comprise:
During read operation,, provide data to more than first data I/O pin from the first memory cell array of first integrated circuit memory devices by more than first output driver;
During read operation,, provide data to more than second data I/O pin from the second memory cell array of second integrated circuit memory devices by more than second output driver; And
Respond described mode register instruction is set, adjust the intensity of more than second output driver.
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