CN100543877C

CN100543877C - The sensing apparatus of charge-trapping nonvolatile storage medium and method

Info

Publication number: CN100543877C
Application number: CNB2005100511826A
Authority: CN
Inventors: 叶致锴
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2004-09-09
Filing date: 2005-03-02
Publication date: 2009-09-23
Anticipated expiration: 2025-03-02
Also published as: CN1747069A

Abstract

The invention relates to a kind of sensing apparatus and method of charge-trapping nonvolatile storage medium.A kind of storage unit, this storage unit has charge trapping structure, and utilize to measure the electric current between one of them of the source electrode of the substrate of storage unit and storage unit and drain electrode, and storage unit is read.When other parts of charge trapping structure store the data that need not be selected, then read operation can reduce coupling between other parts of charge trapping structure.Therefore, above-mentioned read operation can improve the sensing window of storage unit.

Description

The sensing apparatus of charge-trapping nonvolatile storage medium and method

Technical field

The present invention relates to a kind of electronic type programmable non-volatile storage medium of can erasing, particularly relate to a kind of sensing apparatus and method of charge-trapping nonvolatile storage medium.

The invention relates to and particularly be absorbed in storage medium that it is to having high sensitive in the diverse location in the charge trapping structure of reading cells a kind of relevant for a kind of electric charge with bias arrangement.

Background technology

The application's scope is advocated the interim case sequence number of U.S. Patent application of filing an application on September 9th, 1 60/608, No. 455.The application's scope is also advocated the interim sequence number of U.S. patent application case of filing an application on September 9th, 1 60/608, No. 528.

The technology of electronic type programmable and erasable non-volatile memory medium is as the basis with charge trapping structure, electrically erasable programmable ROM (Electrically Erasable ProgrammableRead Only Memory for example, EEPROM) can apply to different modernizations with flash memory (flash memory) and use, and be to utilize some memory cell structures on electrically erasable programmable ROM and the flash memory.Therefore, when the size of integrated circuit during, then can cause very big interest, because the simplification of its processing procedure and tolerance are higher to the memory cell structure that is absorbed in dielectric layer based on electric charge towards downsizing.Wherein, the memory cell structure that is absorbed in dielectric layer based on electric charge comprises the structure of PHINES.For instance, these memory cell structures are to utilize electric charge to be trapped in electric charge to be absorbed in the dielectric layer with storage data, and wherein charge immersing layer for example is a silicon nitride layer.In addition, when negative charge is in the state of being absorbed in, then the start voltage of storage unit can increase, and the start voltage of storage unit can be by from charge immersing layer negative charge being removed and being reduced.

Existing conventional memory cells structure is to rely on the content of reverse read operation with decision storage medium structure.Yet the reverse read technology is actually the multiple charge immersal structure is coupled in together, in addition have only the Partial charge immersal structure to contain the important data that are selected also must be like this.The operation of above-mentioned dependence reverse read has limited with the method for the content of decision storage medium structure and has utilized charge trapping structure with the difficulty as non-volatile memory medium, measure the sensing window (sensing window) of the electric current of reverse read technology and it is owing to narrowed, and storable data also can be than lacking that other modes are come in charge trapping structure.

Therefore,, need to make to couple between the multiple charge immersal structure and can read for charge trapping memory cells, even also can be like this when having only the Partial charge immersal structure to contain important data that are selected.

This shows that the method for sensing of above-mentioned existing charge trapping nonvolatile storage medium obviously still has inconvenience and defective, and demands urgently further being improved in the use.The problem that exists for the method for sensing that solves the charge-trapping nonvolatile storage medium, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, and this obviously is the problem that the anxious desire of relevant dealer solves.

Because the defective that the method for sensing of above-mentioned existing charge trapping nonvolatile storage medium exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, sensing apparatus and method in the hope of the charge-trapping nonvolatile storage medium of founding a kind of new structure, can improve the method for sensing of general existing charge trapping nonvolatile storage medium, make it have more practicality.Through constantly research, design, and after studying sample and improvement repeatedly, create the present invention who has practical value finally.

Summary of the invention

The objective of the invention is to, overcome the defective that the method for sensing of existing charge trapping nonvolatile storage medium exists, and a kind of method of operating of new storage unit is provided, thereby be suitable for practicality more, and have the value on the industry.

Another object of the present invention is to, a kind of structure of integrated circuit of new structure is provided, thereby be suitable for practicality more.

A further object of the present invention is, a kind of manufacture method of new storage medium is provided, thereby is suitable for practicality more.

The object of the invention to solve the technical problems realizes by the following technical solutions.The method of operating of a kind of storage unit that proposes according to the present invention, be applicable to that this storage unit contains a gate and the one source pole and the drain electrode that are arranged in a substrate, and this storage unit comprises a upper dielectric layer, have part to should source electrode and one of this drain electrode charge trapping structure and time dielectric layer one of between this gate and this substrate, this method may further comprise the steps: select to should source area or this charge trapping structure of part of this drain region, to determine one of selected this charge trapping structure of part charge storage state; Use one first bias arrangement, determining this charge storage state of selected this charge trapping structure of part, wherein said first bias arrangement maybe applies one first voltage difference between one of them of this drain electrode in this substrate and this source electrode; And measure maybe this drain electrode electric current one of between one of them of this substrate and this source electrode of flowing through, to determine this charge storage state of selected this charge trapping structure of part.

The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.

The method of operating of aforesaid storage unit, wherein this source electrode maybe wherein another of this drain electrode be to float.

The method of operating of aforesaid storage unit, wherein said first bias arrangement is maybe to produce one second voltage difference between wherein another of this drain electrode in this gate and this source electrode, wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

The method of operating of aforesaid storage unit, wherein said first bias arrangement in this gate and this source electrode maybe should drain electrode wherein another between produce one second voltage difference of 5V, and this first voltage difference is less than 5V.

The method of operating of aforesaid storage unit, wherein said first bias arrangement make electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least.

The method of operating of aforesaid storage unit, this electric current of wherein said measurement maybe one of them of this drain electrode of this substrate and this source electrode of flowing through.

The method of operating of aforesaid storage unit, wherein said substrate are to be arranged in one of semiconductor substrate well region.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, by utilizing the F-N tunnelling in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, by utilizing the channel hot electron injection current in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge by utilizing passage to open beginning second electron injection current, to adjust this charge storage state.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this substrate, to adjust this charge storage state.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this gate, to adjust this charge storage state.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state, wherein this electric current by the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement is 100nA, and is 1nA by this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement.

The method of operating of aforesaid storage unit, it more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state, be greater than by 10 times in this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement wherein by this electric current of the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement.

The method of operating of aforesaid storage unit, this charge storage state of wherein said each this charge trapping structure partly are to store a bit.

The method of operating of aforesaid storage unit, this charge storage state of wherein said each this charge trapping structure partly are to store multiple bit.

The method of operating of aforesaid storage unit, wherein the hot hole that produces during described first bias arrangement is not enough to disturb this charge storage state.

The object of the invention to solve the technical problems also adopts following technical scheme to realize.According to a kind of non-volatile memory medium that the present invention proposes, it comprises: a substrate, contain an one source pole and a drain electrode; Once dielectric layer is couple to this substrate; One charge trapping structure is couple to and has part to should source electrode and this time dielectric layer of this drain electrode, and each part has a charge storage state; One upper dielectric layer is couple to this charge trapping structure; One gate is couple to this upper dielectric layer; And one logic use one first bias arrangement to determine this charge storage state, and measure flow through this substrate and this source electrode maybe this drain electrode electric current is determining this charge storage state of selected this charge trapping structure of part one of between one of them, wherein said first bias arrangement maybe applies a voltage difference between one of them of this drain electrode in this substrate and this source electrode.

Aforesaid non-volatile memory medium, wherein this source electrode maybe wherein another of this drain electrode be to float.

Aforesaid non-volatile memory medium, wherein said first bias arrangement in this gate and this source electrode maybe produce between wherein another of this drain electrode one second voltage difference wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

Aforesaid non-volatile memory medium, wherein said first bias arrangement in this gate and this source electrode maybe should drain electrode wherein another between produce one second voltage difference of 5V, and this first voltage difference is less than 5V.

Aforesaid non-volatile memory medium, wherein said first bias arrangement make electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least.

Flow through one of them of this substrate and this source electrode and this drain electrode of aforesaid non-volatile memory medium, this electric current of wherein said measurement.

Aforesaid non-volatile memory medium, wherein said substrate are to be arranged in one of semiconductor substrate well region.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement,

By utilizing the F-N tunnelling in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, by utilizing the channel hot electron injection current in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge by utilizing passage to open beginning second electron injection current, to adjust this charge storage state.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this substrate, to adjust this charge storage state.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this gate, to adjust this charge storage state.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, by increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, by in this charge trapping structure, increasing by a net negative charge, to adjust this charge storage state, wherein this electric current by the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement is 100nA, and is 1nA by this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement.

Aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, one of increase clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, one of in this charge trapping structure, increase net negative charge, to adjust this charge storage state, be greater than by 10 times in this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement wherein by this electric current of the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement.

Aforesaid non-volatile memory medium, this charge storage state of wherein said each this charge trapping structure partly are to store a bit.

Aforesaid non-volatile memory medium, this charge storage state of wherein said each this charge trapping structure partly are to store multiple bit.

Aforesaid non-volatile memory medium, wherein the hot hole that produces during described first bias arrangement is not enough to disturb this charge storage state.

The object of the invention to solve the technical problems also adopts following technical scheme to realize.The manufacture method of a kind of non-volatile memory medium that proposes according to the present invention, it may further comprise the steps: provide a substrate, and this substrate contains an one source pole and a drain electrode; Providing, dielectric layer is couple to this substrate; Provide a charge trapping structure to be couple to have part to should source electrode and this time dielectric layer of this drain electrode, and each part have a charge storage state; Provide a upper dielectric layer to be couple to this charge trapping structure; Provide a gate to be couple to this upper dielectric layer; And provide a logic to use one first bias arrangement to determine this charge storage state, and measure flow through this substrate and this source electrode maybe this drain electrode electric current is determining this charge storage state of selected this charge trapping structure of part one of between one of them, wherein said first bias arrangement maybe applies one first voltage difference between one of them of this drain electrode in this substrate and this source electrode.

The manufacture method of aforesaid non-volatile memory medium, wherein this source electrode maybe wherein another of this drain electrode be to float.

The manufacture method of aforesaid non-volatile memory medium, wherein said first bias arrangement in this gate and this source electrode maybe produce between wherein another of this drain electrode one second voltage difference wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

The manufacture method of aforesaid non-volatile memory medium, wherein said first bias arrangement in this gate and this source electrode maybe should drain electrode wherein another between produce one second voltage difference of 5V, and this first voltage difference is less than 5V.

The manufacture method of aforesaid non-volatile memory medium, wherein said first bias arrangement make electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least.

The manufacture method of aforesaid non-volatile memory medium, this electric current of wherein said measurement maybe one of them of this drain electrode of this substrate and this source electrode of flowing through.

The manufacture method of aforesaid non-volatile memory medium, wherein said substrate are to be arranged in one of semiconductor substrate well region.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, by utilizing the F-N tunnelling in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, by utilizing the channel hot electron injection current in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge by utilizing passage to open beginning second electron injection current, to adjust this charge storage state.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this substrate, to adjust this charge storage state.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this gate, to adjust this charge storage state.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state, wherein this electric current by the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement is 100nA, and is 1nA by this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement.

The manufacture method of aforesaid non-volatile memory medium, wherein said logic more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state, be greater than by 10 times in this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement wherein by this electric current of the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement.

The manufacture method of aforesaid non-volatile memory medium, this charge storage state of wherein said each this charge trapping structure partly are to store a bit.

The manufacture method of aforesaid non-volatile memory medium, this charge storage state of wherein said each this charge trapping structure partly are to store multiple bit.

The manufacture method of aforesaid non-volatile memory medium, wherein the hot hole that produces during this charge storage state of described decision is not enough to disturb this charge storage state.

The object of the invention to solve the technical problems also adopts following technical scheme to realize., a kind of non-volatile memory medium integrated circuit that propose according to the present invention, it comprises: a storage medium array comprises most row, each those row comprises most storage unit and is a series connection configuration, and have one first end and one second end, wherein each those storage unit comprises: a substrate, contain an one source pole and a drain electrode; Once dielectric layer is couple to this substrate; One charge trapping structure is couple to and has part to should source electrode and this time dielectric layer of this drain electrode, and each part has a charge storage state; One upper dielectric layer is couple to this charge trapping structure; One first transmission transistor is couple to this first end of this arranged in series; One second transmission transistor is couple to this second end of this arranged in series; One first bit line is couple to this first transmission transistor; One second bit line is couple to this second transmission transistor; Most character lines are couple to this upper dielectric layer of each those storage unit, and each those character line as a gate so that those storage unit are couple to each those character line; And one logic be couple to those storage unit, and this logic open this first transmission transistor and this second transmission transistor one of them so that electronics couples a sensing amplifier one of them maybe this drain electrode of this source electrode to those storage unit, select corresponding this source electrode of this charge storage state of part maybe should drain, and this logic uses one first bias arrangement to determine this charge storage state, and electric current is determining this charge storage state of selected this charge trapping structure of part one of between one of them to measure flow through this basal area and this source area or this drain region, and wherein said first bias arrangement maybe applies a voltage difference between one of them of this drain electrode in this substrate and this source area.

Aforesaid non-volatile memory medium integrated circuit, wherein this source electrode maybe wherein another of this drain electrode be to float.

Aforesaid non-volatile memory medium integrated circuit, wherein said first bias arrangement be in this gate and this source electrode maybe produce between wherein another of this drain electrode one second voltage difference wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

Aforesaid non-volatile memory medium integrated circuit, wherein said first bias arrangement in this gate and this source electrode maybe should drain electrode wherein another between produce one second voltage difference of 5V, and this first voltage difference is less than 5V.

Aforesaid non-volatile memory medium integrated circuit, wherein said first bias arrangement make electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least.

Aforesaid non-volatile memory medium integrated circuit, this electric current of wherein said measurement maybe one of them of this drain electrode of this substrate and this source electrode of flowing through.

Aforesaid non-volatile memory medium integrated circuit, wherein said substrate are to be arranged in one of semiconductor substrate well region.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, by utilizing the F-N tunnelling in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, by utilizing the channel hot electron injection current in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge by utilizing passage to open beginning second electron injection current, to adjust this charge storage state.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this substrate, to adjust this charge storage state.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this gate, to adjust this charge storage state.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state, wherein this electric current by the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement is 100nA, and is 1nA by this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement.

Aforesaid non-volatile memory medium integrated circuit, wherein said logic more comprises: use one second bias arrangement, increase by a clean positive charge in this charge trapping structure, to adjust this charge storage state; And use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state, be greater than by 10 times in this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement wherein by this electric current of the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement.

Aforesaid non-volatile memory medium integrated circuit, this charge storage state of wherein said each this charge trapping structure partly are to store a bit.

Aforesaid non-volatile memory medium integrated circuit, this charge storage state of wherein said each this charge trapping structure partly are to store multiple bit.

Aforesaid non-volatile memory medium integrated circuit, wherein the hot hole that produces during this charge storage state of described decision is not enough to disturb this charge storage state.

The present invention proposes a kind of non-volatile memory medium, and this non-volatile memory medium comprises substrate, following dielectric layer, charge trapping structure, upper dielectric layer, gate and logic.Wherein, substrate contains an one source pole and a drain electrode, and following dielectric layer is couple to substrate, and charge trapping structure is couple to down dielectric layer, and upper dielectric layer is couple to charge trapping structure, and gate is couple to upper dielectric layer.In addition, above-mentioned charge trapping structure has a part of corresponding source electrode, and another partly corresponding drain electrode.And each charge trapping structure partly has a charge storage state, its can according to the design of storage unit with use to store a bit or multiple bit.Above-mentioned logic uses a bias arrangement with the decision charge storage state, and measures flow through substrate and source electrode or the electric current between one of them of draining with the decision charge storage state, and above-mentioned electric current also comprises tunnelling current between valence band-conduction band.

Can produce an electric field at gate and source electrode or one of them the voltage difference of draining, and this electric field can cause source electrode or the band curvature on one of them of draining.The degree of band curvature is influenced by corresponding source electrode or one of them the charge storage state of this charge trapping structure of part of draining, and cause tunnelling current between source electrode or the valence band-conduction band on one of them of draining, and tunnelling current can change with charge storage state is different between above-mentioned valence band-conduction band.In certain embodiments, bias arrangement is to apply a voltage difference between one of them of substrate and source electrode or drain electrode, and wherein another of source electrode or drain electrode is to float.The vacancy that couples between the Partial charge immersal structure that above-mentioned bias arrangement can cause corresponding source electrode basically and the Partial charge immersal structure of corresponding drain electrode.Determine that the measurement electric current of charge storage state of the charge trapping structure of corresponding source electrode is independent with the charge storage state of the charge trapping structure of corresponding drain electrode in fact, and vice versa.

In certain embodiments, above-mentioned bias arrangement is in gate and source electrode or generation one first voltage difference between one of them that drains, and between wherein another of substrate and source electrode or drain electrode, produce one second voltage difference, wherein first voltage difference and second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and first voltage difference and second voltage difference can not change charge storage state, and any hot hole that produces during bias arrangement is not enough to disturb charge storage state.Therefore, read operation does not have help to storing the data in the charge trapping structure.In certain embodiments, first voltage difference that produces between one of them of gate and source electrode or drain electrode is 5V, and second voltage difference that produces between wherein another of substrate and source electrode or drain electrode is less than 5V.

In certain embodiments, above-mentioned substrate is the well region that is arranged in the semiconductor-based end.In further embodiments, above-mentioned substrate is the semiconductor-based end.

In certain embodiments, above-mentioned logic is that utilization one second bias arrangement is to increase by a clean positive charge in charge trapping structure, adjusting charge storage state, and use one the 3rd bias arrangement one of in charge trapping structure, to increase net negative charge, to adjust charge storage state.Wherein, above-mentioned clean positive charge is to increase by electric current mechanism in charge trapping structure, and electric current mechanism is for example utilized hot hole tunnelling between valence band-conduction band.Above-mentioned net negative charge is to increase by electric current mechanism in charge trapping structure, and electric current mechanism for example electron tunneling, F-N tunnelling, channel hot electron injection current and passage opens beginning second electron injection current.In certain embodiments, the electric current of the measurement of above-mentioned one of them charge storage state of adjusting by second bias arrangement and the 3rd bias arrangement is greater than by 10 times in the electric current of the measurement of another charge storage state of adjusting wherein of second bias arrangement and the 3rd bias arrangement.For example, the electric current of one of them is 100nA, and another electric current wherein is 1nA.

In another embodiment of the present invention, comprise the method for measuring flow through substrate and source electrode or the electric current between one of them that drains, and the manufacture method of non-volatile memory medium.

In another embodiment of the present invention, comprise an integrated circuit, this integrated circuit contains a memory cell array, and memory cell array comprises that a multiple bit line and a transmission transistor are couple to each bit line.

In sum, the sensing apparatus and the method for the charge-trapping nonvolatile storage medium of special construction of the present invention, the method for operating of the storage unit that it is new, the structure of the integrated circuit of new structure, and the manufacture method of new storage medium.Have above-mentioned many advantages and practical value, and in like product and manufacture method, do not see have similar structural design and method to publish or use and really genus innovation, no matter it all has bigger improvement on product structure, manufacture method or function, have large improvement technically, and produced handy and practical effect, and the method for sensing of more existing storage medium has the multinomial effect of enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.

Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of instructions, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by going out a plurality of preferred embodiments, and conjunction with figs., be described in detail as follows.

Description of drawings

Figure 1A is a kind of schematic diagram of carrying out the charge trapping memory cells of read operation on the Partial charge immersal structure of corresponding source side.

Figure 1B is a kind of schematic diagram of carrying out the charge trapping memory cells of read operation on the Partial charge immersal structure of corresponding drain side.

Fig. 2 A is the schematic diagram at a kind of charge trapping memory cells of the enterprising line program operation of Partial charge immersal structure of corresponding drain side.

Fig. 2 B is that a kind of electronics that utilizes moves to carry out the schematic diagram of the charge trapping memory cells of erase operation for use in charge trapping structure from gate to substrate.

Fig. 2 C is that a kind of electronics that utilizes moves to carry out the schematic diagram of the charge trapping memory cells of erase operation for use in charge trapping structure from substrate to gate.

Fig. 3 A is a kind of graph of a relation of sensing window of desirable storage unit.

Fig. 3 B is a kind of graph of a relation of sensing window of typical memory cell.

Fig. 4 A is a kind of graph of a relation that carries out erase operation for use on storage unit.

Fig. 4 B is a kind of graph of a relation of a part of enterprising line program operation in the charge storing unit immersal structure.

Fig. 4 C is the graph of a relation of the enterprising line program operation of a kind of another part in the charge storing unit immersal structure.

Fig. 5 A is a kind of schematic diagram of charge trapping memory cells of serial connection of a part of enterprising line program operation in selected storage unit.

Fig. 5 B is a kind of another schematic diagram of the charge trapping memory cells of the serial connection of enterprising line program operation partly in selected storage unit.

Fig. 6 A is a kind of schematic diagram of charge trapping memory cells of serial connection of carrying out read operation on the some of selected storage unit.

Fig. 6 B is the schematic diagram of the charge trapping memory cells of a kind of in selected storage unit another serial connection of carrying out read operation on partly.

Fig. 7 A is a kind of schematic diagram of charge trapping memory cells of serial connection of carrying out erase operation for use on storage unit.

Fig. 7 B is the schematic diagram of the charge trapping memory cells of another kind of serial connection of carrying out erase operation for use on storage unit.

Fig. 8 is a kind of schematic diagram of charge trapping memory cells of the serial connection at the common bit line of storage unit two ends electric property coupling.

Fig. 9 is a kind of schematic diagram of charge trapping memory cells of the array that carries out erase operation for use on storage unit.

Figure 10 is the schematic diagram of the charge trapping memory cells of the another kind of array that carries out erase operation for use on storage unit.

Figure 11 is a kind of schematic diagram of the charge trapping memory cells of the array of the selected enterprising line program operation of storage unit in some.

Figure 12 is a kind of in another schematic diagram of the charge trapping memory cells of the array of the selected enterprising line program operation of storage unit partly.

Figure 13 is a kind of schematic diagram of charge trapping memory cells of the array that carries out read operation on the selected storage unit of some.

Figure 14 is a kind of schematic diagram of charge trapping memory cells of the array that carries out read operation on another selected storage unit partly.

Figure 15 is a kind of schematic diagram of integrated circuit of the charge trapping structure with control circuit and array.

110,210: gate 120,220: go up dielectric structure

130,230: charge trapping structure 140,240: following dielectric structure

150,250: source electrode 160,260: drain electrode

170,270,502,602,702,902,1002,1102,1202,1302,1402: substrate

233: drain side 234: hole

310,320,410,420: curve 330,340: the time interval

350: sensing window 360,362,364,366: the position is accurate

505,605: the first bit lines

510,590,610,690,710,790,810,890,910,990,1010,1090: transmission transistor

520,530,540,550,560,570,580,620,630,640,650,660,670,680,720,730,740,750,760,770,780,820,830,840,850,860,870,880: storage unit

542,544,642,644: charge trapping structure

595,695: the second bit lines

705,795,804,903,904,905,906,907,1003,1004,1005,1006,1007,1203,1204,1205,1206,1207,1303,1304,1305,1306,1307,1403,1404,1405,1406,1407: the bit line

920,930,940,950,960,970,980,1020,1030,1040,1050,1060,1070,1080,1120,1130,1140,1150,1160,1170,1180,1220,1230,1240,1250,1260,1270,1280,1320,1330,1340,1350,1360,1370,1380,1420,1430,1440,1450,1460,1470,1480: the character line

1110,1190,1210,1290,1310,1390,1410,1490: transmission transistor character line

1143,1144,1145,1146,1147,1243,1244,1245,1246,1247,1343,1344,1345,1346,1347,1443,1444,1445,1446,1447: the charge trapping structure part

1500: memory array 1501: column decoder

1502: the character line 1503 of row configuration: row decoder

1504: the character line 1505 of row configuration: bus

1506: square 1507: data bus

1508: supply voltage 1509: bias arrangement status mechanism

1511: Data In-Line 1515: DOL Data Output Line

1550: integrated circuit

Embodiment

Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, sensing apparatus and its embodiment of method, structure, manufacture method, step, feature and the effect thereof of the charge-trapping nonvolatile storage medium that foundation the present invention is proposed, describe in detail as after.

Seeing also shown in Figure 1A, is a kind of schematic diagram of charge trapping memory cells, and it is presented at the state that carries out read operation on the source side of charge trapping structure.Please refer to Figure 1A, the substrate 170 that the p type mixes comprises n ⁺Type impure source 150 and n ⁺The drain electrode 160 that type mixes.In addition, other parts of storage unit also comprise the following dielectric structure (following oxide layer) 140 that is positioned in the substrate 170, be positioned at charge trapping structure 130 on the dielectric structure (following oxide layer) 140 down, be positioned at the last dielectric structure (going up oxide layer) 120 on the charge trapping structure 130, and are positioned at the gate 110 on the dielectric structure (last oxide layer) 120.Wherein, typically going up dielectric structure (going up oxide layer) 120 for example is silicon dioxide and the silicon oxynitride with thickness 5～10nm, or other suitable high dielectric constant materials, and it for example is aluminium oxide (Al ₂O ₃).Typical dielectric structure (following oxide layer) 140 down for example is silicon dioxide and the silicon oxynitride with thickness 3～10nm, or other suitable high dielectric constant materials.Typical charge trapping structure 130 for example is the silicon nitride with thickness 3～9nm, or other suitable high dielectric constant materials, and it for example is a metal oxide, and metal oxide for example is aluminium oxide, hafnia (HfO ₂) or other suitable materials.In addition, charge trapping structure 130 also can for example be that particle or block electric charge are absorbed in the discontinuous combination of material, or continuous rete as shown in FIG..

For instance, similarly be the storage unit of PHINES structure have thickness range in the following oxide layer between 2～10nm, thickness range in the charge immersing layer between 2～10nm and thickness range oxide layer between 2～15nm.

In certain embodiments, gate comprises the material with a work function, and this work function is greater than the intrinsic work function of n type silicon, or greater than 4.1eV, is preferably greater than 4.25eV, and comprises it for example being greater than 5eV.The material of typical case's gate comprises that p type polysilicon, titanium nitride (TiN), platinum (Pt) and other have the metal and the material of high work function.In addition, the material with relative high work function that other are suitable comprises metal, metal alloy, metal nitride and metal oxide, but is not limited to these materials.Wherein, above-mentioned metal for example is ruthenium (Ru), iridium (Ir), nickel (Ni) and cobalt (Co), and metal alloy for example is ruthenium-titanium alloy and Ni-Ti alloy, and metal oxide for example is ruthenium-oxide (RuO ₂).The gate material of high work function can cause having higher electron tunneling to inject carrier than general n type polycrystalline silicon gate pole, and is 3.15eV with silicon dioxide as the injection carrier of the n type polycrystalline silicon gate pole of last dielectric structure.Therefore, present embodiment is to use the material with the injection carrier that is higher than about 3.15eV as gate and last dielectric structure, and it for example is to be higher than about 3.4eV, is preferably to be higher than about 4eV.For with the p type polycrystalline silicon gate pole of silicon dioxide for last dielectric structure, it injects carrier is about 4.25eV, and with respect to the born of the same parents of the n type polycrystalline silicon gate pole with dioxide dielectric structure, its convergent born of the same parents' final start voltage is the about 2V of reduction.

In Figure 1A, the drain side of storage unit is by sequencing, its for example be by hole between valence band-conduction band inject (band-to-band hole injection) to the drain side of charge trapping structure 130 to carry out programming operations.In addition, the source side of storage unit is erased, and it for example is by F-N tunnelling (Fowler-Nordheim tunneling) effect, from gate 110 to charge trapping

structure

130, and 170 utilize passage to reset operation to inject electronics to carry out erase operation for use from charge trapping structure 130 to substrate.

In the bias arrangement of Figure 1A, be that the source side of charge trapping structure 130 is carried out read operation, the voltage (V of gate 110 wherein _GATE) be-10V, the voltage (V of source electrode 150 _SOURCE) be the voltage (V of 2V, drain electrode 160 _DRAIN) for floating and the voltage (V of substrate 170 _SUBSTRATE) be 0V.The storage unit of Figure 1B is similar to the storage unit of Figure 1A, except Figure 1B carries out read operation rather than carries out the read operation in source side in the drain side of charge trapping structure.In the bias arrangement of Figure 1B, be that the drain side of charge trapping structure 130 is carried out read operation, the voltage (V of gate 110 wherein _GATE) be-10V, the voltage (V of source electrode 150 _SOURCE) for floating, drain 160 voltage (V _DRAIN) be the voltage (V of 2V and substrate 170 _SUBSTRATE) be 0V.Yet bias arrangement is by determining between the different end points, for example at n ⁺In the type impure source 150 (Figure 1A) or n ⁺In the drain electrode 160 (Figure 1B) that type mixes, can enough bend to electric current between initiation valence band-conduction band by band, but still can keep substrate 170 and source electrode 150 (Figure 1A) or the potential difference (PD) that drains between 160 (Figure 1B) enough low to the sequencing state not taking place, its discussion that in following Fig. 2 A, continues.

In the bias arrangement of Figure 1A and Figure 1B, substrate 170 and n that the P type mixes ⁺Engaging zones between the type impure source 150, or the substrate 170 and the n of the doping of P type ⁺Engaging zones between the drain electrode 160 that type mixes has all shown the behavior that reverse biased p-n engages.Yet, gate voltage (V _GATE) can cause can be with enough bendings so that at n ⁺Type impure source 150 (Figure 1A) or n ⁺Produce tunnelling between valence band-conduction band in the drain electrode 160 (Figure 1B) that type mixes.And, source electrode 150 or the drain high-dopant concentration in 160, the high charge density in space charge region (space charge region), and follow because of voltage changes and shorten the length of space charge region, all can cause contribution to being with rapid bending.Therefore, valency can be with the electronics in (valence band) can tunnelling by forbidden band energy gap (forbidden gap) to conduction band (conductor band), and electronics can be along the potential energy slope (potential hill) drift down and be deep into n ⁺Type impure source 150 (Figure 1A) or n ⁺In the drain electrode 160 (Figure 1B) that type mixes.Similarly, the hole can drift about up along the potential energy slope, and away from n ⁺Type impure source 150 (Figure 1A) or n ⁺The drain electrode 160 (Figure 1B) that type mixes, and the substrate 170 of mixing towards the p type.

Voltage (the V of gate 110 _GATE) the close voltage (V of the part substrate 170 of dielectric structure (following oxide layer) 140 down of may command _SUBSTRATE), in other words, the close voltage (V of the part substrate 170 of dielectric structure (following oxide layer) 140 down _SUBSTRATE) dielectric structure (following oxide layer) 140 and n under the may command ⁺Between the type impure source 150 (Figure 1A) or down dielectric structure (following oxide layer) 140 and n ⁺Band curvature degree between the drain electrode 160 (Figure 1B) that type mixes.Therefore, as the voltage (V of gate 110 _GATE) become more negative, then near the voltage (V of the part substrate 170 of dielectric structure (following oxide layer) 140 down _SUBSTRATE) also can become more negative, and cause n ⁺Type impure source 150 (Figure 1A) or n ⁺In the drain electrode 160 (Figure 1B) that type mixes darker band curvature is arranged.In addition, at least the electric current between multivalence band-conduction band flows will to have some contributions can make more, for example (1) is increased in occupying the electronic energy rank and do not occupy overlapping between the electronic energy rank on bending energy band opposite side on bending energy band one side, and (2) occupy the electronic energy rank and do not occupy narrower energy barrier width (" semiconductor element physics (Physics ofSemiconductor) " Shi Min in 1981) between the electronic energy rank

As mentioned above, the drain side of charge trapping structure 130 occupies by sequencing and by the hole, and is anti-, and the hole that the source side of charge trapping structure 130 is erased and quilt also will be lacked than the drain side of charge trapping structure 130 occupies.Therefore, according to Gauss's Law (Gauss ' s Law), when applying on gate 110-10V, the bias condition of then descending dielectric structure (following oxide layer) 140 is for to have the bias voltage more negative than drain side in source side.Therefore, in the bias arrangement of Figure 1A, when the source side of charge trapping structure 130 is carried out read operation, have between source electrode 150 and the substrate 170 than multiple current and flow, and its magnitude of current is in the bias arrangement of Figure 1B, when the drain side of charge trapping structure 130 is carried out read operation, between drain electrode 160 and the substrate 170 more than the mobile electric current.

The difference of carrying out read operation and carrying out programming operations in the bias arrangement of Figure 1A and Figure 1B in the bias arrangement of Fig. 2 A has shown a balance.For read operation, the potential difference (PD) between source electrode or the drain electrode can not cause basic carrier (carrier) number to have influence on charge storage state by tunnel oxide (referring to the following dielectric structure (following oxide layer) 140 of Figure 1A and Figure 1B, the following dielectric structure 240 of Fig. 2 A).On the contrary, for programming operations, potential difference (PD) between source electrode or the drain electrode is enough to cause basic carrier number by tunnel oxide (referring to the following dielectric structure (following oxide layer) 140 of Figure 1A and Figure 1B, the following dielectric structure 240 of Fig. 2 A), and can have influence on charge storage state.

It is described to see also figure Fig. 2 A, Fig. 2 B and Fig. 2 C, is a kind of schematic diagram of storage unit, and it is presented at the state of enterprising line program operation of storage unit and erase operation for use.As general custom, programming operations refers to and makes the net charge corrigendum that is stored in the charge trapping structure, for example by making other holes enter in the charge trapping structure or electronics being shifted out from charge structure.Erase operation for use refers to and makes the net charge that is stored in the charge trapping structure more negative, for example by other holes being shifted out from charge structure or electronics being entered in the charge trapping structure.Yet the present invention comprises sequencing and generation of erasing and method, and wherein sequencing refers to the more negative or corrigendum of the net charge that is stored in the charge trapping structure, and erasing refers to the more negative or corrigendum of the net charge that is stored in the charge trapping structure.

Fig. 2 A utilizes between valence band-conduction band tunnelling to cause that hot hole injects to finish the mode of operation of sequencing.Fig. 2 B and Fig. 2 C utilize negative gate voltage and electric field to cause electron tunneling (being so-called F-N tunnelling) and cause tunnelling current from gate to charge trapping structure, or utilize negative basic voltage and electric field to cause electron tunneling (being so-called F-N tunnelling) and cause tunnelling current from substrate to charge trapping structure, to finish the mode of operation of erasing.Shown in Fig. 2 A, apply to apply on 0V and the gate 210 on 5V, the source electrode 250 on 260 in drain electrode and apply-6V, and substrate 270 ground connection can make right bit carry out sequencing.Above-mentioned sequencing meeting causes that hot hole has enough energy, passes down dielectric structure 240 in the drain side 233 of charge trapping structure 230 with jump, and for example hole 234 can be stored in the drain side 233 of charge trapping structure 230.Similarly, apply 5V on the source electrode 250, drain electrode applies on 0V and the gate 210 on 260 and applies-6V, and substrate 270 ground connection can make left bit carry out sequencing (not illustrating).Above-mentioned sequencing meeting causes that hot hole has enough energy, passes down dielectric structure 240 in the source side of charge trapping structure 230 with jump.Shown in Fig. 2 B, be utilize electric field auxiliary electron tunnelling by last dielectric structure 220 and following dielectric structure 240 erasing, and electric field be by in the relative negative bias on the gate and the substrate mutually forward bias cause.For instance, on gate, apply-20V, and make substrate ground connection, the bit in the storage unit is erased.Shown in Fig. 2 C, be to utilize electric field auxiliary electron tunnelling erasing, and electric field is to cause with forward bias mutually on the gate by the relative negative bias in substrate, source electrode and the drain electrode.For instance, in substrate, source electrode and drain electrode, apply-20V, and make gate ground connection, the bit in the storage unit is erased.In addition, in the operation of PHINES type storage unit, the technology that can use other sequencing and erase, for example United States Patent (USP) announces the 6th, 690, No. 601 describe, and also can use other storage unit or operation.

See also shown in Fig. 3 A and Fig. 3 B, be the sensing window of the desirable storage unit of contrast with by reverse read operation graph of a relation with the sensing window of the storage unit that reads.Wherein, curve 310 is represented the current curve that reads of first bit, and curve 320 is represented the current curve that reads of second bit.During the time interval 330, first bit is to be in the sequencing state, and during the time interval 340, second bit is to be in the sequencing state.The operation of above-mentioned sequencing (injecting by hot hole) can increase the electric current (channel current) in the reverse read operation, and the electric current (BTB electric current) in the BTB sense operation is descended, and it is represented by the sensing window 350 of storage unit reading current intervals.

In Fig. 3 A, desirable storage unit has narrow relatively sensing window 350.During the time interval 330, when first bit is in the programming operations state, the reading current curve 310 and can be increased to the most significant digit standard of first bit from the lowest order standard.And during the time interval 330, what the programming operations state of first bit can not have influence on second bit reads current curve 320.In addition, during the time interval 340, when second bit is in the programming operations state, the reading current curve 320 and can be increased to the most significant digit standard of second bit from the lowest order standard.And during the time interval 340, what the programming operations state of second bit can not have influence on first bit reads current curve 310.

In Fig. 3 B, because the influence of the second bit effect, by the reverse read operation, reading of storage unit can have narrow relatively sensing window, and it is described as follows.During the time interval 330, when first bit is in the programming operations state, the reading current curve 310 and can be increased to high levels 364 of first bit from lowest order standard 360.And during the time interval 330, what the programming operations state of first bit can influence second bit reads current curve 320, and makes it be increased to low level 362 from lowest order standard 360.In addition, during the time interval 340, when second bit is in the programming operations state, the reading current curve 320 and can be increased to most significant digit standard 366 of second bit from low level 362.And during the time interval 340, what the programming operations state of second bit can influence first bit reads current curve 310, and makes it be increased to most significant digit standard 366 from high levels 364.Therefore, when on one of storage unit bit, carrying out reverse read when operation, final read electric current and can be influenced by the programming operations state of another bit or erase operation for use state basically.And, in reverse read operating period, a gate voltage that has applied can make that producing the phenomenon of vague and general and counter-rotating and the part substrate below another bit in the part substrate below another bit produces the difficulty that the phenomenon that electrically punctures (punch through) becomes.

See also shown in Fig. 4 A, Fig. 4 B and Fig. 4 C, be between the enterprising line program operation of storage unit, erase operation for use and valence band-conduction band read operation read electric current to time relation figure.

In the graph of a relation of Fig. 4 A, storage unit is to carry out erase operation for use by electric field auxiliary electron tunnelling, and electric field is by high relatively negative bias being arranged on the gate and having high relatively positive bias to be caused in substrate, and first electric charge of storage unit is absorbed in part 410 and second electric charge, and to be absorbed in part 420 be to be in the sequencing state.In addition, the electric charge on the storage unit is absorbed in part and can be erased simultaneously, its can by on gate, apply-19.5V with make substrate ground connection, and source electrode and drain electrode be to float, to finish erase operation for use.For each data point among the figure, read operation be by apply-10V is to gate, and applies source electrode that 2V is read to the Partial charge immersal structure and one of them of drain electrode, and the other end of source electrode and drain electrode floated, and makes substrate ground connection.In addition,, then can apply 2V, and drain electrode is floated to source electrode if carry out read operation in the source side of charge trapping structure.If the drain side in charge trapping structure is carried out read operation, then can apply 2V to drain electrode, and source electrode is floated.

Fig. 4 B be first electric charge be absorbed in that part is in the sequencing state read electric current to time relation figure, Fig. 4 C be second electric charge be absorbed in that part is in the sequencing state read electric current to time relation figure.Wherein, on behalf of second electric charge, the current curve that reads that on behalf of first electric charge, curve 410 be absorbed in part, curve 420 be absorbed in the current curve that reads of part.In Fig. 4 B, first electric charge be absorbed in part be by apply-8V to gate, apply 5V to the first end (this first end is that storage first electric charge near charge trapping structure is absorbed in part), second end is floated (this second end is that storage first electric charge away from charge trapping structure is absorbed in part) and make substrate ground connection, to carry out programming operations.In Fig. 4 B, when being absorbed in part, first electric charge is in the sequencing state, first electric charge be absorbed in part read current curve 410 can fall to from the higher levels of about 100nA about 1nA than low level, and this first electric charge be absorbed in sequencing partly can not have influence on basically second electric charge be absorbed in partly read current curve 420.In Fig. 4 C, second electric charge be absorbed in part be by apply-8V to gate, apply 5V to the second end (this second end is that storage second electric charge near charge trapping structure is absorbed in part), first end is floated (this first end is that storage second electric charge away from charge trapping structure is absorbed in part) and make substrate ground connection, to carry out programming operations.In Fig. 4 C, when being absorbed in part, second electric charge is in the sequencing state, second electric charge be absorbed in part read current curve 420 can fall to from the higher levels of about 100nA about 1nA than low level, and this second electric charge be absorbed in sequencing partly can not have influence on basically first electric charge be absorbed in partly read current curve 410.For each data point among Fig. 4 B and Fig. 4 C, read operation be by apply-10V is to gate, apply source electrode and drain electrode that 2V is read to the Partial charge immersal structure one of them, and the source electrode and the drain electrode other end are floated, and are made substrate ground connection.In addition,, then can apply 2V, and drain electrode is floated to source electrode if the source side of charge trapping structure is carried out read operation.If the drain side of charge trapping structure is carried out read operation, then can apply 2V to drain electrode, and source electrode is floated.

Sensing window among Fig. 4 B and Fig. 4 C is relatively wide, and this is because the read operation between valence band-conduction band is to be positioned at first end or second end.First electric charge be absorbed in the part on carry out read operation between valence band-conduction band and produce read electric current be with respect to second electric charge be absorbed in the part logic state comparatively insensitive, and in second electric charge be absorbed in the part carry out read operation between valence band-conduction band and produce read electric current be relative first electric charge be absorbed in the part logic state comparatively insensitive.Read operation is with respect to there not being the influence that second electric charge is absorbed in part between valence band-conduction band, the feature of this influence is reverse read operation, and carries out read operation and the electric current that reads that produces is comparatively independent with respect to the data storing at the charge trapping structure opposite side on charge trapping structure one side.Each electric charge is absorbed in part can store a bit or multiple bit, for instance, can store two bits if each electric charge is absorbed in part, then have 4 electric charges not connect the position accurate.

Seeing also shown in Fig. 5 A and Fig. 5 B, is the schematic diagram of the storage unit of serial connection, and it is presented at the mode of operation of the enterprising line programization of storage unit.

In Fig. 5 A, one of them that contains serial connection storage unit that the series connection of N storage unit couples is by sequencing.Wherein, the voltage (V of substrate 502 _BUB) be 0V, chosen gate with the storage unit 540 of carrying out sequencing has-voltage (V of 5V _WL3).More particularly, charge trapping structure 542 partly is chosen carrying out sequencing, and the method that charge trapping structure 542 is partly carried out sequencing is by the voltage (V that applies 10V _SLG1) to the gate of transmission transistor (pass transistor) 510, and open this transmission transistor 510 and chosen.In addition, also comprise the voltage (V that applies 10V _WL1, V _WL2) to the gate of storage unit 520 and 530,, these gate voltage have 5V voltage (V and being electric property couplings _BL1) the first bit line 505 to the source electrode of selected storage unit 540 and drain electrode one of them.Corresponding to source electrode and one of them selected part charge trapping structure 542 of drain electrode by sequencing, its for example by hot hole between valence band-conduction band to carry out sequencing.In addition, the residue transistor of serial connection is by the voltage (V that applies 0V _WL4, V _WL5, V _WL6, V _WLN) to the gate of storage unit 550,560,570 and 580, and the voltage (V that applies 0V _SLG2) to the gate of transmission transistor 590 and close (turnoff).Above-mentioned gate voltage be from the source electrode of selected storage unit 540 and drain electrode wherein another with the electrical decoupling second bit line 595, and corresponding to source electrode and drain electrode wherein another selected part charge trapping structure be not by sequencing.

In Fig. 5 B, one of them that contains serial connection storage unit that the series connection of N storage unit couples is by sequencing.Wherein, the gate voltage (V of 0V _SLG1, V _WL1, V _WL2) be to be applied to the gate of transmission transistor 510 and the gate of

storage unit

520 and 530, the gate voltage (V of 10V _SLG2, V _WL4, V _WL5, V _WL6, V _WLN) be to be applied to the gate of transmission transistor 590 and the gate of storage unit 550,560,570 and 580.Relevant with the bias arrangement of Fig. 5 A, the first bit line 505 is that electric property coupling arrives the source electrode of storage unit 540 and one of them of drain electrode, so that charge trapping structure 542 sequencing of part, and in the bias arrangement of Fig. 5 B, the second bit line 595 is wherein another that electric property coupling arrives the source electrode of storage unit 540 and drain electrode, so that charge trapping structure 544 sequencing of part.

Seeing also shown in Fig. 6 A and Fig. 6 B, is the schematic diagram of the storage unit of serial connection, and it is presented at the state that carries out read operation on the storage unit.

In Fig. 6 A, one of them of storage unit that contains the serial connection that the series connection of N storage unit couples is to be read.Wherein, the voltage (V of substrate 602 _BUB) be 0V, selected gate with the storage unit 640 that reads has-voltage (V of 10V _WL3).More particularly, charge trapping structure 642 partly is chosen reading, and the method that charge trapping structure 642 partly reads is by the voltage (V that applies 10V _SLG1) to the gate of transmission transistor (pass transistor) 610, and open this transmission transistor 610 and chosen.In addition, also comprise the voltage (V that applies 10V _WL1, V _WL2) to the gate of storage unit 620 and 630,, these gate voltage have 2V voltage (V and being electric property couplings _BL1) the first bit line 605 to the source electrode of the storage unit of selecting 640 and drain electrode one of them.Corresponding to source electrode and one of them selected part charge trapping structure 642 of drain electrode is to be read, its for example by hot hole between valence band-conduction band to read.In addition, the residue transistor of serial connection is by the voltage (V that applies 0V _WL4, V _WL5, V _WL6, V _WLN) to the gate of storage unit 650,660,670 and 680, and the voltage (V that applies 0V _SLG2) to the gate of transmission transistor 690 and close.Above-mentioned gate voltage be from the source electrode of selected storage unit 640 and drain electrode wherein another with the electrical decoupling second bit line 695, and corresponding to source electrode and the drain electrode wherein another not the choosing bonding part part charge trapping structure be not to be read.

In Fig. 6 B, one of them of storage unit that contains the serial connection that the series connection of N storage unit couples is to be read.Wherein, the gate voltage (V of 0V _SLG1, V _WL1, V _WL2) be to be applied to the gate of transmission transistor 610 and the gate of

storage unit

620 and 630, the gate voltage (V of 10V _SLG2, V _WL4, V _WL5, V _WL6, V _WLN) be to be applied to the gate of transmission transistor 690 and the gate of storage unit 650,660,670 and 680.Relevant with the bias arrangement of Fig. 6 A, the first bit line 605 is that electric property coupling arrives the source electrode of storage unit 640 and drains one of them, so that the charge trapping structure 642 of part reads, and in the bias arrangement of Fig. 6 B, the second bit line 695 is wherein another that electric property coupling arrives the source electrode of storage unit 640 and drain electrode, so that the charge trapping structure 644 of part reads.

Seeing also shown in Fig. 7 A and Fig. 7 B, is the schematic diagram of the storage unit of serial connection, and it is presented at the state that carries out erase operation for use on the storage unit.

In Fig. 7 A, all storage unit that contain in the serial connection storage unit that the series connection of N storage unit couples are erased.Wherein, the voltage (V of substrate 702 _BUB) be 10V, storage unit 720,730,740,750,760,770 and 780 gate have-10V voltage (V _WL1, V _WL2, V _WL3, V _WL4, V _WL5, V _WL6, V _WLN),

transmission transistor

710 and 790 gate are floated, and bit

line

705 and 795 is floated.Storage unit 720,730,740,750,760,770 and 780 is erased, its for example be by electronics from gate to charge trapping structure the F-N tunnelling and the F-N tunnelling of electronics from charge trapping structure to substrate to carry out.

In Fig. 7 B, all storage unit that contain in the serial connection storage unit that the series connection of N storage unit couples are erased.Wherein, the voltage (V of substrate 702 _BUB) be-10V that storage unit 720,730,740,750,760,770 and 780 gate have 10V voltage (V _WL1, V _WL2, V _WL3, V _WL4, V _WL5, V _WL6, V _WLN), the voltage (V of

transmission transistor

710 and 790 gate _SLG1, V _SLG2) be 5V, and bit

line

705 and 795 is floated.Storage unit 720,730,740,750,760,770 and 780 is erased, its for example be by electronics from substrate to charge trapping structure the F-N tunnelling and the F-N tunnelling of electronics from charge trapping structure to gate to carry out.

See also shown in Figure 8, each storage unit is that electric property coupling arrives a bit line 804 at the most, from another point of view, the structure of Fig. 8 is the structure that is different from Fig. 6 A and Fig. 6 B, and the first bit line 605 among Fig. 6 A and Fig. 6 B and the second bit line 695 are electric property couplings permanently.In the storage unit of each row, storage unit is selected by opening the character line, and above-mentioned character line is the gate voltage (V by storage unit 820,830,840,850,860,870 and 880 _WL1, V _WL2, V _WL3, V _WL4, V _WL5, V _WL6, V _WLN) set.For instance, the method for controlling a known storage unit and be reading state or sequencing state can be by opening one of them of

transmission transistor

810 and 890, and

close transmission transistor

810 and 890 wherein another.Though the

transmission transistor

810 and 890 that illustrates among Fig. 8 is not a storage unit, and in other embodiments,

transmission transistor

810 and 890 also has the storage unit of charge trapping structure.

See also shown in Fig. 9, memory cell array is erased, and this memory cell array has the storage unit of multiple serial connection, and the storage unit of each serial connection includes N storage unit series connection and couples.Wherein, the voltage (V of substrate 902 _SUB) be 10V, the character line 920,930,940,950,960,970 and 980 of storage unit has-voltage (V of 10V _WL1, V _WL2, V _WL3, V _WL4, V _WL5, V _WL6, V _WLN) erasing,

transmission transistor

910 and 990 character line have the voltage (V of 0V _SLG1, V _SLG2), and bit line 903,904,905,906 and 907 is to float.The said memory cells array is erased, its for example be by electronics from gate (comprising source electrode and drain electrode) to charge trapping structure the F-N tunnelling and the F-N tunnelling of electronics from charge trapping structure to substrate to carry out.

See also shown in Figure 10, memory cell array is erased, and this memory cell array has the storage unit of multiple serial connection, and the storage unit of each serial connection includes N storage unit series connection and couples.Wherein, the voltage (V of substrate 1002 _SUB) be-10V that the

character line

1020,1030,1040,1050,1060,1070 and 1080 of storage unit has the voltage (V of 10V _WL1, V _WL2, V _WL3, V _WL4, V _WL5, V _WL6, V _WLN) erasing,

transmission transistor

1010 and 1090 character line have the voltage (V of 5V _SLG1, V _SLG2), and

bit line

1003,1004,1005,1006 and 1007 has-voltage (V of 10V _BL1, V _BL2, V _BL3, V _BL4, V _BL5).The said memory cells array is erased, its for example be by electronics from substrate (comprising source electrode and drain electrode) to charge trapping structure the F-N tunnelling and the F-N tunnelling of electronics from charge trapping structure to gate to carry out.

See also shown in Figure 11, it is to carry out sequencing that some storage unit are arranged on the memory cell array of the storage unit that multiple serial connection is arranged, and wherein the storage unit of each serial connection comprises that N storage unit series connection couples.Wherein, the voltage (V of substrate 1102 _SUB) be 0V, the character line 1140 of storage unit has-voltage (V of 5V _WL3) to carry out sequencing.By the selected storage unit of character line 1140, then charge trapping structure part 1143,1144,1145,1146 and 1147 is by the voltage (V with 10V _SLG1) open transmission transistor character line 1110 and chosen.Voltage (V between storage unit character line 1120 and 1130 _WL1, V _WL2) be set at 10V, and other transmission transistor character lines 1190 and unused memory cell character line 1150,1160,1170 and 1180 are the voltage (V with 0V _WL3, V _WL4, V _WL5, V _WL6, V _WLN) and be closed.In selected charge trapping structure part 1143,1144,1145,1146 and 1147, charge trapping structure part 1144,1146 and 1147 is by the voltage (V that sets bit line 1104,1106 and 1107 _BL2, V _BL4, V _BL5) be that 5V is to carry out sequencing.In addition, in selected charge trapping structure part 1143,1144,1145,1146 and 1147, charge trapping structure part 1143 and 1145 is by the voltage (V that sets bit line 1103 and 1105 _BL1, V _BL3) can not carry out sequencing for 0V.

See also shown in Figure 12, it is to carry out some storage unit sequencing similar in appearance to Figure 11.Voltage (the V of substrate 1202 _SUB) be 0V, by the selected storage unit of character line 1240, then charge trapping

structure part

1243,1244,1245,1246 and 1247 is by the voltage (V with 10V _SLG2) open transmission transistor character line 1290 and chosen.Voltage (V between 1250,1260,1270 and 1280 on storage unit character line _WL4, V _WL5, V _WL6, V _WLN) be set at 10V, and other transmission transistor character lines 1210 and unused memory

cell character line

1220 and 1230 are the voltage (V with 0V _SLG1, V _WL1, V _WL2) and be closed.In selected charge trapping

structure part

1243,1244,1245,1246 and 1247, charge trapping

structure part

1244,1246 and 1247 is by the voltage (V that sets

bit line

1204,1206 and 1207 _BL2, V _BL4, V _BL5) be that 5V is to carry out sequencing.In addition, in selected charge trapping

structure part

1243,1244,1245,1246 and 1247, charge trapping

structure part

1243 and 1245 is by the voltage (V that sets

bit line

1203 and 1205 _BL1, V _BL3) can not carry out sequencing for 0V.

See also shown in Figure 13, it is to read that some storage unit are arranged on the memory cell array of the storage unit that multiple serial connection is arranged, and wherein the storage unit of each serial connection comprises that N storage unit series connection couples.As shown in the figure, the voltage (V of substrate 1302 _SUB) be 0V, the character line 1340 of storage unit has-voltage (V of 10V _WL3) to read.By the selected storage unit of character line 1340, then charge trapping structure part 1343,1344,1345,1346 and 1347 is by the voltage (V with 10V _SLG1) open transmission transistor character line 1310 and chosen.Voltage (V between storage unit character line 1320 and 1330 _WL1, V _WL2) be set at 10V, and other transmission transistor character lines 1390 and unused memory cell character line 1350,1360,1370 and 1380 are the voltage (V with 0V _SLG2, V _WL4, V _WL5, V _WL6, V _WLN) and be closed.Xuan Ding charge trapping structure part 1343,1344,1345,1346 and 1347 is by the voltage (V that sets bit line 1303,1304,1305,1306 and 1307 _BL1, V _BL2, V _BL3, V _BL4, V _BL5) be that 2V is to read.In another embodiment, can be by setting 2V voltage to only being selected on the bit line of data, to carry out read operation.

See also shown in Figure 14, it is to carry out some storage unit similar in appearance to Figure 13 to read.。As shown in the figure, the voltage (V of substrate 1402 _SUB) be 0V, by the selected storage unit of character line 1440, then charge trapping

structure part

1443,1444,1445,1446 and 1447 is by the voltage (V with 10V _SLG2) open transmission transistor character line 1490 and chosen.Voltage (V between 1450,1460,1470 and 1480 on storage unit character line _WL4, V _WL5, V _WL6, V _WLN) be set at 10V, and other transmission transistor character lines 1410 and unused memory

cell character line

1420 and 1430 are the voltage (V with 0V _SLG1, V _WL1, V _WL2) and be closed.Xuan Ding charge trapping

structure part

1443,1444,1445,1446 and 1447 is by the voltage (V that sets

bit line

1403,1404,1405,1406 and 1407 _BL1, V _BL2, V _BL3, V _BL4, V _BL5) be that 2V is to read.In another embodiment, can be by setting 2V voltage to only being selected on the bit line of data, to carry out read operation.

Seeing also shown in Figure 15ly, is the simple block diagram according to the integrated circuit of one of the present invention embodiment.Integrated circuit 1550 comprises memory array 1500, and it is to utilize charge trapping memory cells to be carried out, and is positioned at at semiconductor-based the end.Integrated circuit 1550 also comprises column decoder 1501, and it couples most the character lines 1502 along the row configuration of memory array 1500, and row decoder 1503, and it couples most the character lines 1504 along the row configuration of memory array 1500.In addition, on bus 1505, supply address to column decoder 1501 and row decoder 1503, and sensing amplifier in the square 1506 and data input structure are to couple row decoder 1503 by data bus 1507.Data are by Data In-Line 1511 I/O part from the integrated circuit 1550, or are fed to integrated circuit 1550 from other Data Source inside or outside.Data are to be fed to I/O part on the integrated circuit 1550 by the sensing amplifier of DOL Data Output Line 1515 from square 1506, or other data endpoints are inner or outside to integrated circuit 1550.In addition, the application of bias arrangement status mechanism 1509 control bias arrangement supply voltages 1508 and the sequencing of storage unit, the configuration of reading and erasing, the application examples of wherein above-mentioned bias arrangement supply voltage 1508 verifies as erase checking and sequencing, and the sequencing of storage unit, reads and the configuration of erasing for example is an electric current between valence band-conduction band.

The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims

1, a kind of method of operating of storage unit, be applicable to that this storage unit contains a gate and the one source pole and the drain electrode that are arranged in a substrate, and this storage unit comprises a upper dielectric layer, have part to should source electrode and one of this drain electrode charge trapping structure and one of between this gate and this substrate time dielectric layer, it is characterized in that this method may further comprise the steps:

Selection is to should source area or this charge trapping structure of part of this drain region, to determine one of selected this charge trapping structure of part charge storage state;

Use one first bias arrangement, determining this charge storage state of selected this charge trapping structure of part, wherein said first bias arrangement maybe applies one first voltage difference between one of them of this drain electrode in this substrate and this source electrode; And

Measurement maybe this drain electrode electric current one of between one of them of this substrate and this source electrode of flowing through is to determine this charge storage state of selected this charge trapping structure of part.

2, the method for operating of storage unit according to claim 1, it is characterized in that this source electrode wherein maybe wherein another of this drain electrode be to float.

3, the method for operating of storage unit according to claim 1, it is characterized in that wherein said first bias arrangement maybe produces one second voltage difference between wherein another of this drain electrode in this gate and this source electrode, wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

4, the method for operating of storage unit according to claim 1 it is characterized in that wherein said first bias arrangement maybe produces one second voltage difference of 5V in this gate and this source electrode between wherein another of this drain electrode, and this first voltage difference is less than 5V.

5, the method for operating of storage unit according to claim 1 is characterized in that wherein said first bias arrangement makes electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least.

6, the method for operating of storage unit according to claim 1, this electric current that it is characterized in that wherein said measurement maybe one of them of this drain electrode of this substrate and this source electrode of flowing through.

7, the method for operating of storage unit according to claim 1 is characterized in that wherein said substrate is to be arranged in one of semiconductor substrate well region.

8, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Use one second bias arrangement, in this charge trapping structure, increase by a clean positive charge, to adjust this charge storage state; And

Use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, to adjust this charge storage state.

9, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Use one second bias arrangement, the hot hole tunnelling increases by a clean positive charge between valence band-conduction band in this charge trapping structure by utilizing, to adjust this charge storage state; And

Use one the 3rd bias arrangement, by utilizing the F-N tunnelling in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

10, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Use one the 3rd bias arrangement, by utilizing the channel hot electron injection current in this charge trapping structure, to increase by a net negative charge, to adjust this charge storage state.

11, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge by utilizing passage to open beginning second electron injection current, to adjust this charge storage state.

12, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this substrate, to adjust this charge storage state.

13, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Use one the 3rd bias arrangement, move increase by one net negative charge in this charge trapping structure by the electronics that is used between this charge trapping structure and this gate, to adjust this charge storage state.

14, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Use one the 3rd bias arrangement, in this charge trapping structure, increase by a net negative charge, adjusting this charge storage state,

Wherein this electric current by the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement is 100nA, and is 1nA by this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement.

15, the method for operating of storage unit according to claim 1 is characterized in that it also comprises:

Be greater than by 10 times in this electric current of the measurement of another this charge storage state of adjusting wherein of this second bias arrangement and the 3rd bias arrangement wherein by this electric current of the measurement of one of them this charge storage state of adjusting of this second bias arrangement and the 3rd bias arrangement.

16, the method for operating of storage unit according to claim 1, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly are to store a bit.

17, the method for operating of storage unit according to claim 1, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly are to store multiple bit.

18, the method for operating of storage unit according to claim 1 is characterized in that the hot hole that produces during described therein first bias arrangement is not enough to disturb this charge storage state.

19, a kind of non-volatile memory medium is characterized in that it comprises:

One substrate contains an one source pole and a drain electrode;

Once dielectric layer is couple to this substrate;

One charge trapping structure is couple to and has part to should source electrode and this time dielectric layer of this drain electrode, and each part has a charge storage state;

One upper dielectric layer is couple to this charge trapping structure;

One gate is couple to this upper dielectric layer; And

One logic uses one first bias arrangement to determine this charge storage state, and measure flow through this substrate and this source electrode maybe this drain electrode electric current is determining this charge storage state of selected this charge trapping structure of part one of between one of them, wherein said first bias arrangement maybe applies one first voltage difference between one of them of this drain electrode in this substrate and this source electrode.

20, non-volatile memory medium according to claim 19, it is characterized in that this source electrode wherein maybe wherein another of this drain electrode be to float.

21, non-volatile memory medium according to claim 19, it is characterized in that wherein said first bias arrangement maybe produces one second voltage difference between wherein another of this drain electrode in this gate and this source electrode, wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

22, non-volatile memory medium according to claim 19 it is characterized in that wherein said first bias arrangement maybe produces one second voltage difference of 5V in this gate and this source electrode between wherein another of this drain electrode, and this first voltage difference is less than 5V.

23, non-volatile memory medium according to claim 19 is characterized in that wherein said first bias arrangement makes electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least.

24, flow through one of them of this substrate and this source electrode and this drain electrode of non-volatile memory medium according to claim 19, this electric current that it is characterized in that wherein said measurement.

25, non-volatile memory medium according to claim 19 is characterized in that wherein said substrate is to be arranged in one of semiconductor substrate well region.

26, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

27, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

28, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

29, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

30, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

31, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

32, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

Use one second bias arrangement, by in this charge trapping structure, increasing by a clean positive charge, to adjust this charge storage state; And

Use one the 3rd bias arrangement, by in this charge trapping structure, increasing by a net negative charge, adjusting this charge storage state,

33, non-volatile memory medium according to claim 19 is characterized in that wherein said logic also comprises:

Use one second bias arrangement, one of in this charge trapping structure, increase clean positive charge, to adjust this charge storage state; And

Use one the 3rd bias arrangement, one of in this charge trapping structure, increase net negative charge, adjusting this charge storage state,

34, non-volatile memory medium according to claim 19, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly are to store a bit.

35, non-volatile memory medium according to claim 19, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly are to store multiple bit.

36, non-volatile memory medium according to claim 19 is characterized in that the hot hole that produces during wherein said first bias arrangement is not enough to disturb this charge storage state.

37, a kind of manufacture method of non-volatile memory medium is characterized in that it may further comprise the steps:

Provide a substrate, and this substrate contains an one source pole and a drain electrode;

Providing, dielectric layer is couple to this substrate;

Provide a charge trapping structure to be couple to have part to should source electrode and this time dielectric layer of this drain electrode, and each part have a charge storage state;

Provide a upper dielectric layer to be couple to this charge trapping structure;

Provide a gate to be couple to this upper dielectric layer; And

Provide a logic to use one first bias arrangement to determine this charge storage state, and measure flow through this substrate and this source electrode maybe this drain electrode electric current is determining this charge storage state of selected this charge trapping structure of part one of between one of them, wherein said first bias arrangement maybe applies one first voltage difference between one of them of this drain electrode in this substrate and this source electrode.

38, according to the manufacture method of the described non-volatile memory medium of claim 37, it is characterized in that this source electrode wherein maybe wherein another of this drain electrode be to float.

39, according to the manufacture method of the described non-volatile memory medium of claim 37, it is characterized in that wherein said first bias arrangement produces one second voltage difference between wherein another of this gate and this source electrode or this, wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band one conduction band to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

40, according to the manufacture method of the described non-volatile memory medium of claim 37, it is characterized in that wherein said first bias arrangement maybe produces one second voltage difference of 5V in this gate and this source electrode between wherein another of this drain electrode, and this first voltage difference is less than 5V.

41,, it is characterized in that wherein said first bias arrangement makes electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least according to the manufacture method of the described non-volatile memory medium of claim 37.

42, according to the manufacture method of the described non-volatile memory medium of claim 37, this electric current that it is characterized in that wherein said measurement maybe one of them of this drain electrode of this substrate and this source electrode of flowing through.

43,, it is characterized in that wherein said substrate is to be arranged in one of semiconductor substrate well region according to the manufacture method of the described non-volatile memory medium of claim 37.

44,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

45,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

46,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

47,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

48,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

49,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

50,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

51,, it is characterized in that wherein said logic also comprises according to the manufacture method of the described non-volatile memory medium of claim 37:

52, according to the manufacture method of the described non-volatile memory medium of claim 37, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly is to store a bit.

53, according to the manufacture method of the described non-volatile memory medium of claim 37, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly is to store multiple bit.

54,, it is characterized in that the hot hole that wherein produces is not enough to disturb this charge storage state during described first bias arrangement according to the manufacture method of the described non-volatile memory medium of claim 37.

55, a kind of non-volatile memory medium integrated circuit is characterized in that it comprises:

One storage medium array comprises most row, and each those row comprises most storage unit and is a series connection configuration, and has one first end and one second end, and wherein each those storage unit comprises:

One substrate contains an one source pole and a drain electrode;

Once dielectric layer is couple to this substrate;

One upper dielectric layer is couple to this charge trapping structure;

One first transmission transistor is couple to this first end of this arranged in series;

One second transmission transistor is couple to this second end of this arranged in series;

One first bit line is couple to this first transmission transistor;

One second bit line is couple to this second transmission transistor;

Most character lines are couple to this upper dielectric layer of each those storage unit, and each those character line as a gate so that those storage unit are couple to each those character line; And

One logic is couple to those storage unit, and this logic open this first transmission transistor and this second transmission transistor one of them so that electronics couples a sensing amplifier one of them maybe this drain electrode of this source electrode to those storage unit, select corresponding this source electrode of this charge storage state of part maybe should drain, and this logic uses one first bias arrangement to determine this charge storage state, and electric current is determining this charge storage state of selected this charge trapping structure of part one of between one of them to measure flow through this basal area and this source area or this drain region, and wherein said first bias arrangement maybe applies one first voltage difference between one of them of this drain electrode in this substrate and this source area.

56, according to the described non-volatile memory medium integrated circuit of claim 55, it is characterized in that this source electrode wherein maybe wherein another of this drain electrode be to float.

57, according to the described non-volatile memory medium integrated circuit of claim 55, it is characterized in that wherein said first bias arrangement maybe produces one second voltage difference between wherein another of this drain electrode in this gate and this source electrode, wherein this first voltage difference and this second voltage difference can cause tunnelling current between enough valence band-conduction bands to measurement, and this first voltage difference and this second voltage difference can not change this charge storage state.

58, according to the described non-volatile memory medium integrated circuit of claim 55, it is characterized in that wherein said first bias arrangement maybe produces one second voltage difference of 5V in this gate and this source electrode between wherein another of this drain electrode, and this first voltage difference is less than 5V.

59,, it is characterized in that wherein said first bias arrangement makes electric current between one valence band-conduction band form by this source electrode one of them of this drain electrode maybe at least according to the described non-volatile memory medium integrated circuit of claim 55.

60, according to the described non-volatile memory medium integrated circuit of claim 55, this electric current that it is characterized in that wherein said measurement maybe one of them of this drain electrode of this substrate and this source electrode of flowing through.

61,, it is characterized in that wherein said substrate is to be arranged in one of semiconductor substrate well region according to the described non-volatile memory medium integrated circuit of claim 55.

62,, it is characterized in that wherein said logic also comprises according to the described non-volatile memory medium integrated circuit of claim 55:

63,, it is characterized in that wherein said logic also comprises according to the described non-volatile memory medium integrated circuit of claim 55:

64,, it is characterized in that wherein said logic also comprises according to the described non-volatile memory medium integrated circuit of claim 55:

65,, it is characterized in that wherein said logic also comprises according to the described non-volatile memory medium integrated circuit of claim 55:

66,, it is characterized in that wherein said logic also comprises according to the described non-volatile memory medium integrated circuit of claim 55:

67,, it is characterized in that wherein said logic also comprises according to the described non-volatile memory medium integrated circuit of claim 55:

68,, it is characterized in that wherein said logic also comprises according to the described non-volatile memory medium integrated circuit of claim 55:

69,, it is characterized in that wherein said logic more comprises according to the described non-volatile memory medium integrated circuit of claim 55:

70, according to the described non-volatile memory medium integrated circuit of claim 55, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly is to store a bit.

71, according to the described non-volatile memory medium integrated circuit of claim 55, this charge storage state that it is characterized in that wherein said each this charge trapping structure partly is to store multiple bit.

72,, it is characterized in that the hot hole that wherein produces is not enough to disturb this charge storage state during described first bias arrangement according to the described non-volatile memory medium integrated circuit of claim 55.