CN100543769C - Save the method and apparatus of memory source - Google Patents

Save the method and apparatus of memory source Download PDF

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CN100543769C
CN100543769C CNB2006100636648A CN200610063664A CN100543769C CN 100543769 C CN100543769 C CN 100543769C CN B2006100636648 A CNB2006100636648 A CN B2006100636648A CN 200610063664 A CN200610063664 A CN 200610063664A CN 100543769 C CN100543769 C CN 100543769C
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address
numerical value
carry out
value
abridgment
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CN101211457A (en
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李建儒
陈自强
吴国瑞
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Industrial Technology Research Institute ITRI
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Abstract

A kind of method of saving memory source, it can be used for simplifying and can be used for the address stored space in the form.Analyze the numerical value in all address fields of an original form, to judge whether there is a logical relation between numerical value.If there is this logical relation between numerical value, then will the interior numerical classification of this original form be a plurality of radix values and the simplification value of corresponding each radix value, thereby produces a conversion form.In the value storage that has the identity logic relation in these radix values in this conversion form and the corresponding simplification the value new and identical address field in an abridgment of table.

Description

Save the method and apparatus of memory source
Technical field
The present invention relates to a kind of method and apparatus of saving memory source, and be particularly related to a kind of method and apparatus that in image or Audio Processing process, can save memory source.
Background technology
On dynamic data compression technology, an internal memory can be cut into the block of a plurality of 16x16 usually, be referred to as macro zone block (Macroblock).Each macro zone block (Macroblock) may be partitioned into the block of four 8x8 again, and the block of this 8x8 is the base unit of data compression.
In order to reach the purpose of compression, (Discrete Cosine.Transform can obtain preferable concentration of energy (Energy Concentration) after DCT) to the 8x8 block through discrete cosine transform.Then utilize to quantize (Quantification) and produce the distortion compression, the result of gained passes through variable length code again, and (Variable Length.Coding delivers to output terminal after VLC).Again, in order to obtain preferable code efficiency, usually after quantizing, utilize the similar characteristic of adjacent block to carry out DC coefficient (Directcoefficient, DC) with ac coefficient (Alternate coefficient, AC) estimation (Prediction), with obtain carrying out again after the less difference Run-Length Coding (Run Length Coding, RLC).
Therefore, handle variable-length decoding (Variable Length Decoding at the decoding end, VLD) resulting afterwards coefficient, can't carry out the action of re-quantization (Inverse Quantification) at once, but must carry out difference estimation compensation (Predictionand Compensation of Difference) to DC coefficient value and ac coefficient value earlier.Yet,, must carry out coefficient correction (CoefficientScaling) to reach identical accurate (Level) if present handled 8x8 block adheres to different quantized values separately with the block of institute desire estimation compensation.
The video encoding standard " Video Codec 1 (being designated hereinafter simply as VC-1) " that develops with Microsoft, in order to avoid the real problem of doing division of hardware, employing table look-up (Lookup Table, LUT) mode and cooperate multiplication and shift operation.Therefore, in table look-up (LUT), 64 different quantized values correspond to 64 data respectively, wherein, maximal value accounts for 18 positions, so that table look-up (LUT) needs internal memory that the degree of depth and width be respectively 64 word groups and 18 positions for storage, and resource of some waste internal memory like this.
Therefore, the invention provides a kind of method and apparatus of saving memory source, can effectively save memory source and improve system effectiveness.
Summary of the invention
Based on above-mentioned purpose, the embodiment of the invention has disclosed a kind of method of saving memory source, it is used for simplifying a form and is used for the address stored space, comprises the following steps: to analyze the numerical value in all address fields of an original form, to judge whether there is a logical relation between numerical value; If there is this logical relation between numerical value, then will the interior numerical classification of this original form be a plurality of radix values and the simplification value of corresponding each radix value, thereby produces a conversion form; In the value storage that has the identity logic relation in these radix values in this conversion form and the corresponding simplification the value new and identical address field in an abridgment of table; Obtain one first address of maximum X positions input; This first address is deciphered, to obtain one second address of maximum Y positions, wherein, and X〉Y; According to this first address, this conversion form and this abridgment of table, judge whether to carry out a logical operation; If needn't carry out this logical operation, then directly will be to a decoding numerical value output that should second address; If will carry out this logical operation, then to numerical value that should the address is carried out this logical operation; According to this first address, this conversion form and this abridgment of table, judge whether to carry out a compensation operation; If do not carry out this compensation operation, then directly should decipher numerical value output; And, then this decoding numerical value is carried out an addition or subtraction if will carry out this compensation operation, should decipher numerical value output then.
The embodiment of the invention has more disclosed a kind of device of saving memory source, it is used for simplifying a form and is used for the address stored space, comprise: one first medium, the conversion form that it produces in order to the numerical value in all address fields of inventory analysis and classification one original form; One second medium, it is simplified a plurality of radix values in this conversion form and an abridgment of table of generation with the simplification value of corresponding each radix value in order to storage; One code translator is obtained one first address that maximum X positions are imported, and this first address is deciphered, to obtain one second address of maximum Y positions, wherein, and X〉Y; An and multiplexer, be coupled to this from this first medium, this second medium and this code translator, according to this first address, this conversion form and this abridgment of table, judge whether to carry out a logical operation, if needn't carry out this logical operation, then directly will be to a decoding numerical value output that should second address, and if will carry out this logical operation, then to numerical value that should the address is carried out this logical operation, wherein, this multiplexer is more according to this first address, this conversion form and this abridgment of table judge whether to carry out a compensation operation, if do not carry out this compensation operation, then directly should decipher numerical value output, and, then this decoding numerical value is carried out an addition or subtraction if will carry out this compensation operation, should decipher numerical value output then.
Description of drawings
Fig. 1 is the configuration diagram of device that shows the saving memory source of the embodiment of the invention.
Fig. 2 is the flow chart of steps of method that shows the saving memory source of the embodiment of the invention, and it can be used for simplifying the address space of a form.
Fig. 3 is the flow chart of steps of method that shows the saving memory source of the embodiment of the invention, and it can be used for calculating an actual address.
The reference numeral explanation
The device of 100～saving memory source
110～address decoder
130～internal memory
150～multiplexer
Embodiment
For purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. 1 is described in detail to Fig. 3.Instructions of the present invention provides different embodiment that the technical characterictic of the different embodiments of the present invention is described.Wherein, the usefulness that is configured to explanation of each assembly among the embodiment is not in order to restriction the present invention.And the part of reference numerals repeats among the embodiment, is for the purpose of simplifying the description, is not the relevance that means between the different embodiment.
The embodiment of the invention has disclosed a kind of method and apparatus that can save memory source in image or Audio Processing process, content character at table look-up (LUT), utilize simple displacement, addition (or subtraction) computing and cooperate the use of multiplexer, table look-up (LUT) can be simplified to the internal memory use amount that the degree of depth and width are respectively 32 word groups and 15 positions.Note that the method and apparatus of the memory source saved of the embodiment of the invention is also applicable to Audio Processing, but hereinafter only do explanation that it is not in order to limit the present invention with Video processing.
In the VC-1 of Microsoft, no matter be that quantification, coefficient correction (Coefficient Scaling), DC coefficient and ac coefficient estimation (DC/AC Prediction) or dynamic vector estimation (MotionVector Prediction) all can be used a large amount of memory sources.Therefore, the method and apparatus of the saving memory source of the embodiment of the invention is at the characteristic of (LUT) content of tabling look-up, utilize simple displacement, compensation operation and cooperate the use of multiplexer, to reach the purpose of simplifying (LUT) content of tabling look-up, make that limited memory source can effectively use in the hardware design.
When carrying out DC coefficient and ac coefficient estimation compensation (DC/AC Prediction andCompensation), when if present handled image block adheres to different quantization parameters separately with the image block of desire estimation compensation, then need the image block of desire estimation is carried out coefficient correction, to reach identical accurate position (Level).With VC-1, its coefficient correction utilizes formula 1 (Eq.1) to realize, and is as follows:
C ~ p = ( C p × Q p Q c × 262144 + 0 x 20000 ) > > 18 . . . ( Eq . 1 ) ,
Wherein, C pBe the coefficient value in the image block of desire estimation compensation, Q pAnd Q cBe respectively the quantized value of desire estimation image block and the present image block of handling.Formula 1 simplification can be obtained formula 2 (Eq.2), as follows:
C ~ p = ( C pi × 262144 Q c + 0 x 20000 ) > > 18 . . . ( Eq . 2 ) ,
Wherein, C Pi=C p* Q pThe image block that is institute's desire estimation is finished re-quantization resulting value afterwards, and the Qc value then drops between 1～64.According to formula 2, consider real the doing of hardware and easily spend considerable area of hardware and time resource as if the computing of use divider, therefore can utilize (LUT) mode of tabling look-up to avoid the design of divider, so with a function DQScale[Qc] replace
Figure C200610063664D00082
And obtain formula 3 (Eq.3), as follows:
C ~ p = ( C pi × DQScale [ Qc ] + 0 x 20000 ) > > 18 . . . ( Eq . 3 ) ,
Wherein, DQScale[Qc] value promptly be to learn that by table look-up (LUT) it is by Q cValue obtains correspondence
Figure C200610063664D00084
The result.
DQScale[Qc] content shown in the form of annex 1.
Form by annex 1 can learn that the greatest measure in the form is 262144.Therefore, if will set up this form, needing the degree of depth is that 64 word groups, width are that the internal memory of 18 positions constitutes.If further to this tabular analysis, can find to exist 2 power power relation in the form between some numerical value, so can come the abridgment of table content by such relation.That is to say, can only store certain partial data in the form, and cooperate displacement, compensation operation to wait and derive its remainder values, be simplified to 32 data with 64 data that will originally must write down.
The simplification process of form is implemented with two rules, but it is not in order to limit the present invention.The first, as radix, so can reduce the required width of internal memory with less numerical value.The second, if less radix value in deriving the process of other numerical value, also can produce the action of subtraction compensation except shift operation, serve as preferential then to avoid subtracter.Therefore, the form of annex 1 can be rearranged according to above-mentioned two rules and obtain the form of annex 2.
In the form of annex 2, bold-faced part is the radix value of corresponding other correlation values, and each radix value can be deduced out 1 to 5 numerical value that does not wait.For instance, simultaneously with reference to the form of annex 1,2, in the address was 32 field, its decoding institute value was " 8192 ".And in the address was 1 field, its decoding institute value was " 8192 * 2 5=262144 ", it is expressed as " 8192＜＜5 ".Again, in the address was 11 field, its decoding institute value was " 23831 ".And in the address was 22 field, its decoding institute value was " 23831 ÷ 2+1=11916 " (a round numbers part), and it is expressed as " 23831〉〉 1+1 ".As mentioned above, form after the simplification only need spend the internal memory of 32 word groups, and for fear of the computing of subtracter, each radix value is not all is minimum value so need the internal memory width of 15～17 positions (whether use totalizer (or subtracter) and decide according to compensation operation).
Next the real flow process of doing of hardware design framework of the present invention and software is described.
Fig. 1 is the configuration diagram of device that shows the saving memory source of the embodiment of the invention.
Device 100 comprises an address decoder (Address Decoder) 110, one internal memory (for example, random access memory (Random Access Memory, RAM)) 130 and one multiplexer (Multiplexer) 150.The actual execution when tabling look-up, input still is six positions (0～63), and the internal memory after simplifying only needs the address of five positions.Therefore, address decoder 110 needs through conversion the address decoding of 64 of original inputs at most to be become earlier the address (rule of its correspondence is shown in the form of annex 3) of 32 radixes, form stores after will simplifying then is in internal memory 130, and its degree of depth and width are respectively 32 word groups, 15 positions.At last, according to internal memory 130 resulting outputs, utilize multiplexer 150 to select and determine to obtain correct output result after suitable displacement and addition (or subtraction) compensation.In addition, revise table look-up (LUT) later and still can in the clock pulse of one-period, obtain required output.
For instance, with reference to the form of annex 3, shown in the field that new address is 0, it comprises script address (Original) is 1,2,4,8,16 and 32 De Xie Code numerical value, and the radix value (Base) of all numeric reference is " 8192 ".Therefore, when from internal memory 130 resulting being output as " 16384 ", can learn that according to the form of annex 1 this numerical value is the decoding numerical value in the field of address 16, and then be referenced to the form of annex 2,3, Gai Xie Code numerical value can be learnt through behind the shift compensation, the field of the address 0 in the form of annex 3 should be stored in.Again, with reference to the form of annex 3, shown in the field that new address is 10, it comprises originally address (Original) is 21,42 decoding numerical value, and the radix value (Base) of all numeric reference is " 12483 ".Therefore, when from internal memory 130 resulting being output as " 6242 ", can learn that according to the form of annex 1 this numerical value is the decoding numerical value in the field of address 42, and then be referenced to the form of annex 2,3, Gai Xie Code numerical value can be learnt through displacement and addition (or subtraction) compensation back (round numbers part), the field of the address 10 in the form of annex 3 should be stored in.
Note, do in fact in hardware design, address decoder 110 can be incorporated into internal memory 130, and displacement also can utilize a shift unit (Shifter) and a totalizer (Adder) (or subtracter (Subtracter)) to implement respectively with addition (or subtraction) operation.In addition, can design exclusive address decoder in internal memory 130, use replacement address converter (being address decoder 110), it can be decoded into Input Address actual effective address.
Fig. 2 is the flow chart of steps of method that shows the saving memory source of the embodiment of the invention, and it can be used for simplifying the address space of a form.
At first, analyze the numerical value (step S21) in all address fields of a form, whether have a logical relation between numerical value to judge (for example, 2 power power relation) (step S22).If do not have a logical relation between numerical value, then process ends.If there is a logical relation between numerical value, then be a plurality of radix values and the simplification value (step S23) of corresponding each radix value with numerical classification in this form, store the memory headroom of above-mentioned numerical value with minimizing.For instance, originally needing the degree of depth is that 64 word groups, width are that the internal memory of 18 positions is stored above-mentioned numerical value, and after simplifying, only needing the degree of depth is that 32 word groups, width are that the internal memory of maximum 17 positions is stored above-mentioned numerical value.Then, with sorted radix value and corresponding simplification value, according to above-mentioned logical relation, the value storage that will have an identity logic relation is in a new and identical address field (step S24).
Fig. 3 is the flow chart of steps of method that shows the saving memory source of the embodiment of the invention, and it can be used for calculating an actual address.
At first, providing an address decoder, an internal memory and a multiplexer (step S31) in a device, wherein, is that a degree of depth is that 32 word groups, width are the internal memory of 15 positions in this internal memory, and it stores an abridgment of table (as the form of annex 3).Part numerical value in a part numerical value in this abridgment of table and the original form (as the form of annex 1) has a logical relation (for example, 2 power power relation).In addition, tool one conversion form in a medium, whether this abridgment of table of its mapping need carry out displacement or addition (or subtraction) compensating operation in order to represent the numerical value in a certain field in this abridgment of table.The address of maximum six inputs that this address decoder is obtained, and this Input Address deciphered is to obtain maximum five address (step S32) in should abridgment of table.
Then, this multiplexer judges whether to carry out a shifting function (step S33) according to former Input Address, this conversion form and this abridgment of table.If needn't carry out shifting function, then directly will be to numerical value output (step S34) that should the address.If will carry out shifting function, then utilize this multiplexer to numerical value that should the address is carried out a shifting function (step S35).Then, this multiplexer judges whether to carry out an addition (or subtraction) operation (step S36) according to former Input Address, this conversion form and this abridgment of table.If do not carry out addition (or subtraction) operation, the numerical value of then directly should decoding output (step S34).If will carry out addition (or subtraction) operation, then utilize this multiplexer to numerical value that should the address is carried out an addition (or subtraction) operation (step S37), then will be to numerical value output that should the address.
The method and apparatus of the saving memory source of the embodiment of the invention is to do explanation with the VC-1 coding techniques, but not as limit, any in real image and the audio compression techniques that needs to use multiplier or divider design of doing of hardware, all can utilize method and apparatus of the present invention to simplify and table look-up (LUT) content to save memory source.
The present invention more provides a kind of recording medium (for example discs, disk sheet and removable hard drive or the like), and it writes down the authority sign-off program of an embodied on computer readable, so that carry out the method for above-mentioned saving memory source.At this, be stored in the authority sign-off program on the recording medium, basically (for example the setting up organization chart code segment, sign-off forms code segment, setting program code snippet and deployment program code snippet) formed by most code segment, and the function of these code segment corresponds to the step of said method and the functional block diagram of said system.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking appended the claim person of defining.
Figure C200610063664D00121
Figure C200610063664D00131
Figure C200610063664D00141

Claims (7)

1. method of saving memory source, it is used for simplifying a form and is used for the address stored space, comprises the following steps:
Analyze the numerical value in all address fields of an original form, to judge whether there is a logical relation between numerical value;
If there is this logical relation between numerical value, then will the interior numerical classification of this original form be a plurality of radix values and the simplification value of corresponding each radix value, thereby produces a conversion form;
In the value storage that has the identity logic relation in these radix values in this conversion form and the corresponding simplification the value new and identical address field in an abridgment of table;
Obtain one first address of maximum X positions input;
This first address is deciphered, to obtain one second address of maximum Y positions, wherein, and X〉Y;
According to this first address, this conversion form and this abridgment of table, judge whether to carry out a logical operation;
If needn't carry out this logical operation, then directly will be to a decoding numerical value output that should second address;
If will carry out this logical operation, then to numerical value that should the address is carried out this logical operation;
According to this first address, this conversion form and this abridgment of table, judge whether to carry out a compensation operation;
If do not carry out this compensation operation, then directly should decipher numerical value output; And
If will carry out this compensation operation, then this decoding numerical value is carried out an addition or subtraction, should decipher numerical value output then.
2. the method for saving memory source as claimed in claim 1, wherein, above-mentioned logical relation refers to the power power relation of N.
3. the method for saving memory source as claimed in claim 1, it comprises that more with needing the degree of depth be that A word group, width are that this original table case transformation of B position is this abridgment of table that needs degree of depth C word group, the maximum D of width, to store these radix values and corresponding simplification value, wherein, A〉C and B〉D.
4. the method for saving memory source as claimed in claim 1, wherein, this logical operation is a shifting function.
5. device of saving memory source, it is used for simplifying a form and is used for the address stored space, comprising:
One first medium, the conversion form that it produces in order to the numerical value in all address fields of inventory analysis and classification one original form;
One second medium, it is simplified a plurality of radix values in this conversion form and an abridgment of table of generation with the simplification value of corresponding each radix value in order to storage;
One code translator is obtained one first address that maximum X positions are imported, and this first address is deciphered, to obtain one second address of maximum Y positions, wherein, and X〉Y; And
One multiplexer, be coupled to this from this first medium, this second medium and this code translator, according to this first address, this conversion form and this abridgment of table, judge whether to carry out a logical operation, if needn't carry out this logical operation, then directly will be to a decoding numerical value output that should second address, and if will carry out this logical operation, then to numerical value that should the address is carried out this logical operation, wherein, this multiplexer is more according to this first address, this conversion form and this abridgment of table judge whether to carry out a compensation operation, if do not carry out this compensation operation, then directly should decipher numerical value output, and, then this decoding numerical value is carried out an addition or subtraction if will carry out this compensation operation, should decipher numerical value output then.
6. the device of saving memory source as claimed in claim 5, wherein, this logical operation is a shifting function.
7. the device of saving memory source as claimed in claim 5, wherein, this code translator is arranged in this multiplexer, Input Address is decoded into actual effective address.
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Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
基于嵌入式系统的视频监控系统与H263图像编码实现研究. 吴杰，宋国文.现代电视技术，第5期. 2004
基于嵌入式系统的视频监控系统与H263图像编码实现研究. 吴杰，宋国文.现代电视技术，第5期. 2004 *

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