CN100541569C

CN100541569C - Drive circuit

Info

Publication number: CN100541569C
Application number: CN 200510097814
Authority: CN
Inventors: 前田荣作; 安藤仁; 金田甚作; 前岛明广; 松永弘树
Original assignee: Matsushita Electric Industrial Co Ltd
Current assignee: Craib Innovations Ltd
Priority date: 2004-08-30
Filing date: 2005-08-30
Publication date: 2009-09-16
Anticipated expiration: 2025-08-30
Also published as: CN1744175A

Abstract

The present invention provides a drive circuit capable of preventing the occurrence of a shoot-through current in a CMOS output section even when a power supply voltage VDD supplied from a low-voltage power supply is lower than a recommended operating power supply voltage. The driving circuit includes: a level shifting part (13) and a CMOS output part (14), wherein the level shifting part (13) has a P-type that the source is connected to a high-voltage power supply, the drain is connected to IN4, and the gate is connected to IN5 MOS transistor (2), P-type MOS transistor (3) whose source is connected to high-voltage power supply, drain is connected to IN5, and gate is connected to IN4, source is grounded, drain is connected to IN4, and gate receives low-voltage signal N Type MOS transistor (5), and the N-type MOS transistor (6) that the source is grounded and the drain is connected to IN5; the CMOS output part (14) has a P-type MOS transistor (1) and an N-type MOS transistor (4); P The driving current of the N-type MOS transistor (2) is larger than that of the N-type MOS transistor (5).

Description

Driving circuit

Technical field

The present invention relates to a kind of driving circuit that drives plasma display etc.

Background technology

Existing PDP driver shown in Figure 1 is made of level shift portion 25, CMOS efferent 26, low voltage control portion 21.

Level shift portion 25 has source electrode and all is connected, drains with high-voltage power supply terminal 22 and be connected with contact IN5, IN4 respectively and P type MOS transistor 17 and P type MOS transistor 16 that each other grid is reported to the leadship after accomplishing a task with drain electrode and is connected.And level shift portion 25 has grid and connects separately that the IN1 of low voltage control portion 21 or IN2, drain electrode are connected with contact IN5, IN4 respectively, the N type MOS transistor 20 and the N type MOS transistor 19 of the equal army of source electrode ground connection.

CMOS efferent 26 has grid and the IN3 of low voltage control portion 21 and is connected, drains and connect the N type MOS transistor 18 of lead-out terminal 24, source ground; Be connected with high-voltage power supply terminal 22 with source electrode, grid is connected with contact IN4, drain electrode is connected with the P type MOS transistor 15 of lead-out terminal 24.

Low voltage control portion 21 is connected with low-tension supply terminal 27.The such capacitor type load of output load 34 expression plasma displays.

Fig. 2 is the figure of the signal waveform in the input/output signal of the low voltage control portion 21 in the existing PDP driver of expression and contact IN4, IN5, the lead-out terminal 24.

The work of existing PDP driver then, is described.Suppose to switch to the situation of Low (this situation GND level) from Hi (this situation VDD level) to the signal IN of low voltage control portion 21 inputs.In the case, because of signal from the IN1 of low

voltage control portion

21,16 conductings of N type MOS transistor, because the current potential of contact IN5 drops to earthing potential (GND), so 16 conductings of P type MOS transistor.Meanwhile, because of the IN2 signal from low voltage control portion 21, N type MOS transistor 19 is ended, thus because the current potential of contact IN4 rises to the current potential (VDDH) of high-voltage power supply, so P type MOS transistor 15 is ended.Have again, because of IN3 signal from low

voltage control portion

21,18 conductings of N type MOS transistor, the current potential of lead-out terminal 24 becomes earthing potential (GND), transmission IN signal.

Conversely, when IN when Low switches to Hi, because of signal from the IN2 of low

voltage control portion

21,19 conductings of N type MOS transistor, meanwhile, because of the IN1 signal from low voltage control portion 21, N type MOS transistor 20 is ended.At this moment, the current potential of contact IN4 is reduced to earthing potential (GND), so 15 conductings of P type MOS transistor.Therefore, the current potential of lead-out terminal 24 rises to the current potential of high-voltage power supply (VDDH).Because of the signal of IN3, N type MOS transistor 18 is ended, the signal transmission of IN.

At this moment, decide each transistorized current driving ability of level shift portion 25 as described below.

Drain electrode is connected P type MOS transistor 16 and N type MOS transistor 19 on the CMOS efferent 26, drives CMOS efferent 26, so compare with the P type MOS transistor 17 and the N type MOS transistor 20 in level shift portion 25 left sides, the load of driving will be big., compare for this reason, just need to improve the current driving ability (with reference to special fair 6-91442 communique) of P type MOS transistor 16 and N type MOS transistor 19 with P type MOS transistor 17 and N type MOS transistor 20.

In addition, at the current potential of the IN4 of level shift portion 25 and IN5 when Hi (this situation VDDH level) switches to Low (this situation GND level), or on the contrary, when Low switches to Hi, flowing through punchthrough current between P type MOS transistor 17 and the N type MOS transistor 20 and between P type MOS transistor 16 and the N type MOS transistor 19 to transition.In order to reduce this punchthrough current, must be promptly the current potential of IN4, IN5 be switched to stationary value., compare for this reason, just need to increase the current driving ability (spy opens the 2000-164730 communique) of N

type MOS transistor

20,19 with the current driving ability of P

type MOS transistor

17,16.

So, for existing PDP driver, be applied to the supply voltage VDD of low-tension supply terminal 27 if in recommended work supply voltage scope from low-tension supply, even in the scope of the supply voltage that guarantees the circuit operate as normal, then in level shift portion 25, CMOS efferent 26, just punchthrough current can be do not flow through basically, desirable work can be obtained.

But, during conducting/deenergization, there is such situation sometimes, that is, the rise and fall of low-tension supply are not carried out hastily, have that to be applied to the supply voltage VDD of low-tension supply terminal 27 from low-tension supply lower than ratings, maintain near the intermediate potential VLo.For example, the ratings of supply voltage VDD is under the situation of 5V, during deenergization, the transitional period in that the supply voltage VDD that is applied to low-tension supply terminal 27 from low-tension supply is interdicted, maintains sometimes near the intermediate potential VLo=2V.As above, become lower than recommended work supply voltage at the supply voltage VDD that is applied to low-tension supply terminal 27 from low-tension supply, IN1, IN2, IN3, Hi level when descending, the working condition of circuit is different from above-mentioned situation.

As shown in Figure 3, when input voltage IN switches to Low (this situation GND level) from Hi (this situation VLo level), because the input voltage IN1 of level shift portion 25 becomes Hi, thereby 20 conductings of N type MOS transistor, 16 conductings of P type MOS transistor.With respect to this, because the input voltage IN2 of level shift portion 25 becomes Low, thereby N type MOS transistor 19 ends, and P type MOS transistor 17 is ended., when supply voltage VDD descends, but can not guarantee the input voltage IN1 enough bigger than the threshold voltage (VT) of N type MOS transistor 20.For this reason, the current potential of contact IN5 can moment not break away from Low, the current potential that has a contact IN5 stop at intermediate potential 1 (this situation VDDL level) during t0.

On the other hand, the current driving ability of P type MOS transistor 16 is littler than the current driving ability of N type MOS transistor 19.In addition, because the current potential of contact IN5 is not Low, and becomes the current potential of intermediate potential 1 (VDDL level) that so P type MOS transistor 16 becomes incomplete conducting state, the drive current of P type MOS transistor 16 descends during tO.For this reason, not exclusively the P type MOS transistor 16 of conducting state can not be supplied with the enough big electric current of introducing than the N type MOS transistor 19 of incomplete cut-off state of electric current, and P type MOS transistor 16 can not the moment conducting.Its result, the current potential of contact IN4 just can not rise to Hi (this situation VDDH level) from Low (this situation GND level) immediately, exist stop at intermediate potential 2 (this situation VDDM level) during t0.

For t0 during this, the P type MOS transistor 15 of CMOS efferent 26 is ended because of the current potential of contact IN4 breaks away from fully, and in addition, the N type MOS transistor 18 of CMOS efferent 26 becomes conducting state according to the output signal from IN3.As a result, because the P type MOS transistor 15 and the 18 both sides' conductings of N type MOS transistor of CMOS efferent 26 so the current potential of lead-out terminal 24 does not become earthing potential completely, but become intermediate potential (this situation VoutM level).Thus, a large amount of punchthrough current from high-voltage power supply (VDDH) effluent of CMOS efferent 26 to earthing potential (GND) side.This punchthrough current just becomes the reason of the image disorder of the destruction that causes the PDP driver and plasma display.

Problem when especially, this situation is closed the power supply that supplies to the PDP driver with regard to becoming.As shown in Figure 4, behind the powered-down, cause becoming big with the load that high-voltage power supply VDDH is connected with low-tension supply VDD respectively, with respect to the voltage of low-tension supply VDD under little time constant (promptly, hurry up) descend, the voltage of high-voltage power supply VDDH (that is, slow) under big time constant descends.For this reason, because under the high-tension state that CMOS efferent 26 is applied from high-voltage power supply VDDH, the gate voltage of N type MOS transistor 20 descends in advance, 15 ones of P type MOS transistor are ended fully, flow through punchthrough current in CMOS efferent 26.

Summary of the invention

Therefore, the present invention has considered above-mentioned problem, and its purpose is, though provide a kind of supply voltage of supplying with from low-tension supply lower than recommended work supply voltage, also can prevent the driving circuit that the punchthrough current of CMOS efferent takes place.

In order to solve above-mentioned problem, realize above-mentioned purpose, driving plasma display panel driving circuit of the present invention comprises: level shift portion, this level shift portion has: source electrode is connected with high-voltage power supply, drain electrode is connected with first contact, the P type MOS transistor that grid is connected with second contact, source electrode is connected with above-mentioned high-voltage power supply, drain electrode is connected with above-mentioned second contact, the 2nd P type MOS transistor that grid is connected with above-mentioned first contact, source ground, drain electrode is connected with above-mentioned first contact, grid receives a N type MOS transistor of first signal, and source ground, drain electrode is connected with above-mentioned second contact, grid receives the 2nd N type MOS transistor of secondary signal; The low-voltage control part, this low-voltage control part not only is connected with low-tension supply, also be connected with the grid of an above-mentioned N type MOS transistor, the grid of above-mentioned the 2nd N type MOS transistor, according to input signal, above-mentioned first signal is outputed to the grid of an above-mentioned N type MOS transistor, above-mentioned secondary signal is outputed to the grid of above-mentioned the 2nd N type MOS transistor; And recommend efferent, the 3rd signal according to the signal of above-mentioned first contact of above-mentioned level shift portion and the output of above-mentioned low voltage control portion carries out switch work, above-mentioned low-tension supply from the voltage more than first voltage under the situation of second change in voltage lower than above-mentioned first voltage, the drive current of an above-mentioned P type MOS transistor is bigger than the drive current of an above-mentioned N type MOS transistor.

As above, because the drive current of an above-mentioned P type MOS transistor is bigger than the drive current of an above-mentioned N type MOS transistor, so even supply voltage VDD is lower than recommended work supply voltage, driving circuit of the present invention also can prevent to produce in the punchthrough current of CMOS efferent.

Drain current when the drive current of MOS transistor is the MOS transistor conducting is arranged again.Concrete grammar as this driving current value of decision, comprise MOS transistor is designed so that current driving ability (mutual conductance) that MOS transistor itself had becomes the method for appropriate value the method that is connected as the load of MOS transistor with the resistor-type element of the drain current that will limit MOS transistor etc.

In addition, in this said output (プ Star シユプ Le is exerted oneself) portion that recommends, be that two transistor series are connected transistor output circuit between power supply and the earth point, comprise totem-pote circuit and cmos circuit etc.

As above, even the present invention can provide a kind of supply voltage lower than recommended work supply voltage, also can prevent the driving circuit of generation of the punchthrough current of CMOS efferent.

Especially, driving circuit of the present invention is being applicable under the situation of PDP driver, owing to do not have punchthrough current to flow to the CMOS efferent, so can prevent the destruction of PDP driving circuit and the disorder of Plasma Display image.Thus, can improve the reliability of PDP driver and Plasma Display.

Description of drawings

From the description below in conjunction with accompanying drawing, these and other objects of the present invention, advantage and feature will become obviously, wherein description of drawings specific embodiments of the invention.Wherein:

The structural drawing of the existing PDP driver of Fig. 1.

Fig. 2 represents the figure of the input/output signal of existing PDP driver.

The figure of the input/output signal when Fig. 3 represents to be applied to the supply voltage decline that has the PDP driver now.

Fig. 4 represents to have closed the variation diagram of the output voltage of high-voltage power supply under the situation of the power supply that the PDP driver is supplied with and low-tension supply.

The structural drawing of the PDP driver of Fig. 5 embodiment 1.

Fig. 6 represents the planimetric map of the structure of MOS transistor.

Input/output signal figure when the supply voltage that Fig. 7 represents to be applied to the PDP driver of embodiment 1 descends.

The structural drawing of the PDP driver of Fig. 8 embodiment 2.

Fig. 9 represents the structural drawing of voltage detection circuit.

Figure 10 represents the sequential chart of the work of voltage detection circuit.

Figure 11 represents the figure of the structure of low voltage control portion.

Figure 12 is the structural drawing of the PDP driver of embodiment 3.

Figure 13 is the structural drawing of the PDP driver in the variation of embodiment 3.

Figure 14 is the structural drawing of the PDP driver of embodiment 4.

Figure 15 is the structural drawing of the PDP driver in the variation of embodiment 4.

Embodiment

Below, be used to implement best mode of the present invention with reference to accompanying drawing explanation.

(embodiment 1)

At first, use Fig. 5 that the structure of the PDP driver of embodiment 1 is described.

Fig. 5 is the structural drawing of the PDP driver of embodiment 1.The PDP driver of embodiment 1 is made of level shift portion 13, CMOS efferent 14, low voltage control portion 7 as an example of driving circuit of the present invention.

Level shift portion 13 has source electrode and all is connected, drains with high-voltage power supply terminal 9 and be connected with contact IN5, IN4 respectively and P type MOS transistor 3 and P type MOS transistor 2 that each other grid is reported to the leadship after accomplishing a task with drain electrode and is connected.And, level shift portion 13 have grid respectively be connected, drain by IN1 or IN2 from the low voltage control portion 7 of the driven of low-tension supply terminal 10 be connected with contact IN5, IN4 respectively, N type MOS transistor 6 and N type MOS transistor 5 that source electrode all is connected to earthing potential terminal 11.

CMOS efferent 14 is examples of recommending efferent that carry out switch work as the signal IN3 according to the signal of the contact IN4 of

level shift portion

13 and 7 outputs of low voltage control portion, has grid and the IN3 of low voltage control portion 7 is connected, drain electrode is connected with lead-out terminal 12, source electrode is connected with ground terminal 11 N type MOS transistor 4; With the P type MOS transistor 1 that source electrode is connected with high-voltage power supply terminal 9, grid is connected with contact IN4, drain electrode is connected with lead-out terminal 12.

Low voltage control portion 7 is connected with low-tension supply terminal 10.Output load 34 is the capacitor type loads as plasma display.

At this, by the P type MOS transistor 2 in the setting level shift as follows portion 13, P type MOS transistor 3, N type MOS transistor 5, and the current driving ability of N type MOS transistor 6.That is, the order of each transistorized current driving ability of level shift portion 13 being set for by P type MOS transistor 3, N type MOS transistor 6, N type MOS transistor 5, P type MOS transistor 2 becomes big.Transistorized current driving ability is that the length of grid wide 54 decides by length between the opposite face of source region 52 shown in the plane structure chart of the MOS transistor of Fig. 6 and drain region 53.For example, according to the width of each the transistorized grid in the order increase level shift portion 13 of P type MOS transistor 3, N type MOS transistor 6, N type MOS transistor 5, P type MOS transistor 2, set above-mentioned current driving ability.Have, current driving ability is transistorized mutual conductance gm=ID/VGS again, refers to represent the characteristic at the size of the drain current ID of the input voltage VGS between grid and source electrode.Have, current driving ability also can change by changing grid shown in Figure 6 long 55 again.

Then, use Fig. 7 that the work of the PDP driver of embodiment 1 is described.

Because the work of the PDP driver when the supply voltage VDD of low-tension supply is in recommended work supply voltage scope is identical with the work of existing PDP driver, so omit this explanation.Below, being described as follows the work of the PDP driver under the situation, described situation is: because conducting is not carried out the rise and fall of supply voltage hastily when power supply, supply voltage VDD becomes the situation of the Vlo lower than recommended work supply voltage.

Fig. 7 is illustrated in the PDP driver of embodiment 1, the input/output signal of the low voltage control portion 7 when supply voltage VDD becomes than the low VLo of recommended work supply voltage, and the oscillogram of the signal of contact IN4, IN5, lead-out terminal 12.

When input voltage IN switched to Low (this situation GND level) from Hi (this situation VLo level), owing to be switched to Hi from the IN1 signal of low voltage control portion 7 outputs, so 6 conductings of N type MOS transistor, P type MOS transistor 3 was ended.In addition, owing to be switched to Low from the IN2 signal of low voltage control portion 7 outputs, so N type MOS transistor 5 is ended 2 conductings of P type MOS transistor.At this moment, though the current driving ability of N type MOS transistor 6 is bigger than the current driving ability of P type MOS transistor 3, because the decline of the input voltage of IN1, so can not fully guarantee the threshold voltage (VT) of N type MOS transistor 6.Therefore, on the contrary, if same with prior art, the current driving ability of P type MOS transistor 2 is littler than the current driving ability of N type MOS transistor 5, then the current potential moment disengaging Low of contact IN5 keeps intermediate potential 1 (this situation VDDL level) as shown in Figure 3.

But in embodiment 1, the current driving ability of P type MOS transistor 2 is bigger than the current driving ability of N type MOS transistor 5.Thus, contact IN5 keeps the current potential of intermediate potential 1, even P type MOS transistor 2 is the state of incomplete conducting, P type MOS transistor 2 also can provide the enough big electric current of introducing than the N type MOS transistor 5 of incomplete cut-off state of electric current, makes the P type MOS transistor 2 can the moment conducting.Its result, the current potential of contact IN4 reaches Hi (being the VDDH level in the case) immediately, and P type MOS transistor 3 is ended, and the current potential of contact IN5 changes to Low (being the GND level in the case) immediately.Therefore, t0 during not existing in that as shown in Figure 3 intermediate potential stops for 1,2 times.

Therefore, at IN when Hi switches to Low since current potential moment of contact IN4 become Hi (VDDH), so the P type MOS transistor 1 of CMOS efferent 14 was ended fully with regard to moment.In addition, since the N type MOS transistor 4 of CMOS efferent 14 because of the output signal from IN3 becomes conducting state, so the current potential of lead-out terminal 12 becomes earthing potential (GND) completely.Thus, mobile punchthrough current in CMOS efferent 14.

Therefore, just can prevent the disorder of the image of the destruction of PDP driver and plasma display (output load 34), can realize the raising of the reliability of PDP driver and plasma display.

As mentioned above, each the transistorized current driving ability with level shift portion 13 is set at by the order change of P type MOS transistor 3, N type MOS transistor 6, N type MOS transistor 5, P type MOS transistor 2 big.Thus, even supply voltage VDD becomes the voltage VLo lower than recommended work supply voltage, when input voltage IN when Hi switches to Low, each transistor in each level shift portion 13 and the CMOS efferent 14 also can switch to cut-off state from conducting state moment, or switches to conducting state from cut-off state.That is, in CMOS efferent 14, P type MOS transistor 1 and N type MOS transistor 4 can not become conducting state simultaneously.Its result does not have punchthrough current to flow in CMOS efferent 14, can prevent the destruction of PDP driving circuit and the disorder of plasma display (output load 34) image.

Have again, in above-mentioned embodiment 1, illustrated that IN switches to the situation of Low from Hi.Even IN switches under the situation of Hi from Low, also identical with above-mentioned situation, because by above-mentioned such each transistorized current driving ability of setting in the level shift portion 13, even so become VLo from the voltage of low-tension supply, each transistor also can switch to cut-off state from conducting state moment, or switches to conducting state from cut-off state.Therefore, in CMOS efferent 14, do not have punchthrough current to flow, can prevent the destruction of PDP driving circuit and the disorder of plasma display (output load 34) image.

(embodiment 2)

Then, use Fig. 8 that the structure of the PDP driver of embodiment 2 is described.

Fig. 8 is the structural drawing of the PDP driver of embodiment 2.The PDP driver of embodiment 2 comprises voltage detection circuit 8, and other structure is identical with the PDP driver of embodiment 1.

Voltage detection circuit 8 is connected with low voltage control portion 7 with low-tension supply terminal 10.Fig. 9 illustrates the detailed structure of voltage detection circuit 8, and voltage detection circuit 8 utilizes hysteretic converter 30 relatively to carry out the voltage of dividing potential drop and the voltage of reference voltage source 33 by

resistance

31 and 32 pairs of voltages from low-tension supply terminal 10 of resistance.Voltage detection circuit 8 outputs to lead-out terminal 29 according to the comparative result that obtains with hysteretic converter 30 with control signal.

Figure 10 is the figure that shows the work of voltage detection circuit 8 with slip chart.Voltage detection circuit 8, reach from earthing potential at the supply voltage VDD of low-tension supply terminal 10 regulation voltage (VTON current potential) during output Low level; When surpassing the VTON current potential when further rising of supply voltage VDD, be outputted to the control signal of Hi level, supply voltage VDD reaches ratings.After this, supply voltage VDD begins to descend from ratings, even it descends lowlyer than VTON current potential, also continues output Hi level, and when dropping to than the low VTOFF current potential of VTON current potential, output switches to the control signal of Low level.

Figure 11 is the structural drawing of low voltage control portion 7.In low voltage control portion 7, when the control signal that is input to signal deteching circuit 41 from voltage detection circuit 8 became the Hi level, switch (SW) 44 was selected change-over circuits 43.Change-over circuit 43 is identical with embodiment 1, conversion input signal IN.Be output to each grid of N type MOS transistor 6, N type MOS transistor 5, N type MOS transistor 4 by signal IN1, IN2, the IN3 of change-over circuit 43 conversions.Thus, carry out the work identical with embodiment 1.

On the other hand, from the voltage decline of low-tension supply, when the control signal that is input to signal deteching circuit 41 from voltage detection circuit 8 became the Low level, switch (SW) 44 was selected fixed signal output circuits 42.Fixed signal output circuit 42 and input signal IN irrespectively export signal IN2, Low (GND level) the signal IN3 of signal IN1, the Low (GND level) of Hi (for example VDD level).

When signal IN1 became the Hi level, 6 conductings of N type MOS transistor were because the current potential of contact IN5 becomes earthing potential (GND), so 2 conductings of P type MOS transistor.Thus, the current potential of contact IN4 is thus lifted to the current potential of high-voltage power supply (VDDH), and P type MOS transistor 1 is ended.In addition, by the Low level of signal IN3, N type MOS transistor 4 is ended, and by the Low level of IN2, N type MOS transistor 5 is also ended.Thus, because P type MOS transistor 1 and N type MOS transistor 4 are ended, do not produce punchthrough current at CMOS efferent 14.

Owing to the deviation on making, there is the situation of threshold voltage (VT) skew of MOS transistor.In the case, when the voltage from low-tension supply terminal 10 significantly descends, do not guarantee the current driving ability big such condition of the current driving ability of P type MOS transistor 2 than N type MOS transistor 5, P type MOS transistor 2 can not be supplied with the enough big electric current of introducing than N type MOS transistor 5 of electric current.

But, when significantly descending from the voltage of low-tension supply terminal 10, the control signal of voltage detection circuit 8 output Low level, the 7 output Hi signal IN1 of low voltage control portion, Low signal IN2, Low signal IN3.Thus, as mentioned above, P type MOS transistor 1 and N type MOS transistor 4 are ended.Its result as mentioned above, even can not supply with in P type MOS transistor 2 under the situation of the electric current enough bigger than the electric current of N type MOS transistor 5 introducings, also can prevent the generation of the punchthrough current of CMOS efferent 14.

Have again, in embodiment 2, be illustrated in and voltage detection circuit 8 be set and in the PDP driver of embodiment 1 when the control signal of voltage detection circuit 8 output Hi level, signal IN1, the Low signal IN2 of the 7 output Hi of low voltage control portion, the PDP driver of Low signal IN3.But voltage detection circuit 8 not only is arranged on the PDP driver of embodiment 1, also can be arranged on existing PDP driver.In the case, low voltage control portion 21 is designed in advance: from the control signal of voltage detection circuit 8 input Hi level the time, signal IN1, Low signal IN2, the Low signal IN3 of output Hi.Thus, when even supply voltage VDD is lower than recommended work supply voltage, also irrelevant with the size of the current driving ability of each transistor, N type MOS transistor 19, N type MOS transistor 20, P type MOS transistor 16 and the P type MOS transistor 17 of level shift portion 25, work by voltage detection circuit 8 and low voltage control portion 21 can prevent the generation of the punchthrough current of CMOS efferent 26.Its result can design the current driving ability of each the P type N type MOS transistor in the

level shift portion

13,25 easily.

(embodiment 3)

Then, use Figure 12 that the structure of the PDP driver of embodiment 3 is described.

Figure 12 is the structural drawing of the PDP driver of embodiment 3.The PDP driver of embodiment 3 except level shift portion 113, comprises the structure identical with the PDP driver of embodiment 1.

Level shift portion 113 is equivalent to the P type MOS transistor 3 in the level shift portion 13 of embodiment 1 is replaced with the level shift circuit of the series circuit of P type MOS transistor 103 and N type MOS transistor 103a.

For example, P type MOS transistor 103 is the P type MOS transistor that have with the current driving ability of opposite side N type MOS transistor 6 same degree of its formation complementary pair.

As an example of resistor-type element, the source electrode of P type MOS transistor 103a connects high-voltage power supply VDDH, and its drain electrode is connected with the source electrode of P type MOS transistor 103, and its grid is connected with the grid of P type MOS transistor 103.And, P

type MOS transistor

103 and 103a, when their grid was imported the Low level signal, the both became conducting state, and the conducting resistance composition between leakage-source electrode of P type MOS transistor 103a has the function of the pull-up resistor of P type MOS transistor 103.

Make up the circuit of these P type MOS transistor 103 and P type MOS transistor 103a, play the effect identical with the P type MOS transistor 3 of embodiment 1.Promptly, in the present embodiment, though the current driving ability of P type MOS transistor 103 itself is identical degree with N type MOS transistor 6 with the opposite side of its formation complementary pair, but, thereby limited the drive current (drain current during conducting) of P type MOS transistor 103 owing to the pull-up resistor as this P type MOS transistor 103 has connected P type MOS transistor 103a.Its result makes the drive current that flows through P type MOS transistor 103a and P type MOS transistor 103 become littler than the drive current of N type MOS transistor 6.

According to the above-mentioned fact, the PDP driver in the present embodiment has the effect identical with embodiment 1.Promptly, because the drive current of N type MOS transistor 6 is bigger than the drive current of P type MOS transistor 3, even so under the situation that the voltage of low-tension supply descends after as power-off, when signal IN1 is Hi, also can reliably keep the conducting state of N type MOS transistor 6, and, because the drive current of P type MOS transistor 2 is bigger than the drive current of N type MOS transistor 5, so can reliably keep the conducting state of P type MOS transistor 2, its result, grid to the P type MOS transistor 1 of CM0S efferent 14 applies high voltage VDDH, reliably keeps the cut-off state of P type MOS transistor 1, has avoided flowing through punchthrough current at CMOS efferent 14.

Have, in the present embodiment, though the grid of P type MOS transistor 103a is connected to the grid of P type MOS transistor 103, the present invention is not limited to this connection again.Because P type MOS transistor 103a also can have the function of pull-up resistor, so for example the grid of P type MOS transistor 103a also can be connected the Low current potential (for example, GND etc.) of regulation.

In addition, the 113a of level shift portion as shown in figure 13 is such, and also available resistance 110 with same resistance value is replaced the P type MOS transistor 103a in the present embodiment.This is because can limit the drain current of P type MOS transistor 103.

(embodiment 4)

Then, use Figure 14 that the structure of the PDP driver of embodiment 4 is described.

Figure 14 is the structural drawing of the PDP driver of embodiment 4.The PDP driver of embodiment 4 comprises the structure identical with the PDP driver of embodiment 3 except level shift portion 114.

Level shift portion 114 is equivalent to the N type MOS transistor 6 in the level shift portion 113 of embodiment 3 is replaced with the circuit of N type MOS transistor 106 and N type MOS transistor 106a.

For example, N type MOS transistor 106 is the N type MOS transistor that have with the current driving ability of N type MOS transistor 5 same degree that are positioned at thereafter level.

As an example of resistor-type element, the source electrode of N type MOS transistor 106a is connected with low-tension supply VDD, and its drain electrode is connected with the source electrode of N type MOS transistor 106, and its grid is connected with the grid of N type MOS transistor 106.And, N

type MOS transistor

106 and 106a, when their grid was imported the Hi level signal, the both became conducting state, and the conducting resistance composition between leakage-source of N type MOS transistor 106a has the function of the pull-up resistor of N type MOS transistor 106.

Make up the circuit of these N type MOS transistor 106 and N type MOS transistor 106a, play the effect identical with the N type MOS transistor 6 of embodiment 3.Promptly, in the present embodiment, though the current driving ability of N type MOS transistor 106 itself and with being positioned at thereafter the N type MOS transistor 5 of level is a same degree, but, thereby limited the drive current (drain current during conducting) of N type MOS transistor 106 owing to the pull-up resistor as this N type MOS transistor 106 connects N type MOS transistor 106a.Its result makes the drive current that flows through N type MOS transistor 106 and N type MOS transistor 106a become littler than the drive current of N type MOS transistor 5.

Have, P type MOS transistor 103a and N type MOS transistor 106a are designed to again: so that the relation of the P type MOS transistor 103 and the drive current of N type MOS transistor 106 becomes identical with embodiment 3.That is, the drive current of N type MOS transistor 106 is bigger than the drive current of P type MOS transistor 103.

As above, the PDP driver in the present embodiment has the effect identical with embodiment 1.Promptly, because the drive current of N type MOS transistor 106 is bigger than the drive current of P type MOS transistor 103, even so under the situation that the voltage of this low-tension supply descends behind the power-off, when signal IN1 is Hi, also can reliably keep the conducting state of N type MOS transistor 106, and, because the drive current of P type MOS transistor 2 is bigger than the drive current of N type MOS transistor 5, so can reliably keep the conducting state of P type MOS transistor 2, its result, grid to the P type MOS transistor 1 of CMOS efferent 14 applies high voltage VDDH, can reliably keep the cut-off state of P type MOS transistor 1, has avoided flowing through punchthrough current at CMOS efferent 14.

Have, in the present embodiment, though the grid honesty of the grid of N type MOS transistor 106a and N type MOS transistor 106, the present invention is not limited to such connected mode again.Because N type MOS transistor 106a also can have the function of pull-up resistor, so for example, the grid of N type MOS transistor 106a gets final product as long as connect with the Hi current potential (for example, VDD etc.) of regulation.

In addition, the 114a of level shift portion as shown in figure 15 is such, and also available resistance 111 with same resistance value is replaced the N type MOS transistor 106a in the present embodiment.This is because can limit the drain current of N type MOS transistor 106.

More than, though according to embodiment 1～4 driving circuit of the present invention has been described, the present invention is not limited to these embodiments.In not breaking away from aim scope of the present invention, the mode that the inscape of each embodiment of structure of various distortion of enforcement and appropriate combination realizes under each embodiment of those of ordinary skills is also contained in the present invention.

For example, in embodiment 3, the P type MOS transistor 3 of embodiment 1 is replaced with P type MOS transistor 103 and P type MOS transistor 103a, in embodiment 4, in addition, N type MOS transistor 6 can also be replaced with N type MOS transistor 106 and N type MOS transistor 106a, but such replacement is not limited to these transistors.Even, also can carry out same replacement to P type MOS transistor 2, N type MOS transistor 5.And four MOS transistor for constituting level shift portion also can replace with the combination of MOS transistor and resistance.

Promptly, as long as the drain current when being designed to conducting increases by P type MOS transistor 3, N type MOS transistor 6, N type MOS transistor 5, P type MOS transistor 2 orders, then each MOS transistor also can realize separately, and each MOS transistor also can realize by the combination of MOS transistor and resistor-type element (MOS transistor or resistance).

In addition, in above-mentioned embodiment 1～4, though be illustrated by the example of recommending efferent (CMOS efferent) 14 that uses between high-voltage power supply (VDDH) and earthing potential (GND), be connected in series P type MOS transistor 1 and N type MOS transistor 4 formations, but the present invention is not limited to these examples, also can use and (for example be connected in series two transistors of the same race, N type MOS transistor class, P type MOS transistor class, the bipolar transistor tubing, or IGBT (Insulatde Gate BipolarTransistor) class) recommend efferent, make one of the transistor of high-voltage power supply (VDDH) side or transistorized control signal of earthing potential (GND) side be set to opposite polarity and implement.

Industrial applicibility

Drive circuit of the present invention is conducive to drive as output HIGH voltage the drive circuit of signal, particularly As the PDP driver that drives plasma display etc.

Claims

1. A driving circuit for driving a plasma display panel, comprising:

A level shifter, the level shifter has: a first P-type MOS transistor whose source is connected to the high-voltage power supply, the drain is connected to the first contact, and the gate is connected to the second contact, the source is connected to the above-mentioned high-voltage power supply, A second P-type MOS transistor whose drain is connected to the second contact and whose gate is connected to the first contact; a first N-type MOS transistor whose source is grounded, whose drain is connected to the first contact, and whose gate receives the first signal a transistor, and a second N-type MOS transistor whose source is grounded, whose drain is connected to the second contact, and whose gate receives a second signal;

A low-voltage control unit, which is not only connected to a low-voltage power supply, but also connected to the gate of the first N-type MOS transistor and the gate of the second N-type MOS transistor, and converts the first signal to output to the gate of the first N-type MOS transistor, and output the second signal to the gate of the second N-type MOS transistor; and

The push-pull output unit performs switching operation according to the signal of the first contact of the level shift unit and the third signal output by the low-voltage control unit,

A driving current of the first P-type MOS transistor is larger than a driving current of the first N-type MOS transistor.

2. The driving circuit for driving a plasma display panel according to claim 1, wherein the driving current of the first N-type MOS transistor is larger than the driving current of the second N-type MOS transistor;

A driving current of the second N-type MOS transistor is larger than a driving current of the second P-type MOS transistor.

3. The driving circuit for driving a plasma display panel according to claim 1, wherein the current driving capability of the first P-type MOS transistor is larger than that of the first N-type MOS transistor.

4. The driving circuit for driving a plasma display panel according to claim 3, wherein the current driving capability of the first N-type MOS transistor is larger than that of the second N-type MOS transistor;

The current drive capability of the second N-type MOS transistor is greater than that of the second P-type MOS transistor.

5. The driving circuit for driving a plasma display panel according to claim 1, said driving circuit further comprising a first resistive element connected between said high-voltage power supply and said source of said second P-type MOS transistor;

The source of the second P-type MOS transistor is connected to the high voltage power supply through the first resistive element.

6. The driving circuit for driving a plasma display panel according to claim 5, wherein said first resistive element is a P-type MOS transistor.

7. The driving circuit for driving a plasma display panel according to claim 5, said driving circuit further comprising a second resistive element connected between the source of said second N-type MOS transistor and a ground potential;

The source of the second N-type MOS transistor is grounded through the second resistive element.

8. The driving circuit for driving a plasma display panel according to claim 7, wherein said second resistive element is an N-type MOS transistor.

9. The drive circuit for driving a plasma display panel according to claim 1, further comprising a power supply voltage detection circuit, which detects the voltage applied by the low-voltage power supply, and when the detected voltage is from the first voltage or higher to outputting a control signal to the low-voltage control unit when the voltage changes to a second voltage lower than the first voltage;

When the control signal is input, the low-voltage control unit outputs the second signal for turning off the second N-type MOS transistor.