CN100536106C - Method for producing conductor - Google Patents

Abstract

The method includes following steps: first, providing substrate, where at least two isolation structures are already formed on, and a first conductor layer is formed between two adjacent isolation structures; next, forming a dielectric layer on the substrate, and patternizing the dielectric layer in order to form a opening to expose the first conductor layer; then, forming a second conductor layer on the substrate, removing the partial second conductor layer except the opening portion in order to form a conducting wire connected to the first conductor layer electrically. When size of component becomes smaller, the invention fabricates connecting wire with high precision in size and position without limited by design of photo etching technology so as to form connecting wire to connect semiconductor components effectively.

Description

The manufacture method of lead

Technical field

The present invention relates to a kind of semiconductor element and semiconductor technology, particularly relate to a kind of structure and manufacture method thereof of lead.

Background technology

In integrated circuit flourish today, element downsizing and the productive setization trend that is inevitable also is the important topic of all circles' develop actively.When component size is dwindled gradually, the size and the live width of Connection Element lead are also more and more littler, thereby can increase the degree of difficulty of technology.

To make memory on silicon wafer is example, after the memory cell that completes on the silicon wafer, must make lead (word line) again to connect each memory cell, so that its normal operation.

Figure 1A be a flash memory array on look schematic diagram.The isolation structure 110 of this flash memory array is the strip layout, and isolation structure 110 is in order to define active area 120.Lead 150a (word line) is made on the active area 120.About the practice of lead 150a, prior art is made for utilizing the photoengraving lithography.

The profile of Figure 1B for being drawn along hatching P-P ' among Figure 1A.Please refer to Figure 1B, in substrate 100, formed isolation structure 110, tunnel oxide 130 and conductor material layer 140.Isolation structure 110 is between two active areas 120.Dispose tunnel oxide 130 and conductor material layer 140 on the active area 120.Active area 120 in conductor material layer 140 and its covering has formed a plurality of semiconductor elements (not illustrating).Then, in substrate 100, form another layer conductor material layer (not illustrating) to cover isolation structure 110 and conductor material layer 140.Then, utilize the photoengraving carving technology, the patterned conductor material layer also forms an opening 165 that exposes isolation structure 110, to produce the lead 150a (word line) that each bar that is illustrated as Figure 1B connects memory cell array.

Yet the above-mentioned photoengraving carving technology that utilizes is made the method for lead 150a, because the bottleneck (bottle neck) of the optical design law (optical design rule) of photoetching process, and can't carry out the making of the lead 150a of thin size.And the accuracy of the pattern of lead 150a also can be exposed the influence of accuracy.In other words, when the angle of exposure position of photomask or exposure light source was offset to some extent, the position of exposing patterns also can be offset thereupon, and had influence on the accuracy that forms lead 150a position.For instance, produce under the situation of skew at the photoresist mask 170 that is used to form lead 150a, use dry etch process to remove the segment conductor material layer and when forming lead 150a, may be damaged to conductor material layer 140 or even be damaged to tunnel oxide 130 (shown in Fig. 1 C).The result will cause the electrical connection between the element to be affected, and makes the element can't normal operation.

Summary of the invention

Purpose of the present invention is exactly in structure that a kind of lead is provided and manufacture method thereof, and it is suitable for the thin and higher a kind of lead of position precision of manufactured size.

Based on above-mentioned purpose or other purpose, the present invention proposes a kind of manufacture method of lead.At first, provide a substrate, formed a plurality of isolation structures in this substrate, it protrudes in this substrate surface, and is formed with one first conductor layer between adjacent two isolation structures.Then, in this substrate, form a dielectric layer, this dielectric layer patternization is exposed one first opening of this first conductor layer with formation.Then, in this substrate, form one second conductor layer.At last, remove this first opening this second conductor layer of part in addition to form a lead that is electrically connected this first conductor layer.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, the first above-mentioned conductor layer and the material of second conductor layer comprise doped polycrystalline silicon or metal.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, the first above-mentioned conductor layer and the formation method of second conductor layer comprise physical vaporous deposition or chemical vapour deposition technique.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, the above-mentioned method that removes this second conductor layer of part comprises chemical mechanical milling method or eat-backs method.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, the formation method of above-mentioned isolation structure comprises the shallow trench isolation method.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, this above-mentioned dielectric layer comprises one first dielectric layer and one second dielectric layer that is formed on this first dielectric layer.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, the first above-mentioned dielectric layer comprises the material that has different etching selectivities with first conductor layer with the material of this second dielectric layer.The material of first dielectric layer comprises the material that has different etching selectivities with the material of isolation structure.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, wherein the material of this first dielectric layer comprises silicon nitride.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, wherein the material of this second dielectric layer comprises silica.

Manufacture method according to the described lead of the preferred embodiments of the present invention, wherein before forming dielectric layer in the substrate, in first conductor layer, also be formed with a plurality of plough groove type elements, each plough groove type element be by tunnel oxide, control grid, two floating grids with and grid between dielectric layer constituted.Tunnel oxide is disposed at the flute surfaces in the substrate, and floating grid is disposed at the both sides of control grid, and dielectric layer is being controlled between grid and two floating grids between grid.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, above-mentioned lead is a word line.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, wherein the formation method of the isolation structure and first conductor layer is prior to forming one deck conductor material layer in the substrate.Then, on conductor material layer, form one deck mask layer.Then, patterned mask layer and conductor material layer are with at least two second openings that form patterned mask layer, first conductor layer and expose substrate.Afterwards, be mask with the patterned mask layer, remove the part substrate, in substrate, to form at least two grooves.Continue it, in substrate, form one deck insulation material layer, utilize chemical mechanical milling method to remove this insulation material layer of part, up to exposing patterned mask layer.Then, remove patterned mask layer.

Because the material of first dielectric layer of the present invention has different etching selectivities with the material of isolation structure, thus at patterning first dielectric layer when having formed the opening that exposes first conductor layer to the open air, can be with isolation structure as alignment mask voluntarily.And, because the material of first dielectric layer has different etching selectivities with the material of first conductor layer,, can not injure first conductor layer even produce the situation of mis-alignment yet, therefore method of the present invention can increase process margin.Simultaneously, because more can cooperating, the manufacture method of lead of the present invention aims at shallow trench isolation voluntarily from (therefore self-aligned shallow trench isolation, SASTI) technology can improve the reliability of total further.

The present invention reintroduces a kind of manufacture method of lead, and comprising provides substrate, forms conductor material layer and mask layer then in substrate in regular turn.This mask layer of patterning and conductor material layer are with at least two first openings that form patterned mask layer, first conductor layer and expose substrate.Then, be mask with this patterned mask layer, remove the part substrate, in substrate, to form at least two grooves.Afterwards, in groove, form one deck insulation material layer.Then remove patterned mask layer.Form one deck first dielectric layer in substrate, and this first dielectric layer of patterning to be to form second opening between insulation material layer, second opening also exposes first conductor layer.In second opening, form one deck second conductor layer and remove second opening part second conductor layer in addition to form the lead that is electrically connected first conductor layer.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, after wherein first dielectric layer forms, more can form one deck second dielectric layer on first dielectric layer.Wherein, the material of first dielectric layer for example is the material that has different etching selectivities with second dielectric layer.In addition, the material of first dielectric layer for example is the material that has different etching selectivities with first conductor layer and insulating material.The material of first dielectric layer for example is a silicon nitride.The material of second dielectric layer for example is a silica.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, wherein the material of first conductor layer and second conductor layer for example is doped polycrystalline silicon or metal.The formation method of first conductor layer and this second conductor layer for example is physical vaporous deposition or chemical vapour deposition technique.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, the method that wherein removes part second conductor layer for example is chemical mechanical milling method or eat-backs method.

Manufacture method according to the described lead of the preferred embodiments of the present invention, wherein before forming first dielectric layer in the substrate, in first conductor layer, also be formed with a plurality of plough groove type elements, each plough groove type element be by tunnel oxide, control grid, two floating grids with and grid between dielectric layer constituted.Tunnel oxide disposes the flute surfaces in this substrate.Two floating grids are disposed at the both sides of control grid.Dielectric layer is between control grid and two floating grids between grid.

According to the manufacture method of the described lead of the preferred embodiments of the present invention, wherein lead is a word line.

Aim at shallow ditch groove separation process voluntarily because the manufacture method of lead of the present invention can cooperate, therefore can improve the reliability of total further.And the material of first dielectric layer of the present invention has different etching selectivities with the material of isolation structure, at patterning first dielectric layer when having formed the opening that exposes first conductor layer to the open air, can be with isolation structure as alignment mask voluntarily.Moreover, because the material of first dielectric layer has different etching selectivities with the material of first conductor layer,, can not injure first conductor layer even produce the situation of mis-alignment yet, therefore method of the present invention can increase process margin.

For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.

Description of drawings

Figure 1A be a flash memory array on look schematic diagram.

Figure 1B and Fig. 1 C be among Figure 1A along the section of P-P ' hatching, illustrate the making result's of lead generalized section.

Fig. 2 be a flash memory array on look schematic diagram.

Fig. 2 A to Fig. 2 I be among Fig. 2 along the section of A-A ' hatching, illustrate the generalized section of the making flow process of lead.

Fig. 3 A be one have the plough groove type element array on look schematic diagram, illustrated in the manufacturing process of array with plough groove type element, on the word line production phase, look schematic diagram.

Fig. 3 B be among Fig. 3 A along the profile of B-B ' hatching, illustrated in the manufacturing process of array, in the generalized section of word line production phase with plough groove type element.

Fig. 3 C be among Fig. 3 A along the profile of C-C ' hatching, illustrated in the manufacturing process of array, in the generalized section of word line production phase with plough groove type element.

The simple symbol explanation

100,200,320: substrate

110,246,310: isolation structure

120,248,330: active area

130,230a, 370: tunnel oxide

140,150,240,395: conductor material layer

150a, 270a, 395a: lead

160: patterning photoresist layer

165,247,265,365: opening

230: oxide layer

230a: pad oxide

240a, 270,305: conductor layer

242,260a, 336a: mask layer

242a: patterned mask layer

244: groove

250,250a, 260,335,335a, 336: dielectric layer

300: the plough groove type element

340: the control grid

350a, 350b: floating grid

360: embedded type bit line

380: dielectric layer between grid

390: protective layer

A-A ', B-B ', C-C ', P-P ': hatching

Embodiment

[first embodiment]

Fig. 2 A to 2G is the manufacturing process profile of a kind of lead of the preferred embodiment of the present invention, and the direction along A-A ' hatching among its profile direction such as Fig. 2 is please jointly with reference to Fig. 2 A～2G.

Please refer to Fig. 2 A, substrate 200 is provided, in substrate 200, form layer of oxide layer 230, one deck conductor material layer 240 and one deck mask layer 242 in regular turn.The material of oxide layer 230 for example is a silica.The material of conductor material layer 240 for example is doped polycrystalline silicon or metal.And the material of mask layer 242 for example is a silicon nitride.The formation method of oxide layer 230 for example is a thermal oxidation method, and the formation method of conductor material layer 240 and mask layer 242 for example is physical vaporous deposition (physical vapor deposition, PVD) or chemical vapour deposition technique (chemical vapor deposition, CVD).

Then, please refer to Fig. 2 B, for example with dry etch process patterned mask layer 242, conductor material layer 240 and oxide layer 230, to form patterned mask layer 242a, conductor layer 240a, tunnel oxide 230a and at least two openings 247 that expose substrate 200.

Please refer to Fig. 2 C, is mask with patterned mask layer 242a, removes part substrate 200, to form at least two grooves 244 in substrate 200.The method that removes part substrate 200 for example is a dry etch process.Then, in substrate 200, form one deck insulation material layer (not illustrating) to fill up groove 244.The material of this insulation material layer for example is a silica, and the formation method of this insulation material layer for example is a chemical vapour deposition technique.Afterwards, utilize chemical mechanical milling method to remove this insulation material layer of part, up to exposing patterned mask layer 242a, and form isolation structure 246, and define active area 248.

Then, please refer to Fig. 2 D, remove patterned mask layer 242a and SI semi-insulation material layer.The method that removes patterned mask layer 242a and SI semi-insulation material layer for example is a wet etch process.Present embodiment is to aim at shallow ditch groove separation process (SASTI) voluntarily the formation method of isolation structure 246 to be described.Certainly, the formation method of isolation structure 246 also can be a shallow trench isolation method (STI).

Then, please continue E, in substrate 200, form a dielectric layer 250, on dielectric layer 250, form a dielectric layer 260 again to cover dielectric layer 250 to cover isolation structure 246 and conductor layer 240a with reference to Fig. 2.Wherein, the material of dielectric layer 250 is preferably the material that has different etching selectivities with the material of conductor layer 240a, isolation structure 250 and dielectric layer 260.In addition, the material of dielectric layer 250 is a silicon nitride for example, and is covered in dielectric layer 260 on the dielectric layer 250 for optionally, and it can be used as the used mask layer of etching dielectric layer 250, for example is silica.

Afterwards, please continue the F with reference to Fig. 2, form one deck patterning photoresist layer 262 in substrate 200, be that mask removes part dielectric layer 260 with patterning photoresist layer 262, to form mask layer 260a again.The method that removes part dielectric layer 260 for example is a dry etch process.Then, remove patterning photoresist layer 262.The method that removes patterning photoresist layer 262 for example is ashing (ashing) technology.

Then, shown in Fig. 2 G, be that mask removes part dielectric layer 250, to form a dielectric layer 250a and an opening 265 that exposes conductor layer 240a with mask layer 260a.The method that removes part dielectric layer 250 for example is a dry etch process.

Then, please continue H with reference to Fig. 2, in substrate 200, form a conductor layer 270, the material of this conductor layer 270 is doped polycrystalline silicon or metal for example, and the formation method of conductor layer 270 for example is physical vaporous deposition (physical vapor deposition, PVD) or chemical vapour deposition technique (chemicalvapor deposition, CVD).

Afterwards, please refer to Fig. 2 I, for removing stop layer, remove segment conductor layer 270, and on conductor layer 240a, form many lead 270a with electrical connecting element to the surface that exposes dielectric layer 260a with dielectric layer 260a.Wherein, the method that removes of segment conductor layer 270 for example is chemical mechanical milling method (chemical mechanical polishing, CMP) or eat-backs method (etching back).Wherein, formed lead 270a for example is the word line (word line, WL) in the memory array, is arranged in a plurality of semiconductor elements (not illustrating) of the active area 248 of conductor layer 240a and its covering with electrical connection.

In above-mentioned technology with form dielectric layer 250, dielectric layer 260 is that example explains.Certainly the present invention can also not form dielectric layer 260, and only forms dielectric layer 250.Then, be that mask etching dielectric layer 250 forms the opening 265 that exposes conductor layer 240a directly with the photoresist behind the patterning.

Because the material of dielectric layer 250 of the present invention has different etching selectivities with the material of isolation structure 246, so when pattern dielectric layer 250 exposes the opening 265 of conductor layer 240a to the open air with formation, can be with isolation structure 246 as alignment mask voluntarily.

On the other hand, when the position of exposing patterns is offset for some reason to some extent,, therefore can not injure conductor layer 240a because conductor layer 240a is different with the etching selectivity of dielectric layer 250.The present invention and prior art relatively can avoid damaging established conductor layer 240a in the substrate when making lead.

In addition, since the manufacture method of lead of the present invention cooperate to aim at shallow trench isolation voluntarily from (therefore self-aligned shallow trench isolation, SASTI) technology can improve the reliability of total further.

In one embodiment of this invention, the material of lead 270a for example is polysilicon or metal.For further specifying the manufacture method of above-mentioned word line, can be applied to the making of a plough groove type element, below connect the lead of plough groove type element with the making among another second embodiment process be illustrated.

[second embodiment]

Fig. 3 A be one have the plough groove type element array on look schematic diagram, wherein, dotted line institute region is plough groove type element position, and the profile direction of profile 3B is along the section of B-B ' hatching among Fig. 3 A, illustrated in the manufacturing process of array, in the generalized section of word line production phase with plough groove type element.Fig. 3 C is along the section of C-C ' hatching, please jointly with reference to Fig. 3 A to Fig. 3 C among Fig. 3 A.

Illustrate as Fig. 3 A to Fig. 3 C, at first, one substrate 320 is provided, a plurality of isolation structures 310 have been formed in this substrate 320, and 310 of adjacent isolation structures define an active area 330, and in active area 330, be formed with conductor layer 305, and be formed with a plurality of plough groove type elements 300 in the conductor layer 305, wherein, isolation structure 310 is the strip layout, and the formation method of isolation structure 310 is for example for aiming at shallow trench isolation voluntarily from (SASTI) technology or shallow trench isolation method (STI), and its material for example is a silica.In addition, the formation method of plough groove type element 300, those skilled in the art can know its manufacture method, are not given unnecessary details at this.

Please refer to Fig. 3 B; in one embodiment of this invention; plough groove type element 300 for example is a plough groove type flash memory cell, and plough groove type element 300 comprises a tunnel oxide 370, control grid 340, two floating grid 350a, 350b and a protective layer 390 etc. at least.

Wherein, tunnel oxide 370 is disposed at the flute surfaces in the active area 330.Two floating grid 350a, 350b are disposed at the both sides of control grid 340.One protective layer 390 is covered on control grid 340 and two floating grid 350a, the 350b.In a preferred embodiment, plough groove type element 300 for example more comprises an embedded type bit line 360, be disposed in the substrate 320 of groove, and control grid 340 is positioned at the top of embedded type bit line 360.In addition, between control grid 340 and two floating grid 350a, 350b, dielectric layer 380 between grid can be set also.

Then, in the making of lead 395a (word line), can utilize the manufacture method of the lead of first embodiment.

Just in substrate 320, form a dielectric layer 335 (not illustrating), form a dielectric layer 336 (not illustrating) again and be covered on the dielectric layer 335.Then, pattern dielectric layer 336 removes part dielectric layer 335 according to mask layer 336a again to form mask layer 336a, with a plurality of openings 365 (not illustrating) that form dielectric layer 335a and expose those plough groove type elements and active area 330.Wherein, the material of dielectric layer 335 for example is the material that has different etching selectivities with isolation structure 310, conductor layer 305 and mask layer 336a.In addition, the material of dielectric layer 335 is a silicon nitride for example, and the material that is covered in the dielectric layer 336 on the dielectric layer 335 for example is silica.

Then, in substrate 320, form a conductor layer 395, the material of conductor layer 395 is doped polycrystalline silicon or metal for example, and the formation method of conductor layer 395 for example is physical vaporous deposition (physicalvapor deposition, PVD) or chemical vapour deposition technique (chemical vapor deposition, CVD).

Afterwards, for removing stop layer, remove segment conductor layer 395, on active area 330, to form many lead 395a that fill up those openings 365 and be electrically connected those plough groove type elements voluntarily to the surface that exposes mask layer 336a with mask layer 336a.In a preferred embodiment, the method that removes of segment conductor layer 395 for example is chemical mechanical milling method (chemical mechanical polishing, CMP) or eat-backs method (etching back).Wherein, formed lead 395a for example is the word line (word line, WL) in the memory array, is arranged in a plurality of plough groove type elements 300 of active area 330 with electrical connection.

In above-mentioned technology with form dielectric layer 335, dielectric layer 336 is that example explains.Certainly the present invention can also not form dielectric layer 336, and only forms dielectric layer 335.Then, be that mask etching dielectric layer 335 forms the opening 365 that exposes plough groove type element 300 directly with the photoresist behind the patterning.

Because dielectric layer 335 of the present invention has different etching selectivities with isolation structure 310, therefore in pattern dielectric layer 335 when forming the opening 365 of exposure plough groove type element 300, can be with isolation structure 310 as alignment mask voluntarily.

On the other hand, when the position of exposing patterns is offset for some reason to some extent, because of conductor layer 305 different with the etching selectivity of dielectric layer 335, so when utilizing dry etch process to make opening 365 unlikely damage plough groove type element 300.The present invention and prior art relatively can avoid damaging established plough groove type element 300 in the substrate when forming word line.

Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.

Claims (25)

1, a kind of manufacture method of lead comprises:

Substrate is provided, has formed at least two isolation structures in this substrate, be formed with first conductor layer between adjacent this two isolation structure;

In this substrate, form dielectric layer;

This dielectric layer of patterning is to form first opening that exposes this first conductor layer;

In this substrate, form second conductor layer; And

Remove this first opening this second conductor layer of part in addition to form the lead that is electrically connected this first conductor layer.

2, the manufacture method of lead as claimed in claim 1, wherein the material of this first conductor layer and this second conductor layer comprises doped polycrystalline silicon or metal.

3, the manufacture method of lead as claimed in claim 1, wherein the formation method of this first conductor layer and this second conductor layer comprises physical vaporous deposition or chemical vapour deposition technique.

4, the manufacture method of lead as claimed in claim 1, the method that wherein removes this second conductor layer of part comprises chemical mechanical milling method or eat-backs method.

5, the manufacture method of lead as claimed in claim 1, wherein the formation method of those isolation structures comprises the shallow trench isolation method.

6, the manufacture method of lead as claimed in claim 1, wherein this dielectric layer comprises first dielectric layer and second dielectric layer that is formed on this first dielectric layer.

7, the manufacture method of lead as claimed in claim 6, wherein this first dielectric layer comprises the material that has different etching selectivities with this first conductor layer with the material of this second dielectric layer.

8, the manufacture method of lead as claimed in claim 6, wherein the material of this first dielectric layer comprises the material that has different etching selectivities with this second dielectric layer.

9, the manufacture method of lead as claimed in claim 6, wherein the material of this first dielectric layer comprises the material that has different etching selectivities with this isolation structure.

10, the manufacture method of lead as claimed in claim 6, wherein the material of this first dielectric layer comprises silicon nitride.

11, the manufacture method of lead as claimed in claim 6, wherein the material of this second dielectric layer comprises silica.

12, the manufacture method of lead as claimed in claim 1 wherein before forming this dielectric layer in this substrate, also is formed with a plurality of plough groove type elements in this first conductor layer, each those plough groove type element comprises:

Tunnel oxide is disposed at the flute surfaces in this substrate;

The control grid;

Two floating grids are disposed at the both sides of this control grid; And

Dielectric layer between grid is between this control grid and this two floating grid.

13, the manufacture method of lead as claimed in claim 1, wherein this lead is a word line.

14, the manufacture method of lead as claimed in claim 1, wherein the formation method of those isolation structures and this first conductor layer comprises:

In this substrate, form conductor material layer;

On this conductor material layer, form mask layer;

This mask layer of patterning and this conductor material layer are with at least two second openings that form patterned mask layer, this first conductor layer and expose this substrate;

With this patterned mask layer is mask, removes this substrate of part, to form at least two grooves in this substrate;

In this substrate, form insulation material layer;

Utilize chemical mechanical milling method to remove this insulation material layer of part, up to exposing this patterned mask layer; And

Remove this patterned mask layer.

15, a kind of manufacture method of lead comprises:

Substrate is provided;

In this substrate, form conductor material layer and mask layer in regular turn;

This mask layer of patterning and this conductor material layer are with at least two first openings that form patterned mask layer, first conductor layer and expose this substrate;

With this patterned mask layer is mask, removes this substrate of part, to form at least two grooves in this substrate;

In this two groove, form insulation material layer;

Remove this patterned mask layer;

In this substrate, form first dielectric layer;

This first dielectric layer of patterning is to form second opening between this insulation material layer, this second opening also exposes this first conductor layer;

In this second opening, form second conductor layer; And

Remove this second opening this second conductor layer of part in addition to form the lead that is electrically connected this first conductor layer.

16, the manufacture method of lead as claimed in claim 15 after wherein this first dielectric layer forms, also comprises forming second dielectric layer on this first dielectric layer.

17, the manufacture method of lead as claimed in claim 16, wherein the material of this first dielectric layer comprises the material that has different etching selectivities with this second dielectric layer.

18, the manufacture method of lead as claimed in claim 17, wherein the material of this second dielectric layer comprises silica.

19, the manufacture method of lead as claimed in claim 15, wherein the material of this first dielectric layer comprises the material that has different etching selectivities with this first conductor layer and this insulating material.

20, the manufacture method of lead as claimed in claim 15, wherein the material of this first dielectric layer comprises silicon nitride.

21, the manufacture method of lead as claimed in claim 15, wherein the material of this first conductor layer and this second conductor layer comprises doped polycrystalline silicon or metal.

22, the manufacture method of lead as claimed in claim 15, wherein the formation method of this first conductor layer and this second conductor layer comprises physical vaporous deposition or chemical vapour deposition technique.

23, the manufacture method of lead as claimed in claim 15, the method that wherein removes this second conductor layer of part comprises chemical mechanical milling method or eat-backs method.

24, the manufacture method of lead as claimed in claim 15 wherein before forming this first dielectric layer in this substrate, also is formed with a plurality of plough groove type elements in this first conductor layer, each those plough groove type element comprises:

Tunnel oxide is disposed at the flute surfaces in this substrate;

The control grid;

Two floating grids are disposed at the both sides of this control grid; And

Dielectric layer between grid is between this control grid and this two floating grid.

25, the manufacture method of lead as claimed in claim 15, wherein this lead is a word line.

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