CN100530738C - Phase-change memory cell structure and fabrication method thereof - Google Patents
Phase-change memory cell structure and fabrication method thereof Download PDFInfo
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- CN100530738C CN100530738C CNB2006101214677A CN200610121467A CN100530738C CN 100530738 C CN100530738 C CN 100530738C CN B2006101214677 A CNB2006101214677 A CN B2006101214677A CN 200610121467 A CN200610121467 A CN 200610121467A CN 100530738 C CN100530738 C CN 100530738C
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- 238000000034 method Methods 0.000 title claims description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000012782 phase change material Substances 0.000 claims description 55
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 9
- 239000005368 silicate glass Substances 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 150000004770 chalcogenides Chemical class 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 229910010037 TiAlN Inorganic materials 0.000 claims description 4
- 239000012634 fragment Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 2
- 230000009466 transformation Effects 0.000 abstract description 4
- 230000002441 reversible effect Effects 0.000 abstract description 2
- 210000000352 storage cell Anatomy 0.000 abstract 1
- 230000008569 process Effects 0.000 description 19
- 238000001259 photo etching Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 11
- 230000008859 change Effects 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000000059 patterning Methods 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- 239000005380 borophosphosilicate glass Substances 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 150000001786 chalcogen compounds Chemical class 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000010422 painting Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
This invention relates to phase transformation storage cell structure. It involves a substrate on the bottom; from this bottom up to the top, presented successively are: a first electrode layer; a first dielectric layer; an electroconductive contactant placed within said dielectric layer for contacting the first electrode layer, which contactant has L or reverse L cross section; a second dielectric layer, which covers said contactant; a phase transformation matter layer within the second dielectric layer with electrically contacting said contactant; a second electrode layer placed on the top and electrically contacting said phase transformation matter layer.
Description
Technical field
The present invention relates to a kind of memory device, relate in particular to phase-change memory cell structure and manufacture method thereof.
Background technology
Speciality non-volatile, that height reads signal, high density, high erasable number of times and low-work voltage/electric current that phase transformation (phase change) memory has is quite potential nonvolatile memory.Wherein improving storage density, reducing current density is the important techniques index.
Phase-change material can present at least two kinds solid-state, comprise crystalline state and noncrystalline attitude, the conversion between binary states is carried out in the change of general using temperature, owing to the atomic arrangement of noncrystalline attitude confusion has higher resistance, therefore can distinguish the crystalline state and the noncrystalline attitude of phase-change material easily by simple electrically measurement.In various phase-change materials, chalcogenide extensive use to the various optical recording elements.
Since phase-change material change a kind of reversible reaction mutually into, when therefore phase-change material is used for being used as storage medium, be to store, that is to say that bank bit (0,1) is to utilize between binary states the difference of resistance to distinguish by the conversion between non-crystalline state and the crystalline state binary states.
Disclosed a kind of memory cell structure of using phase-change material in 6,534, No. 780 patents of U.S. US, its memory cell is arranged at four edges of cross thrust.Its applied technology is rather tediously long, needs to use nearly ten road photoetching processes.So, its formed memory cell structure is vulnerable to the photoetching process factor affecting and causes structural difference between its memory cell.
Summary of the invention
In view of this, purpose of the present invention provides a kind of phase-change memory cell structure and manufacture method thereof, its contact structures that adopt positive L or anti-L type can be produced integrated memory cell array to be electrically connected phase-change material layers and electrode in the process application of simplifying.
According to above-mentioned purpose, the invention provides a kind of phase-change memory cell structure, comprising:
First electrode layer is arranged on the substrate; First dielectric layer is arranged on this first electrode layer; The conduction contactant is arranged in this first dielectric layer to electrically contact this first electrode layer, and wherein this conduction contactant has positive L or anti-L (") section; Second dielectric layer is arranged on this first dielectric layer and covers this conduction contactant; Phase-change material layers is arranged in this second dielectric layer and electrically contacts this conduction contactant; And the second electrode lay, be arranged on this second dielectric layer and electrically contact this phase-change material layers.
The present invention also provides a kind of phase-change memory cell structure, comprising:
First electrode layer is arranged on the substrate along the first direction extension; First dielectric layer covers this first electrode layer and this substrate; The pair of conductive contactant is arranged in this first dielectric layer respectively and electrically contacts this first electrode layer, and wherein those conduction contactants have positive L or anti-L (") section; Second dielectric layer, be arranged on this first dielectric layer and cover those the conduction contactant; A pair of phase-change material layers is arranged in this second dielectric layer and covers those conduction one of contactants respectively; And a pair of the second electrode lay, extend and be arranged at respectively on this second dielectric layer along second direction, to electrically contact one of those phase-change material layers.
The present invention also provides a kind of manufacture method of phase-change memory cell structure, comprising:
Form first electrode layer on substrate, this first electrode layer extends setting and partly covers this substrate along first direction; Form first dielectric layer to cover this first electrode layer and this substrate; In this first dielectric layer, form first opening, this of exposed portions serve first electrode layer; Form a pair of have positive L or anti-L (" in the both sides of this first opening) the conduction contactant of section, those conduction contactants electrically contact the sidewall of this first electrode layer and first dielectric layer that is exposed by this first opening respectively; Form second dielectric layer, to fill up this first opening and to cover those conduction contactants; Form a pair of phase-change material layers, part is covered on this first and second dielectric layer and electrically contacts one of those conduction contactants respectively; Form the 3rd dielectric layer, smooth those phase-change material layers and this first and second dielectric layer of covering with covering; Form a pair of the 3rd and be opened in the 3rd dielectric layer, expose one of those phase-change material layers respectively; And form a pair of the second electrode lay on the 3rd dielectric layer of part, and extend and fill up the 3rd opening along second direction respectively, to electrically contact one of those phase-change material layers respectively, wherein this second direction differs from this first direction.
The phase-change memory cell structure that the manufacture method of above-mentioned this phase-change memory cell structure manufactures comprises two memory cell.
According to another embodiment of the present invention, the manufacture method of above-mentioned phase-change memory cell structure forms a pair of have positive L or anti-L (" in the both sides of this first opening) during the conduction contactant of section; also remove this first electrode layer that is exposed this conductive layer below by this second opening simultaneously, and this first electrode layer is separated into the first electrode fragment and the second electrode fragment.So, the phase-change memory cell structure that manufactures of the manufacture method of above-mentioned this phase-change memory cell structure comprises two electrical memory cell independently.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:
Description of drawings
Figure 1A, 2A, 3A, 4A, 5A are a series of schematic diagrames, look situation in the manufacture method of the phase-change memory cell structure that is presented at one embodiment of the invention;
Figure 1B is a schematic diagram, in order to show the section situation along 1B-1B line segment among Figure 1A;
Fig. 2 B is a schematic diagram, in order to show the section situation along 2B-2B line segment among Fig. 2 A;
Fig. 3 B is a schematic diagram, in order to show the section situation along 3B-3B line segment among Fig. 3 A;
Fig. 4 B is a schematic diagram, in order to show the section situation along 4B-4B line segment among Fig. 4 A;
Fig. 5 B is a schematic diagram, in order to show the section situation along 5B-5B line segment among Fig. 5 A;
Fig. 6 A, 7A are a series of schematic diagrames, look situation in the manufacture method of the phase-change memory cell structure that is presented at another embodiment of the present invention;
Fig. 6 B is a schematic diagram, in order to show the section situation along 6B-6B line segment among Fig. 6 A; And
Fig. 7 B is a schematic diagram, in order to show the section situation along 7B-7B line segment among Fig. 7 A.
The simple symbol explanation
100～memory device;
102～substrate;
104,108,108b, 118～conductive layer;
104a～conductive segment;
106,112,116～dielectric layer;
108a～conduction contactant;
110～photoresist layer;
114～phase-change material layers;
300a, 300b～memory cell.
Embodiment
Embodiments of the invention will cooperate schematic diagrames such as Figure 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, 5A and 5B to be described in detail as follows, wherein Figure 1A, 2A, 3A, 4A, 5A shown when the different phase that phase-change memory cell structure is made on look situation, Figure 1B, 2B, 3B, 4B, 5B have then shown the section situation in the memory cell region in above-mentioned different phase respectively.
Please refer to Figure 1A and Figure 1B, part illustrates the memory cell array in the phase change memory device 100.The making of phase change memory device 100 at first provides Semiconductor substrate, for example is silicon substrate.On this Semiconductor substrate, can be provided with semiconductor device that a promising dielectric layer covered with and/or other conduction interconnect structure, and set semiconductor device for example is transistorized active element on it.Those skilled in the art is when understanding, and above-mentioned active element can be in electrical contact with the memory cell in the memory array by the conduction interconnect structure that is arranged at the appropriate location, uses the store status of memory cell in the control storage array.Be simplicity of illustration, only illustrating in Figure 1B is a smooth substrate 102.
Then, the smooth layer of conductive material that forms for example is materials such as Ti, TiN, TiW, W, Al, Cu, TaN with covering on substrate 102, and it can utilize chemical vapour deposition technique (CVD) or sputtering method and be formed on the substrate 102.Then by the enforcement of photoetching process (not shown), the above-mentioned layer of patterning electric conducting material becomes many conductive layers of separating each other 104.At this, shown in Figure 1A, these conductive layers 104 extend and cover part substrate 102 along the x direction abreast.Then, smooth one deck dielectric material that forms on substrate 102 with covering, its thickness is preferably greater than conductive layer 104 and covers above-mentioned conductive layer 104.At this, the material of this dielectric material for example be boron phosphorus silicate glass (Borophosphosilicate glass, BPSG), silica or silicon nitride.Then, the use that utilizes photoetching process is with this layer of patterning dielectric material, and then the dielectric layer 106 of the patterning of formation shown in Figure 1A and opening therebetween, and the conductive layer 104 and substrate 102 of exposed portions serve.Figure 1B has then shown along the signal of the section in the 1B-1B line segment among Figure 1A situation.
Please then on the structure shown in Figure 1A and 1B, form conductive layer 108 simultaneously with reference to Fig. 2 A, 2B.Conductive layer 108 conformally covers sidewall, the conductive layer 104 of dielectric layer 106 and the dielectric layer 106 that had before exposed.At this, the material of conductive layer 108 for example is TiN, TaN or TiW, TiAlN, and its thickness between 1 to 100nm, preferably is about 5nm approximately, and it can be by chemical vapour deposition technique (CVD) or sputtering method and forms.Follow painting photoresist material on substrate 102.The smooth surface that covers conductive layer 108 with covering and formed planarization of this photo anti-corrosion agent material.By, implement photoetching process (not shown) with this photo anti-corrosion agent material of patterning, and then formed the photoresist layer 110 of a plurality of patternings shown in Fig. 2 A.These photoresist layers 110 partly cover the conductive layer 108 of below respectively and are arranged at conductive layer 104 tops of below substantially.Fig. 2 B has shown along the signal of the section in the 2B-2B line segment among Fig. 2 A situation, photoresist layer 110 is arranged at the both sides of conductive layer 104 and covers the conductive layer 108 that is positioned on the dielectric layer 106 substantially at this moment, photoresist layer 110 and part fill in the opening that is defined for dielectric layer 106, and and then define another less opening partly to expose the conductive layer 108 in it.
Please be simultaneously with reference to Fig. 3 A, 3B, then to implementing etching program (not shown) on the structure shown in Fig. 2 A and the 2B, and adopt previous photoresist layer 110 as etching mask, be not the conductive layer 108 that photoresist layer 110 is covered to remove.Then, after removing photoresist layer 110, the smooth dielectric material (not shown) that forms to cover dielectric layer 106 and to fill in the opening that is defined by dielectric layer 106 with covering.At this, the material of dielectric material for example is that (Borophosphosilicate glass, BPSG), silica or spin-coating glass (spin on glass, SOG), it can form by methods such as chemical vapour deposition (CVD) or rotary coating boron phosphorus silicate glass.Then, implement the planarization program, for example be cmp (CMP) program, exceed the dielectric material of dielectric layer 106 and conductive layer 108 parts that covered for previous photoresist layer and in the opening that is defined by dielectric layer 106, form dielectric layer 112 with worn.Therefore, with reference to shown in Fig. 3 B along the section in the 3B-3B line segment among Fig. 3 A signal situation, can find that last both sides in the opening that is defined by dielectric layer 106 stay conduction contactant 108a respectively.These conductions contactant 108a for electrically independently conduct electricity contactant and have positive L or anti-L (") cross-section structure.Conduction contactant 108a is made of the vertical component effect of contact dielectric layer 106 sidewalls and the bottom of contact conductive layer 104 respectively.At this moment, shown in Fig. 3 B, dielectric layer 106, dielectric layer 112 and conduction contactant 108a and substrate 102 cardinal principle coplines are so that flat surfaces to be provided, in order to the carrying out of subsequent technique.
Please follow smooth one deck phase-change material that forms on substrate 102 simultaneously with reference to Fig. 4 A, 4B with covering, and then cover dielectric layer 106,112 and conduction contactant 108a.Generally speaking, phase-change material is a chalcogenide, for example is Ge-Te-Sb ternary chalcongen compound or Te-Sb binary chalcogen compound, and its generation type can be chemical vapour deposition technique or sputtering method, and its thickness between 10 to 200nm, preferably is about 100nm approximately.Then, with this layer of patterning phase-change material, on substrate, form a plurality of phase-change material layers 114 shown in Fig. 4 A by the enforcement of photoetching process (not shown).Please refer to Fig. 4 B, shown along the signal of the section in the 4B-4B line segment among Fig. 4 A situation, at this moment, 114 conduction contactant 108a that separate and cover respectively substantially the below each other of these phase-change material layers are to be electrically connected on the conductive layer 104 that is positioned at the below.
Please follow the smooth dielectric layer 116 that forms on the structure shown in Fig. 4 A, 4B simultaneously with reference to Fig. 5 A, 5B, its thickness is preferably more than phase-change material layers 114 with covering.The material of dielectric layer 116 for example is boron phosphorus silicate glass Borophosphosilicate glass, and BPSG), silica or spin-coating glass (spinon glass, SOG), it can form by methods such as chemical vapour deposition (CVD) or rotary coating.Utilize photoetching process then, in dielectric layer 116, form a plurality of openings, these openings corresponding to the phase-change material layers 114 of below set and part expose the phase-change material layers 116 of its below.Then, the smooth layer of conductive material that forms for example is materials such as Al, Ti, TiN with covering on dielectric layer 116.Above-mentioned electric conducting material also fills in these openings that expose phase-change material layers 114.Via the definition of follow-up photoetching process, form the conductive layer 118 of a plurality of separations at dielectric layer 116.Shown in Fig. 5 A, conductive layer 118 extends to form and partly covers dielectric layer 116 along the y direction.Please refer to Fig. 5 B, shown along the signal of the section in the 5B-5B line segment among Fig. 5 A situation.At this moment, conductive layer 118 has a protuberance, extends downwards and fills in the opening that is formed in the phase-change material layers top dielectric layer 116, and then electrically contact the phase-change material layers 116 of below.
Technology so far, the making of the phase change memory device of present embodiment has just been finished substantially.Shown in Fig. 5 A, dashed region 300a has indicated the zone of unit storage unit in the present embodiment, and its cross-section structure comprises as shown in Fig. 5 B:
First electrode layer (conductive layer 104) is arranged on the substrate (substrate 102) along first direction (the x direction among Fig. 5 A) extension; First dielectric layer (dielectric layer 106) covers this first electrode layer and this substrate; Pair of conductive contactant (conduction contactant 108a) is arranged in this first dielectric layer respectively and electrically contacts this first electrode layer, and wherein those conduction contactants have positive L or anti-L (") section; Second dielectric layer (dielectric layer 116), be arranged on this first dielectric layer and cover those the conduction contactant; A pair of phase-change material layers (phase-change material layers 114) is arranged in this second dielectric layer and covers those conduction one of contactants respectively; And a pair of the second electrode lay (conductive layer 118), extend and be arranged at respectively on this second dielectric layer along second direction, to electrically contact one of those phase-change material layers.
Phase-change memory cell structure in the present embodiment is two (dual bit) memory cell, its first electrode layer (conductive layer 104) can be electrically connected on the active device (not shown) on the substrate 102, transistor unit for example, and cooperate the control of the second electrode lay (conductive layer 118) and four kinds of remember conditions are provided.In addition, by repeating to be provided with as Fig. 5 A, the unit storage unit structure of the present embodiment shown in the 5B then can provide a kind of integrated phase change memory array, it can preparation be finished only using simplifying under the manufacturing process of six road photoetching processes, be applicable to memory array that forms high density memory cells and the influence that the uniformity between memory cell more is not vulnerable to the photoetching process factor, thereby can improve as conventional as U.S. US6, cause between its memory cell the defective of difference on the structure because of using nearly ten road photoetching processes to make formed memory cell structure be vulnerable to the photoetching process factor affecting in 534, No. 780 patents.Moreover the conduction contactant that has used positive and negative L type in the phase-change memory cell in the present embodiment has advantage that reduces contact area and the waste of having avoided area as the conductive electrode between upper/lower electrode.
Another embodiment of the present invention will cooperate schematic diagrames such as Fig. 6 A, 6B, 7A and 7B to be described in detail as follows, wherein Fig. 6 A, 7A shown when the different phase that phase-change memory cell structure is made on look situation, Fig. 6 B, 7B have then shown the section situation in the memory cell region in above-mentioned different phase respectively.Because present embodiment is another improvement situation of previous embodiment, so only be described in detail difference and no longer repeat identical processing step at this.
Please at first adopt the processing step that is explained orally as previous Figure 1A, 1B, 2A, 2B simultaneously with reference to Fig. 6 A, 6B, form the structure shown in Fig. 2 A, 2B.Then to implementing etching program (not shown) on the structure shown in Fig. 2 A and the 2B, and adopt previous photoresist layer 110,, stay the conductive layer 108b of patterning to remove the conductive layer 108 that is not covered by photoresist layer 110 as etching mask.Then, after removing photoresist layer 110, form photoresist layer (not shown) once more and fill in the opening that is defined by dielectric layer 106, then, form another opening (not shown) with definition in the photoresist layer via the execution of photoetching process (not shown).The edge aligned in general of this opening is positioned at the conductive layer 108b of the opening that is defined by dielectric layer 106, and exposes the partially conductive layer 104 of below.Then implement etch process and be etching mask, remove conductive layer 104 parts of exposing, stay a plurality of conductive segment 104a with this photoresist layer.Fig. 6 B has then shown along the section situation in the 6B-6B line segment among Fig. 6 A.
Then then can continue to use the processing step that previous Fig. 3 A, 3B, 4A, 4B, 5A, 5B etc. are explained orally, form the structure shown in Fig. 7 A, 7B.So, the making of the phase change memory device of present embodiment has just been finished substantially.Shown in Fig. 7 A, dashed region 300b has indicated the zone of unit storage unit in the present embodiment, and its cross-section structure comprises as shown in Fig. 7 B:
First electrode layer (conductive segment 104a) is arranged on the substrate (substrate 102); First dielectric layer (dielectric layer 106) is arranged on this first electrode layer; Conduction contactant (108a) is arranged in this first dielectric layer to electrically contact this first electrode layer, and wherein this conduction contactant has positive L or anti-L (") section; Second dielectric layer (dielectric layer 116) is arranged on this first dielectric layer and covers this conduction contactant; Phase-change material layers (phase-change material layers 114) is arranged in this second dielectric layer and electrically contacts this conduction contactant; And the second electrode lay (conductive layer 118), be arranged on this second dielectric layer and electrically contact this phase-change material layers.
Phase-change memory cell structure in the present embodiment is single position (single bit) memory cell, its first electrode layer (conductive segment 104a) can be electrically connected on the active device (not shown) on the substrate 102, transistor unit for example, and cooperate the control of the second electrode lay (conductive layer 118) and two kinds of store statuss are provided.In addition, by repeating to be provided with as Fig. 7 A, the unit storage unit structure of the present embodiment shown in the 7B then can provide a kind of integrated phase change memory array, it can preparation be finished only using simplifying under the manufacturing process of seven road photoetching processes, be applicable to memory array that forms high density memory cells and the influence that the uniformity between memory cell more is not vulnerable to the photoetching process factor, thereby can improve as conventional U.S. US6, cause between its memory cell the defective of difference on the structure because of using nearly ten road photoetching processes to make formed memory cell structure be vulnerable to the photoetching process factor affecting in 534, No. 780 patents.Moreover the conduction contactant that has used positive and negative L type in the phase-change memory cell in the present embodiment has advantage that reduces contact area and the waste of having avoided area as the conductive electrode between upper/lower electrode.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing various changes and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (25)
1. phase-change memory cell structure is characterized in that comprising:
First electrode layer is arranged on the substrate along the first direction extension;
First dielectric layer is arranged on this first electrode layer, has first opening this first electrode layer with exposed portions serve in this first dielectric layer;
The conduction contactant is arranged at the both sides of this first opening of this first dielectric layer, to electrically contact the sidewall of this first electrode layer and first dielectric layer that is exposed for this first opening respectively, wherein this conduction contactant have positive L or " section of the anti-L of shape;
Second dielectric layer is arranged in this first opening of this first dielectric layer to fill up this first opening and to cover those conduction contactants;
Phase-change material layers, part is covered on this first and second dielectric layer and electrically contacts the conduction contactant;
The 3rd dielectric layer covers those phase-change material layers and this first and second dielectric layer; And
The second electrode lay is arranged on the 3rd dielectric layer and fills up the 3rd dielectric layer and is positioned at opening on the phase-change material layers to electrically contact this phase-change material layers.
2. phase-change memory cell structure as claimed in claim 1 is characterized in that this conduction contactant comprises:
The bottom extends on this first electrode layer; And
Side wall portion extends and runs through this first and second dielectric layer, and wherein this bottom electrical contacts this first electrode layer and the top of this side wall portion electrically contacts this phase-change material layers.
3. phase-change memory cell structure as claimed in claim 1 is characterized in that this phase-change material layers is embedded in the 3rd dielectric layer, and this second electrode lay has protuberance, and this protuberance extends downwards in the 3rd dielectric layer to electrically contact this phase-change material layers.
4. phase-change memory cell structure as claimed in claim 1 is characterized in that this phase-change material layers comprises chalcogenide.
5. phase-change memory cell structure as claimed in claim 1 is characterized in that this first dielectric layer can comprise boron phosphorus silicate glass, silica or silicon nitride.
6. phase-change memory cell structure as claimed in claim 1 is characterized in that this second and the 3rd dielectric layer can comprise boron phosphorus silicate glass, silica or spin-coating glass.
7. phase-change memory cell structure as claimed in claim 1 is characterized in that this conduction contactant comprises TiN, TaN, TiAlN or TiW.
8. phase-change memory cell structure is characterized in that comprising:
First electrode layer is arranged on the substrate along the first direction extension, and has the opening of this substrate of exposed portions serve;
First dielectric layer covers this first electrode layer and has first opening, this first electrode layer of this first opening exposed portions serve of this first dielectric layer;
The conduction contactant, the both sides of this first opening that are arranged at this first dielectric layer respectively are to electrically contact the sidewall of this first electrode layer and first dielectric layer that exposed for this first opening respectively, and inside edge that should the conduction contactant is aimed at the edge of the opening of this first electrode layer, wherein those conduct electricity contactants have positive L or " section of the anti-L of shape;
Second dielectric layer is arranged in this opening of this first opening of this first dielectric layer and this first electrode layer and covers those conduction contactants;
Phase-change material layers, part is covered on this first and second dielectric layer and electrically contacts the conduction contactant;
The 3rd dielectric layer covers those phase-change material layers and this first and second dielectric layer; And
The second electrode lay extends and is arranged at respectively on the 3rd dielectric layer along second direction, and fills up the 3rd dielectric layer and be positioned at opening on the phase-change material layers to electrically contact this phase-change material layers.
9. phase-change memory cell structure as claimed in claim 8 is characterized in that this phase-change memory cell structure comprises two memory cell.
10. phase-change memory cell structure as claimed in claim 8 is characterized in that those conduction contactants comprise respectively:
The bottom extends on this first electrode layer; And
Side wall portion extends and runs through this first and second dielectric layer, it is characterized in that this bottom electrical contacts this first electrode layer and the top of this side wall portion electrically contacts this phase-change material layers.
11. phase-change memory cell structure as claimed in claim 8, it is characterized in that those phase-change material layers are embedded in the 3rd dielectric layer, and those the second electrode lays have protuberance respectively, and this protuberance extends downwards in the 3rd dielectric layer to electrically contact this phase-change material layers.
12. phase-change memory cell structure as claimed in claim 8 is characterized in that this phase-change material layers comprises chalcogenide.
13. phase-change memory cell structure as claimed in claim 8 is characterized in that this first dielectric layer comprises boron phosphorus silicate glass, silica or silicon nitride.
14. phase-change memory cell structure as claimed in claim 8 is characterized in that this second and the 3rd dielectric layer comprises boron phosphorus silicate glass, silica or spin-coating glass.
15. phase-change memory cell structure as claimed in claim 8 is characterized in that those conduction contactants comprise TiN, TaN, TiAlN or TiW.
16. the manufacture method of a phase-change memory cell structure is characterized in that comprising:
Form first electrode layer on substrate, this first electrode layer extends setting and partly covers this substrate along first direction;
Form first dielectric layer to cover this first electrode layer and this substrate;
In this first dielectric layer, form first opening, this of exposed portions serve first electrode layer;
Form in the both sides of this first opening a pair of have positive L or " the conduction contactant of the section of the anti-L of shape, those conduction contactants electrically contact the sidewall of this first electrode layer and first dielectric layer that is exposed for this first opening respectively;
Form second dielectric layer, to fill up this first opening and to cover those conduction contactants;
Form a pair of phase-change material layers, part is covered on this first and second dielectric layer and electrically contacts one of those conduction contactants respectively;
Form the 3rd dielectric layer, cover those phase-change material layers and this first and second dielectric layer;
Form the 3rd and be opened in the 3rd dielectric layer, expose one of those phase-change material layers respectively; And
Form the second electrode lay on the 3rd dielectric layer of part, extend and fill up the 3rd opening along second direction respectively, to electrically contact those phase-change material layers respectively, wherein this second direction differs from this first direction.
17. the manufacture method of phase-change memory cell structure as claimed in claim 16, it is characterized in that staying in the both sides of this first opening a pair of have positive L or " step of the conduction contactant of the anti-L section of shape comprises:
Form conductive layer on this first dielectric layer, and cover first dielectric layer and this first electrode layer in this first opening;
Form the photoresist layer, cover this conductive layer and this first opening;
Form second opening in this photoresist layer, this second opening portion exposes the conductive layer in this first opening;
With this photoresist layer is mask, is etched to this conductive layer that this second opening is exposed; And
Remove remaining this photoresist layer, and expose in this first opening those have positive L or " the conduction contactant of the anti-L section of shape.
18. the manufacture method of phase-change memory cell structure as claimed in claim 17, it is characterized in that staying in the both sides of this first opening a pair of have positive L or " during the conduction contactant of the anti-L section of shape; also remove this first electrode layer that exposes this conductive layer below for this second opening simultaneously, this first electrode layer be separated into the first electrode fragment and the second electrode fragment.
19. the manufacture method of phase-change memory cell structure as claimed in claim 16 is characterized in that this phase-change memory cell structure comprises two memory cell.
20. the manufacture method of phase-change memory cell structure as claimed in claim 18 is characterized in that this phase-change memory cell structure comprises two electrical memory cell independently.
21. the manufacture method of phase-change memory cell structure as claimed in claim 16, it is characterized in that those have positive L or " the conduction contactant of the anti-L section of shape comprises respectively:
The bottom extends on this first electrode layer; And
Side wall portion extends and runs through this first dielectric layer, it is characterized in that this bottom electrical contacts this first electrode layer and the top of this side wall portion electrically contacts this phase-change material layers.
22. the manufacture method of phase-change memory cell structure as claimed in claim 16 is characterized in that this phase-change material layers comprises chalcogenide.
23. the manufacture method of phase-change memory cell structure as claimed in claim 16 is characterized in that this first dielectric layer comprises boron phosphorus silicate glass, silica or silicon nitride.
24. the manufacture method of phase-change memory cell structure as claimed in claim 16 is characterized in that this second dielectric layer comprises boron phosphorus silicate glass, silica or spin-coating glass.
25. the manufacture method of phase-change memory cell structure as claimed in claim 16, it is characterized in that those have positive L or " the conduction contactant of the anti-L section of shape comprises TiN, TaN, TiAlN or TiW.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006101214677A CN100530738C (en) | 2006-08-24 | 2006-08-24 | Phase-change memory cell structure and fabrication method thereof |
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| CNB2006101214677A CN100530738C (en) | 2006-08-24 | 2006-08-24 | Phase-change memory cell structure and fabrication method thereof |
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| CN100530738C true CN100530738C (en) | 2009-08-19 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2009122349A2 (en) | 2008-04-01 | 2009-10-08 | Nxp B.V. | Vertical phase change memory cell |
| KR20110035061A (en) * | 2009-09-29 | 2011-04-06 | 삼성전자주식회사 | Phase-change memory device |
| CN102760831A (en) * | 2011-04-27 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory and formation method thereof |
| CN104746006B (en) * | 2013-12-31 | 2017-06-06 | 北京北方微电子基地设备工艺研究中心有限责任公司 | The magnetron sputtering preparation process of the TiW films of adjustable TiW membrane stresses |
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