CN100530629C - Multi-wafer piling base plate and multi-wafer piling encapsulation structure based on this base plate - Google Patents
Multi-wafer piling base plate and multi-wafer piling encapsulation structure based on this base plate Download PDFInfo
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- CN100530629C CN100530629C CN200710003471.8A CN200710003471A CN100530629C CN 100530629 C CN100530629 C CN 100530629C CN 200710003471 A CN200710003471 A CN 200710003471A CN 100530629 C CN100530629 C CN 100530629C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
The invention relates to a multi-chip stacking base plate, packaging structure and use thereof. The base plate at least includes one first wire bonding, one second wire bonding, one trace for electrical transmission and one loop. Both of the first wire bonding and the second wire bonding are dying bonding region near the base plate. The loop concatenates in series the first wire bonding and the second wire bonding and connects to the trace. Consequently, a plurality of chips can arrange by arrange in the dying bonding region and electrically connect into these wire bonding, and each chip can work independently without mutual interference. The multi-chip stacking packaging structure using the base plate can carry out the repair working without seal line after molding.
Description
Technical field
The present invention relates to a kind of circuit substrate of suitable semiconductor packages, particularly relate to substrate, the multi-chip stacking and packaging construction (multi-chip stackpackage) that uses this substrate and application thereof that a kind of polycrystalline sheet piles up.
Background technology
Because electronics technology evolution constantly, functional more complicated, more humane product is weeded out the old and bring forth the new, with regard to the electronic product outward appearance, also towards light, thin, short, little trend design.Along with the increase of microminiaturization and high running speed requirement, a plurality of wafers can be vertically to being stacked on the substrate, to reach capacity or the multi-purpose demand more than many times.All a plurality of wafers that pile up can be sealed in the adhesive body, can be referred to as multi-chip stacking and packaging construction.Yet it is existing known when carrying out multi-chip stacking and packaging construction, be to use these a plurality of wafers of adhesive body sealing, after finishing, sealing again product is carried out testing electrical property, when wherein a wafer can't operate, whole semiconductor semiconductor packaging structure will become the fault product, and the arrangement that can't do after the sealing is repaired.
See also shown in Figure 1ly, a kind of multi-chip stacking and packaging construction comprises a substrate 100, one first wafer 10, one second wafer 20, a plurality of bonding wire 31,32 and an adhesive body 40 at least.Please cooperate with reference to Fig. 2, this substrate 100 is to comprise a plurality of routings to connect finger (wiring-bonding fingers) 110 and a plurality of trace (trace) 120, it is an inner surface 101 that is formed at this substrate 100, wherein this routing connects and refers to that 110 is crystal bonding area territories 103 that are adjacent to this substrate 100, wherein this first wafer 10 is that to be attached at these crystal bonding area territory 103, the second wafers 20 be to be stacked on this first wafer 10.Please consult shown in Figure 1ly again, these routings connect and refer to that 110 is to be revealed in the insulating barrier 130 that this substrate 100 is formed at this inner surface 101, for routing.One outer surface 102 of this substrate 100 is to be formed with a plurality of outer connection gaskets 140.This first wafer 10 is to have a plurality of first weld pads 11.Utilize first bonding wire 31 to electrically connect these first weld pads 11 and connect finger 110 with corresponding routing.One sept 12 is to be arranged between this first wafer 10 and this second wafer 20.This second wafer 20 is to have a plurality of second weld pads 21, and can utilize this second weld pad 21 of second bonding wire, 32 electric connections to connect finger 110 with this routing.So connecing, the routing of same signal or common source/ground connection refers to that 110 is to engage one first bonding wire 31 and one second bonding wire 32 (as shown in Figure 2) simultaneously.
Existing known multi-chip stacking and packaging construction, for example memory card can comprise an adhesive body 40 in addition, and it is this first wafer 10 and this second wafer 20 of sealing.Because in the encapsulation procedure, the bonding wire idol of wafer itself or its connection has bad generation, when the wafer of learning one of them or part after the packaging and testing can't normal operation, owing to being sealed by adhesive body on the wafer that can't operate and electrically conducting with substrate, cause all the other good wafers can't normal operation, must whole semiconductor product be abandoned along with the wafer of damage, and cause scrappage to improve.
At above-mentioned problem, several solutions are arranged at present, the one, at crystal circle grade all wafers is carried out complete electrical functionality test, to record known good dies (KGD), this testing cost is quite high, does not meet in a large number manufacturing mode cheaply.Another is to repair in encapsulation procedure, can be with reference to No. the 409330th, TaiWan, China patent announcement " can repair the encapsulation of formula polycrystalline sheet module ", at the glutinous crystalline substance of lower chip and in electrically connecting and before sealing, carry out testing in the processing procedure, when recording bad lower chip, remove the bonding wire that connects lower chip, attach one with stack manner again and substitute wafer.This method needs sealing Pretesting and the engineering of removing bad bonding wire, and the quality after the sealing still belongs to uncertain and has extra processing procedure restriction.In addition, its stack manner be good wafer stacking on bad wafer, the non-multi-chip stacking and packaging construction that is exclusively used in.
This shows that the substrate that above-mentioned existing polycrystalline sheet piles up obviously still has inconvenience and defective, and demands urgently further being improved in structure and use.In order to solve the problem of above-mentioned existence, relevant manufacturer there's no one who doesn't or isn't seeks solution painstakingly, but do not see always that for a long time suitable design finished by development, and common product does not have appropriate structure to address the above problem, this obviously is the problem that the anxious desire of relevant dealer solves.Therefore how to found the substrate that a kind of novel polycrystalline sheet piles up, the multi-chip stacking and packaging construction that uses this substrate, real one of the current important research and development problem that belongs to, also becoming the current industry utmost point needs improved target.
Because the defective that the substrate that above-mentioned existing polycrystalline sheet piles up exists, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, substrate, the multi-chip stacking and packaging construction that uses this substrate and the application thereof of piling up in the hope of the polycrystalline sheet of founding a kind of new structure, can improve the substrate that general existing polycrystalline sheet piles up, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, overcome the defective that substrate that existing polycrystalline sheet piles up exists, and the substrate, the multi-chip stacking and packaging construction that uses this substrate and the application thereof that provide a kind of novel polycrystalline sheet to pile up, technical problem to be solved is that a plurality of wafers can be stacked in the packaging structure, utilization has the design of the loop circuit of fuse, the a plurality of wafers in feasible test back separate independently working and do not interfere with each other, thereby are suitable for practicality more.
Another object of the present invention is to, the substrate, the multi-chip stacking and packaging construction that uses this substrate and the application thereof that provide a kind of novel polycrystalline sheet to pile up, technical problem to be solved is to make it can carry out fuse opening after sealing, reach and exempt from the effect that seal line is repaired, thereby be suitable for practicality more.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to the present invention, the substrate that a kind of polycrystalline sheet piles up comprises at least that one first routing connects finger, one second routing connects finger, a trace and a loop circuit.This first routing connects to refer to it is to be adjacent to a crystal bonding area territory.This second routing connects to refer to it is to be adjacent to this crystal bonding area territory.This trace is the transmission of power supply property.This loop circuit is that this first routing of serial connection connects finger and this second routing connects finger and is connected to this trace, this loop circuit is to be provided with one first fuse, one second fuse and one the 3rd fuse, wherein this first fuse is to be serially connected with this first routing to connect between finger and this trace, this second fuse is to be serially connected with this first routing to connect and refer to connect between the finger with this second routing, and the 3rd fuse is to be serially connected with this second routing to connect between finger and this trace.In addition, the present invention discloses a multi-chip stacking and packaging construction and the application thereof of using this substrate in addition.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In aforesaid substrate, arbitrary live width of this first fuse, this second fuse and the 3rd fuse is can be less than the live width of this loop circuit.
In aforesaid substrate, can include an insulating barrier in addition, it is to have plurality of openings, it is aligning and appears this first fuse, this second fuse and the 3rd fuse.
In aforesaid substrate, this insulating barrier can be a core layer, so that this first fuse, this second fuse and the 3rd fuse are revealed in an outer surface of this substrate.
In aforesaid substrate, this insulating barrier can be a welding resisting layer, so that this first fuse, this second fuse and the 3rd fuse are revealed in an inner surface of this substrate.
In aforesaid substrate, this first routing connects finger, this second routing, and to connect finger, this trace and this loop circuit be an inner surface that can be formed at this substrate, and other includes an outer connection gasket, and it is an outer surface that is formed at this substrate.
In aforesaid substrate, the shape of this loop circuit is generally to be the edge of polygon or circular arc.
In aforesaid substrate, can include one the 3rd routing in addition and connect finger, it is connected in series by this loop circuit.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of multi-chip stacking and packaging construction according to the present invention proposes comprises: a substrate, and one first wafer, and one second wafer, wherein this substrate comprises: one first routing connects finger, and it is to be adjacent to a crystal bonding area territory; One second routing connects finger, and it is to be adjacent to this crystal bonding area territory; One trace is for electrical transmission; An and loop circuit, it is that this first routing of serial connection connects finger and this second routing connects finger and is connected to this trace, the loop circuit is to be provided with one first fuse, one second fuse and one the 3rd fuse, wherein this first fuse is to be serially connected with this first routing to connect between finger and this trace, this second fuse is to be serially connected with this first routing to connect and refer to connect between the finger with this second routing, and the 3rd fuse is to be serially connected with this second routing to connect between finger and this trace; This first wafer, it is to be arranged at this crystal bonding area territory of this substrate and to be electrically connected to this first routing to connect finger; This second wafer, it is to be stacked on this first wafer and to be electrically connected to this second routing to connect finger.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In aforesaid multi-chip stacking and packaging construction, other includes a controller wafer, its be with this trace for electrically connecting, and this first wafer and this second wafer be memory chip, to form a memory card.
In aforesaid multi-chip stacking and packaging construction, wherein this substrate includes an insulating barrier in addition, and it is to have plurality of openings, and it is aligning and appears this first fuse, this second fuse and the 3rd fuse.
In aforesaid multi-chip stacking and packaging construction, other includes a dielectricity filling perforation material, and it is to be filled in these perforates.
Via as can be known above-mentioned, the present invention mainly discloses a kind of polycrystalline sheet substrate that piles up and the multi-chip stacking and packaging construction that uses this substrate.This substrate comprises one first routing at least and connects a trace and the loop circuit that finger, one second routing connect finger, a power supply property transmission.This first routing connects and refers to that connecing finger with this second routing all is a crystal bonding area territory that is adjacent to this substrate.This loop circuit is that this first routing of serial connection connects finger and this second routing connects finger and is connected to this trace.Therefore, a plurality of wafers can pile up to be arranged at this crystal bonding area territory and to be electrically connected to these routings and connect finger, and each wafer can separate independently working and not interfere with each other.In addition, use the multi-chip stacking and packaging construction of this substrate can after sealing, exempt from the repairing work of seal line.
By technique scheme, the substrate that polycrystalline sheet of the present invention piles up, the multi-chip stacking and packaging construction that uses this substrate and application thereof have following advantage at least:
One, a plurality of wafers can be stacked in the packaging structure, utilize the design of the loop circuit with fuse, and a plurality of wafers in feasible test back separate independently working and do not interfere with each other.
Two, can after sealing, carry out fuse opening, reach and exempt from the effect that seal line is repaired
In sum, the substrate that the polycrystalline sheet of novelty of the present invention piles up, the multi-chip stacking and packaging construction that uses this substrate and application thereof have above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, be a significant progress in technology, and produced handy and practical effect, and the substrate that more existing polycrystalline sheet piles up has the multinomial outstanding effect of enhancement, thereby be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1: the substrate that a kind of existing known polycrystalline sheet piles up is applied to the schematic cross-section of a multi-chip stacking and packaging construction.
Fig. 2: the existing sectional perspective schematic diagram of known this substrate behind routing.
Fig. 3: according to first specific embodiment of the present invention, the substrate that a kind of polycrystalline sheet piles up is applied to the schematic cross-section of a multi-chip stacking and packaging construction.
Fig. 4: according to first specific embodiment of the present invention, the sectional perspective schematic diagram of this substrate behind routing.
Fig. 5: according to first specific embodiment of the present invention, illustrate this substrate and various test status as a result the time a plurality of fuse-switch states contrast figure.
Fig. 6: according to first specific embodiment of the present invention, the schematic partial cross-sectional view of this substrate.
Fig. 7 A to 7D:, illustrate the schematic diagram of the formation breaking method of this substrate after the routing sealing according to first specific embodiment of the present invention.
Fig. 8: according to second specific embodiment of the present invention, the schematic partial cross-sectional view of another kind of substrate.
Fig. 9 A to 9C:, illustrate the schematic diagram of this substrate formation breaking method before the sealing behind routing according to second specific embodiment of the present invention.
Figure 10: according to the 3rd specific embodiment of the present invention, the local inner surface schematic diagram of another kind of substrate behind routing.
11: the first weld pads of 10: the first wafers
12: 20: the second wafers of sept
31: the first bonding wires of 21: the second weld pads
Bonding wire 40 in 32: the second: adhesive body
50,50 ': the first wafer, 51,51 ': first weld pad
52: sept 60,60 ': second wafer
61,61 ': the second weld pad, 71,71 ': first bonding wire
72,72 ': the second bonding wire 80: adhesive body
90,90 ': laser 100: substrate
101: inner surface 102: outer surface
103: crystal bonding area territory 110: routing connects finger
120: trace 130: insulating barrier
140: outer connection gasket 200: substrate
201: inner surface 202: outer surface
203: 211: the first routings in crystal bonding area territory connect finger
212: the second routings connect and refer to 220: trace
230: loop circuit 240: insulating barrier
241: perforate 250: outer connection gasket
260: welding resisting layer 270: dielectricity filling perforation material
300: substrate 301: inner surface
302: 311: the first routings of outer surface connect finger
312: the second routings connect and refer to 320: trace
330: loop circuit 340: insulating barrier
341: perforate 350: outer connection gasket
360: fuse 401: inner surface
403: 411: the first routings in crystal bonding area territory connect finger
412: the second routings connect and refer to that 413: the three routings connect finger
420: trace 430: the loop circuit
F1: the first fuse F2: second fuse
F3: the 3rd fuse F4: the 4th fuse
F5: the 5th fuse
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, the substrate that the polycrystalline sheet that foundation the present invention is proposed piles up, use the multi-chip stacking and packaging construction of this substrate and use its embodiment, structure, feature and effect thereof, describe in detail as after.
According to a specific embodiment of the present invention, disclose a kind of polycrystalline sheet stacking substrates.Fig. 3 is applied to the schematic cross-section of a multi-chip stacking and packaging construction for this substrate.Fig. 4 is the sectional perspective schematic diagram of this substrate behind routing.Fig. 5 be illustrate this substrate and various test status as a result the time a plurality of fuse-switch states contrast figure.Fig. 6 is the schematic partial cross-sectional view of this substrate.
See also Fig. 3 and shown in Figure 4, this substrate 200 comprises a plurality of cohorts at least, and each cohort comprises one first routing and connects and refer to that 211,1 second routing connects and refer to 212, one trace 220 and a loop circuit 230.This substrate 200 is to have an inner surface 201 and an outer surface 202, and this inner surface 201 is that definition has a crystal bonding area territory 203, for the wafer that plurality of stacks is set.Wherein, this first routing connects and refers to that 211 connect with this second routing and to refer to that 212 all is to be adjacent to this crystal bonding area territory 203, and is formed at this inner surface 201 of this substrate 200.See also shown in Figure 4ly, this trace 220 is these inner surfaces 201 that are formed at this substrate 200, for electrical transmission.In the present embodiment, this substrate 200 includes an outer connection gasket 250 in addition, and it is this outer surface 202 that is formed at this substrate 200.Should outer connection gasket 250 be to can be strip contact finger (gold fingers), to be applicable to the semiconductor product of memory card.
Please consult shown in Figure 4ly again, this loop circuit 230 is that this first routing of serial connection connects and refers to that 211 connect with this second routing and to refer to 212 and be connected to this trace 220, this first routing is connect refer to 211 to connect with this second routing and to refer to that 212 all can be electrically connected to this trace 220.In the present embodiment, this loop circuit 230 is these inner surfaces 201 that can be formed at this substrate 200.The shape of this loop circuit 230 is generally to be the edge of polygon or circular arc.Please consult shown in Figure 4 again, this loop circuit 230 is to be provided with one first fuse F1, one second fuse F2 and one the 3rd fuse F3, wherein this first fuse F1 is serially connected with this first routing to connect between finger 211 and this trace 220, this second fuse F2 is serially connected with this first routing to connect and refer to that 211 connect between the finger 212 with this second routing, the 3rd fuse F3 is serially connected with this second routing to connect between finger 212 and this trace 220, and property opens circuit for you to choose.Preferably, this first routing connect refer to 211 with this second routing connect refer to 212 between apart from configurable single the second fuse F2 only refer to that 211 connect finger 212 with this second routing and can arrange comparatively closely so that this first routing connects.Usually arbitrary live width of this first fuse F1, this second fuse F2 and the 3rd fuse F3 is can be blown with formation by a laser 90 selectivity and open circuit less than the live width of this loop circuit 230.In the present embodiment, this first fuse F1, this second fuse F2 are can be identical with this loop circuit 230 with the material of the 3rd fuse F3, as copper, or can be the metal of tungsten filament or other fusible.
According to first specific embodiment of the present invention, this substrate 200 can further be applied to a multi-chip stacking and packaging construction, the particularly miniature digital card (Micro SD card) of saving from damage.See also shown in Figure 3ly, a kind of multi-chip stacking and packaging construction comprises this substrate 200, one first wafer 50 and one second wafer 60 at least.This first wafer 50 is these crystal bonding area territories 203 that are arranged at this substrate 200, this first wafer 50 is to have a plurality of first weld pads 51, and can utilize traditional routing technology, first weld pad 51 and first routing that electrically connect correspondence with one first bonding wire 71 connect finger 211.This second wafer 60 is to be stacked on this first wafer 50, and this second wafer 60 is to have a plurality of second weld pads 61, and can utilize traditional routing technology, and second weld pad 61 and second routing that electrically connect correspondence with one second bonding wire 72 connect finger 212.Particularly, this multi-chip stacking and packaging construction can comprise a sept 52 in addition, and it is to be situated between to be located between first wafer 50 and second wafer 60, so that the back side of this second wafer 60 does not direct contact to this first wafer 50 and first bonding wire 71.
Please consult shown in Figure 3ly again, utilizing an adhesive body 80 is these inner surfaces 201 that are formed at this substrate 200, to seal this first wafer 50, this second wafer 60, this first bonding wire 71 and this second bonding wire 72.
Particularly, this substrate 200 can comprise a welding resisting layer 260 in addition, and it is this inner surface 201 that is formed at this substrate 200, covers the line layer of this substrate 200 and appear this first routing with the part to connect and refer to that 211 connect with this second routing and to refer to 212, for routing.
In the present embodiment, this multi-chip stacking and packaging construction can include a controller wafer in addition, and it is to be electric connection with this trace 220.For example, this first wafer 50 can be memory chip with this second wafer 60, to form a memory card.
Because employed each wafer quality and situation are neither identical, so test status is not that each wafer is all non-defective unit, therefore this first fuse F1, this second fuse F2 that need blow should do corresponding opening circuit as shown in Figure 5 with the 3rd fuse F3 and adjust variation, but make another good wafer normal operation, can after sealing is finished, carry out testing electrical property and repairing work.
See also Fig. 4 and shown in Figure 5, the test status that when test result is one first wafer 50 and one second wafer 60 then need not to blow this first fuse F1, this second fuse F2 and the 3rd fuse F3 for all good.
Please consult Fig. 4 and shown in Figure 5 again, when test result is these first wafer, 50 faults, should blow this first fuse F1 and this second fuse F2, the routing of winning be connect refer to 211 for being electrically insulated from this trace 220, so first wafer 50 that lower floor piles up will be electrically insulated from the internal wiring of this substrate 200.Therefore, but can avoid first wafer 50 of fault to disturb second wafer 60 of normal operations.Wherein, second bonding wire 72 that connects this second wafer 60 can not need to remove or break.
Please consult Fig. 4 and shown in Figure 5 again, when another test result is these second wafer, 60 faults, should blow this second fuse F2 and the 3rd fuse F3, make second routing connect and refer to 212 for being electrically insulated from this trace 220, so second wafer 60 that pile up on the upper strata will be electrically insulated from the internal wiring of this substrate 200.Therefore, but can avoid second wafer 60 of fault to disturb first wafer 50 of normal operations.Wherein, first bonding wire 71 that connects this first wafer 50 can not need to remove or break.
Therefore, utilize alternative formation of this first fuse F1, this second fuse F2 and the 3rd fuse F3 to open circuit, make this first wafer 50 and this second wafer 60 separate independently working and do not interfere with each other.That is to say,, only need to connect the fuse opening that the routing that damages connects finger, routing is connect refer to be the structure that opens circuit, can make all the other good wafer normal operations even one or wafer damage are partly arranged in the multi-chip stacking and packaging construction, and then the reduction manufacturing cost.In addition, the step that formation is opened circuit to fuse selection can also can have the convenience on the processing procedure after sealing after glutinous crystalline substance.
See also shown in Figure 6, this substrate 200 can include an insulating barrier 240 in addition, it is to have plurality of openings 241, it is aligning and appears this first fuse F1, this second fuse F2 and the 3rd fuse F3, interrupts this first fuse F1, this second fuse F2 or the 3rd fuse F3 for laser 90 selectivity.Preferably, this insulating barrier 240 can be a core layer, so that this first fuse F1, this second fuse F2 and the 3rd fuse F3 are revealed in this outer surface 202 of this substrate 200.After routing and sealing, still can interrupt this first fuse F1, this second fuse F2 or the 3rd fuse F3, open circuit with formation with laser 90.In the present embodiment, can utilize a dielectricity filling perforation material 270 to be filled in these perforates 241.
Fig. 7 A to Fig. 7 D is the schematic diagram of the formation breaking method of this substrate 200 after the routing sealing.At first, see also shown in Fig. 7 A, routing sealing and multi-chip stacking and packaging construction are after tested placed on the platform, and this outer surface 202 that makes this substrate 200 is towards a laser beam emitting device.Then, see also shown in Fig. 7 B, find out these fuses F1, the F2 or the F3 that connect the damage wafer.See also shown in Fig. 7 C,,, open circuit with formation so can utilize a laser 90 that this second fuse F2 is blown because these perforates 241 of this insulating barrier 240 are to appear this second fuse F2.At last, see also shown in Fig. 7 D, can utilize substrate filling perforation technology that this dielectricity filling perforation material 270 is filled in these perforates 241, expose to avoid these fuses F1, F2 or F3.
In second specific embodiment, disclose the substrate that another kind of polycrystalline sheet piles up.See also shown in Figure 8ly, this substrate 300 comprises one first routing at least and connects and refer to that 311,1 second routing connects and refer to 312, one trace 320 and a loop circuit 330.In the present embodiment, this first routing connect refer to 311, this second routing connect refer to 312, this trace 320 is inner surfaces 301 that can be formed at this substrate 300 with this loop circuit 330.This substrate 300 can include an outer connection gasket 350 in addition, and it is an outer surface 302 that is formed at this substrate 300.Wherein, this first routing connects and refers to that 311 connect with this second routing and to refer to that 312 all is to be adjacent to the crystal bonding area territory that can pile up a plurality of wafers 50 ' and 60 '.This trace 320 is the transmission of power supply property.This loop circuit 330 is that this first routing of serial connection connects finger 311 and this second routing connects finger 312 and is connected to this trace 320.Please consult shown in Figure 8ly again, this loop circuit 330 is to be provided with at least one fuse 360, its be this first routing of serial connection connect refer to 311, this second routing connect refer to 312 and this trace 320 between, property opens circuit for you to choose.
Particularly, this substrate 300 can include an insulating barrier 340 in addition, and it is to have plurality of openings 341, and it is aligning and appears this fuse 360, interrupts this fuse 360 in order to laser.In the present embodiment, this insulating barrier 340 can be a welding resisting layer, so that this fuse 360 is revealed in this inner surface 301 of this substrate 300, carries out selectivity before and opens circuit so be applicable to sealing.
Fig. 9 A to Fig. 9 D is the schematic diagram of this substrate 300 formation breaking method before the sealing behind routing.At first, see also shown in Fig. 9 A, one first wafer 50 ' is the inner surface 301 that is arranged at this substrate 300, at least one second wafer 60 ' is the top that is stacked on this first wafer 50 ', first weld pad 51 ' to first routing that a plurality of first bonding wires 71 ' electrically connect first wafer 50 ' connects and refers to 311, and second weld pad 61 ' to second routing that a plurality of second bonding wires 72 ' electrically connect second wafer 60 ' connects and refers to 312.Above-mentioned not sealing and multi-chip stacking and packaging construction are after tested placed on the platform, and this inner surface 301 that makes this substrate 300 is towards a laser beam emitting device, to appear this fuse 360.Then, see also shown in Fig. 9 B, utilize a laser 90 ' to connect to have recorded damage wafer connect finger around fuse 360 blow.At last, see also shown in Fig. 9 C, this fuse 360 is formed open circuit, damage the internal wiring that wafer is electrically insulated from this substrate 300 so that recorded.Therefore, utilize alternative formation of fuse 360 to open circuit, make the wafer of this plurality of stacks separate independently working and do not interfere with each other.
In the 3rd specific embodiment, disclose the substrate that another kind of polycrystalline sheet piles up.See also shown in Figure 10ly, this substrate comprises one first routing at least and connects and refer to that 411,1 second routing connects and refer to 412, one trace 420 and a loop circuit 430.Wherein, this first routing connects and refers to that 411 connect with this second routing and to refer to that 412 all is to be adjacent to a crystal bonding area territory 403.This trace 420 is the transmission of power supply property.This loop circuit 430 is that this first routing of serial connection connects finger 411 and this second routing connects finger 412 and is connected to this trace 420.In the present embodiment, this substrate can include one the 3rd routing in addition and connect finger 413, connects one the 3rd wafer for routing.The 3rd routing connects and refers to that 413 is to be adjacent to this crystal bonding area territory 403 and to be connected in series by this loop circuit 430.Wherein this first routing connects finger 411, this second routing connects and refers to that the 412, the 3rd routing connects finger 413, this trace 420 is inner surfaces 401 that can be formed at this substrate with this loop circuit 430.
Please consult shown in Figure 10 again, this loop circuit 430 is to be provided with one first fuse F1, one second fuse F2, one the 3rd fuse F3, one the 4th fuse F4 and one the 5th fuse F5, wherein this first fuse F1 is serially connected with this first routing to connect between finger 411 and this trace 420, this second fuse F2 is serially connected with this first routing to connect and refer to that 411 connect between the finger 412 with this second routing, the 3rd fuse F3 is serially connected with this second routing to connect between finger 412 and this trace 420, the 4th fuse F4 is serially connected with this second routing to connect and refer to that the 412 and the 3rd routing connects between the finger 413, the 5th fuse F5 is serially connected with the 3rd routing to connect between finger 413 and this trace 420, property formation is opened circuit for you to choose, have at many (three) wafer stacking and after this substrate, can exempt from the effect that seal line is repaired, it repairs flow process is can be in encapsulation procedure or after product makes, and has elasticity and convenience in the manufacturing.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (8)
1, the substrate that piles up of a kind of polycrystalline sheet is characterized in that it comprises:
One first routing connects finger, and it is to be adjacent to a crystal bonding area territory;
One second routing connects finger, and it is to be adjacent to this crystal bonding area territory;
One trace is for electrical transmission; And
One loop circuit, it is that this first routing of serial connection connects finger and this second routing connects finger and is connected to this trace, this loop circuit is to be provided with one first fuse, one second fuse and one the 3rd fuse, wherein this first fuse is to be serially connected with this first routing to connect between finger and this trace, this second fuse is to be serially connected with this first routing to connect and refer to connect between the finger with this second routing, and the 3rd fuse is to be serially connected with this second routing to connect between finger and this trace.
2, substrate according to claim 1 is characterized in that it includes an insulating barrier in addition, and it is to have plurality of openings, and it is aligning and appears this first fuse, this second fuse and the 3rd fuse.
3, substrate according to claim 1, it is characterized in that connecing finger, this second routing by wherein said first routing, to connect finger, this trace and this loop circuit be an inner surface that is formed at this substrate, other includes an outer connection gasket, and it is an outer surface that is formed at this substrate.
4, substrate according to claim 1 is characterized in that it includes one the 3rd routing in addition and connects finger, and it is connected in series by this loop circuit.
5, a kind of multi-chip stacking and packaging construction is characterized in that it comprises:
One substrate, it is to comprise:
One first routing connects finger, and it is to be adjacent to a crystal bonding area territory;
One second routing connects finger, and it is to be adjacent to this crystal bonding area territory;
One trace is for electrical transmission; And
One loop circuit, it is that this first routing of serial connection connects finger and this second routing connects finger and is connected to this trace, the loop circuit is to be provided with one first fuse, one second fuse and one the 3rd fuse, wherein this first fuse is to be serially connected with this first routing to connect between finger and this trace, this second fuse is to be serially connected with this first routing to connect and refer to connect between the finger with this second routing, and the 3rd fuse is to be serially connected with this second routing to connect between finger and this trace;
One first wafer, it is to be arranged at this crystal bonding area territory of this substrate and to be electrically connected to this first routing to connect finger; And
One second wafer, it is to be stacked on this first wafer and to be electrically connected to this second routing to connect finger.
6, multi-chip stacking and packaging construction according to claim 5 is characterized in that it includes a controller wafer in addition, its be with this trace for electrically connecting, and this first wafer and this second wafer be memory chip, to form a memory card.
7, multi-chip stacking and packaging construction according to claim 5 is characterized in that wherein said substrate includes an insulating barrier in addition, and it is to have plurality of openings, and it is aligning and appears this first fuse, this second fuse and the 3rd fuse.
8, multi-chip stacking and packaging construction according to claim 7 is characterized in that it includes a dielectricity filling perforation material in addition, and it is to be filled in above-mentioned perforate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710003471.8A CN100530629C (en) | 2007-02-05 | 2007-02-05 | Multi-wafer piling base plate and multi-wafer piling encapsulation structure based on this base plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710003471.8A CN100530629C (en) | 2007-02-05 | 2007-02-05 | Multi-wafer piling base plate and multi-wafer piling encapsulation structure based on this base plate |
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| Publication Number | Publication Date |
|---|---|
| CN101241892A CN101241892A (en) | 2008-08-13 |
| CN100530629C true CN100530629C (en) | 2009-08-19 |
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| CN200710003471.8A Expired - Fee Related CN100530629C (en) | 2007-02-05 | 2007-02-05 | Multi-wafer piling base plate and multi-wafer piling encapsulation structure based on this base plate |
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| CN (1) | CN100530629C (en) |
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| US8643169B2 (en) * | 2011-11-09 | 2014-02-04 | Freescale Semiconductor, Inc. | Semiconductor sensor device with over-molded lid |
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