CN100527749C - Bus interface and method for implementing sequential adaptive of bus interface - Google Patents

Abstract

This invention discloses a method realizing busbar interface time order self-adaptation. This method is: delay the delaying clock of the same frequency get by the upward clock; sample the busbar by using the upward side and the down side of the up and delay clocks to get four sampling values in each cycle of the up clock; judge whether the back three values of the sampling are the same; if the judgment is 'YES', ensure that the opposite touching edge applied to the present operational up clock touching edge to reliably sample the upward busbar and switch the opposite touching edge to the operational touching edge, otherwise not change the operational touching edge. This invention also discloses a busbar interface.

Description

The method of a kind of bus interface and realization bus interface time sequential adaptive

Technical field

The present invention relates to the switch technology of the communications field, relate in particular to the method for a kind of bus interface and realization bus interface time sequential adaptive.

Background technology

Bus (HW) is a kind of Time Division Multiplexing serial-port, in order to business such as carrying pcm stream, signalings, is mainly used in the digital SPC exchange intercommunication.The HW that several speed such as 2.048M, 8.192M, 16.384M, 32.768M are arranged usually.

One road HW passage comprises up HW, descending HW and corresponding synchronised clock and frame synchronization clock at least.HW with 2.048M is an example, comprises that speed is up HW and the descending HW of 2.048M, and the frame synchronization clock of the synchronised clock of 2.048M and 8K, and the HW of 2.048M is divided into 32 time slots, and each time slot is the time-derived channel of a 64Kbps.

The reception of HW and transmission need be satisfied certain time sequence relation ability operate as normal, and each concrete application all has corresponding sequential relationship.Fig. 1 is the 16M HW sequential illustration of a veneer, and wherein " input 16M " is clock signal, and " incoming frame signal " is the 8K frame synchronizing signal, and DHW is descending HW, and UHW is up HW.

When carrying out the HW butt joint, need design sequential, only need design a kind of fixing sequential just can satisfy a kind of concrete application generally speaking.But under some situation, require one of butt joint to reach and revise sequential neatly so that use and different veneer or systems, the functional test equipment (FT) that typical example is exactly the switch veneer, the functional test equipment is used for production test, finishes large batch of product function checking.

Because the switch veneer is of a great variety, the HW complex time is various, and the HW that so just requires test equipment to provide can adapt to multiple sequential requirement, and common way is at different single board design different HW sequence circuit or logic.

As shown in Figure 2, by logic synchronously, processing such as time-delay, the HW sequential can be adjusted to required sequential requirement.But the shortcoming of this method is at different docking systems, need the different logic of design, can't be by simple method (such as software control) real time altering sequential adjustment logic, cannot shelfization, cause overlapping development, make that linearity increases development cost along with increasing of quantity of exploitation.

Summary of the invention

The object of the present invention is to provide the method for a kind of bus interface and realization bus interface time sequential adaptive, make bus interface carry out the sequential adjustment in real time according to different docking systems.

Realize technical scheme of the present invention:

A kind of method that realizes the bus interface time sequential adaptive, described bus interface comprises up bus and last row clock at least for the interface of the time division multiplexing serial-port of carrying impulse coding modulation code stream and signaling traffic; This method is:

The described upward row clock of delaying time obtains the time-delay clock of same frequency;

Utilize described rising edge and the trailing edge of going up row clock and time-delay clock that up bus is sampled, in each clock cycle of last row clock, to obtain four sampled values;

Judge in described four sampled values that back three sampled values are whether entirely for " 0 " or be " 1 " entirely;

If judged result is a "Yes", opposite triggerings that the last row clock of then confirming to be used for current operation triggers the edge be along can the up bus of reliable samples, and will be somebody's turn to do on the contrary that the triggering edge switches to the triggering edge that is used to move, otherwise do not change the triggering edge that is used to move.

According to said method:

Four sampled values that obtain in each clock cycle with last row clock are stored in the register, and read back three sampled values from this register and judge.

The rising edge or the trailing edge of row clock judged described back three sampled values on described.

Described bus interface is the bus interface of 2M, 8M, 16M or 32M speed.

A kind of bus interface, this bus interface is the interface of the time division multiplexing serial-port of carrying impulse coding modulation code stream and signaling traffic, this bus interface comprises: the up receiver module that is used to handle upstream data, be used to handle the descending receiver module of downlink data, and the controller that is used to control up receiver module and descending receiver module; Described up receiver module comprises up bus, the reception shift register that receives up bus data and the reception read-write controller that this register is controlled at least; Wherein, described up receiver module also comprises with up bus, receives read-write controller, receives the sampling edge adjusting module that shift register is connected with controller, this sampling edge adjusting module be used to accept controller configuration, up bus is sampled, is adjusted up bus sampling edge and control reception read-write controller and reception shift register according to sampled value;

Described up bus sampled, adjusted up bus sampling edge according to sampled value, comprising:

Row clock obtains the time-delay clock of same frequency in the time-delay; Utilize described rising edge and the trailing edge of going up row clock and time-delay clock that up bus is sampled, in each clock cycle of last row clock, to obtain four sampled values; Judge in described four sampled values that back three sampled values are whether entirely for " 0 " or be " 1 " entirely; If judged result is a "Yes", opposite triggerings that the last row clock of then confirming to be used for current operation triggers the edge be along can the up bus of reliable samples, and will be somebody's turn to do on the contrary that the triggering edge switches to the triggering edge that is used to move, otherwise do not change the triggering edge that is used to move.

Described sampling edge adjusting module comprises:

Delayer is connected with last row clock, up clock delay is generated the time-delay clock of same frequency;

Sample register is connected the sampled value of storing up bus at the rising edge and the trailing edge of two clocks with last row clock, time-delay clock with up bus;

Edge judgement and selector are connected with sample register with last row clock, are used under the driving of last row clock control signal is adjudicated and exported to sampled value, to adjust up bus sampling edge.

Software is configurable, the characteristics of self adaptation reliable samples owing to having possessed for the self adaptation bus interface logic that the present invention realizes, go for needing to adjust or dynamically adjust the application scenario of bus sequential, avoid overlapping development, can reduce cost widely, had more wide application prospect.

Description of drawings

Fig. 1 is a veneer 16M bus sequential chart;

Fig. 2 adjusts schematic diagram for the bus fixed time sequence;

Fig. 3 is a 16M bus interface logic diagram of the present invention;

Fig. 4 is for receiving the shift register fundamental diagram;

Fig. 5 is the structure chart of sampling edge adjusting module;

The schematic diagram that Fig. 6 meets the demands for the rising edge sampling;

The schematic diagram that Fig. 7 does not meet the demands for the rising edge sampling.

Embodiment

Present embodiment is that example describes with 16M bus (HW) interface.

Consult shown in Figure 3ly, 16M HW interface logic mainly is made up of up receiver module, descending sending module and three parts of controller.The sampling edge self-adjusting module in up receiver module, up receiver module and descending sending module two large divisions's realization principle is basic identical, all comprise receiving shift register, two-port RAM, three links of transmission shift register, and read and write control, parameter register, three work of clock processing control modules.

The length that receives shift register is 16, and the principle of employing " sliding window " realizes the reception bit synchronization adjustment of up bus (UHW) or Down-link HighWay (DHW) data, consults shown in Figure 4.On each effective edge of 16M clock (selecting the output of parameter or sampling edge self-adjusting module to determine by edge and polarity), UHW or DHW data are sampled, in the sampled value serial immigration register.On each effective edge of 2M clock (obtaining) (determining for the 0th by edge and polarity mask register) from external world's input or by the local clock frequency division, a byte sampled value in the reception shift register is by parallel read-out, and the output decision of address generating module is read in the position of byte by shift register.

Two-port RAM is a toroidal memory that reading-writing port is separated, and its length is 6 bytes, is used for the slot synchronization adjustment of HW Data Receiving.On each effective edge of 2M clock, the data of a time slot are written in the memory, and the data of another time slot are read out simultaneously.After having write at every turn or run through 6 data, write pointer or read pointer will turn back to the start element of memory again.The write pointer of memory and read pointer provide by receiving the read-write control module.

Send shift register, length is 8, is used for the transmission of HW data.It receives time slot data that come from two-port RAM, and on each effective edge of 16M clock each data bit serial is sent.

Receive the read-write control module, produce the various work that receive shift register, dual port RAM, transmission shift register according to the content of parameter register and enable control signal, every address and write address read.

Parameter register is preserved the HW reception and is sent each parameter of using, and its read-write control signal is produced by controller.

Controller is totally controlled the work of each module in the logic; Receive the various parameters that are provided with by interface, and be saved in two parameter register groups with CPU.

Sampling edge adjusting module uses the 16M clock that UHW is sampled, and realizes the self-adjusting of UHW sampled edge then by certain criterion, and the operation principle of this module is referring to Fig. 5.

In order to realize four samplings, another 16M time-delay clock will be generated behind the 16M clock delay 11ns to each data of UHW.Jump edge and trailing edge on each of two 16M clocks, each data bit of UHW is by four samplings (4 sampled points of mark in the instance graph 6), and sampled value is kept in the register of 4 bit lengths in proper order.The edge judgement is analyzed with back three sampled values (sampled value of the 2nd, 3,4 sampled point in the instance graph 6) that selector reads in the sample register.If these three sampled values equate (be entirely ' 0 ' or complete be ' 1 ') illustrate that current triggerings is unreliable along sampling, triggering edge can reliable samples on the contrary for it; If be not ' 0 ' or ' 1 ' entirely, illustrate that current triggering is along the energy reliable samples.Rising edge and trailing edge to input 16M clock are adjudicated respectively, the court verdict under the normal condition should be both one of can reliable samples, another can not reliable samples.Selection result output according to the object module of adjudicating is set or zero clearing, represents whether current sampling is reliable.If current triggering is along can not reliable samples, logic will automatically switch to opposite triggering edge so, guarantee reliable samples.

Fig. 6 is the example that a rising edge satisfies sampling request, if 2,3,4 sampled value does not wait, the saltus step that HW is described occurs between the 2nd and the 4th sampled point, therefore the distance between first sampled point and the HW trip point is more than or equal to 1/4 clock cycle, guaranteed reliable samples, and Fig. 7 is an example that does not meet the demands, and first sampled point has just in time dropped near the HW trip point, in HW trip point ± 1/4 periodic regime.Therefore, can guarantee that by this adaptive logic sampled point guarantees the allowance greater than 1/4 clock cycle at least, thereby realize the reliable samples of HW.

Claims (6)

1, a kind of method that realizes the bus interface time sequential adaptive, described bus interface comprises up bus and last row clock at least for the interface of the time division multiplexing serial-port of carrying impulse coding modulation code stream and signaling traffic; It is characterized in that this method is:

The described upward row clock of delaying time obtains the time-delay clock of same frequency;

Utilize described rising edge and the trailing edge of going up row clock and time-delay clock that up bus is sampled, in each clock cycle of last row clock, to obtain four sampled values;

Judge in described four sampled values that back three sampled values are whether entirely for " 0 " or be " 1 " entirely;

If judged result is a "Yes", opposite triggerings that the last row clock of then confirming to be used for current operation triggers the edge be along can the up bus of reliable samples, and will be somebody's turn to do on the contrary that the triggering edge switches to the triggering edge that is used to move, otherwise do not change the triggering edge that is used to move.

2, the method for claim 1 is characterized in that, four sampled values that obtain in each clock cycle with last row clock are stored in the register, and reads back three sampled values from this register and judge.

3, method as claimed in claim 1 or 2 is characterized in that, the rising edge or the trailing edge of row clock judged described back three sampled values on described.

4, the method for claim 1 is characterized in that, described bus interface is the bus interface of 2M, 8M, 16M or 32M speed.

5, a kind of bus interface, this bus interface is the interface of the time division multiplexing serial-port of carrying impulse coding modulation code stream and signaling traffic, this bus interface comprises: the up receiver module that is used to handle upstream data, be used to handle the descending receiver module of downlink data, and the controller that is used to control up receiver module and descending receiver module; Described up receiver module comprises up bus, the reception shift register that receives up bus data and the reception read-write controller that this register is controlled at least; It is characterized in that, described up receiver module also comprises with up bus, receives read-write controller, receives the sampling edge adjusting module that shift register is connected with controller, this sampling edge adjusting module be used to accept controller configuration, up bus is sampled, is adjusted up bus sampling edge and control reception read-write controller and reception shift register according to sampled value;

Described up bus sampled, adjusted up bus sampling edge according to sampled value, comprising:

Row clock obtains the time-delay clock of same frequency in the time-delay; Utilize described rising edge and the trailing edge of going up row clock and time-delay clock that up bus is sampled, in each clock cycle of last row clock, to obtain four sampled values; Judge in described four sampled values that back three sampled values are whether entirely for " 0 " or be " 1 " entirely; If judged result is a "Yes", opposite triggerings that the last row clock of then confirming to be used for current operation triggers the edge be along can the up bus of reliable samples, and will be somebody's turn to do on the contrary that the triggering edge switches to the triggering edge that is used to move, otherwise do not change the triggering edge that is used to move.

6, bus interface as claimed in claim 5 is characterized in that described sampling edge adjusting module comprises:

Delayer is connected with last row clock, up clock delay is generated the time-delay clock of same frequency;

Sample register is connected the sampled value of storing up bus at the rising edge and the trailing edge of two clocks with last row clock, time-delay clock with up bus;

Edge judgement and selector are connected with sample register with last row clock, are used under the driving of last row clock control signal is adjudicated and exported to sampled value, to adjust up bus sampling edge.

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