CN100527277C - Page-buffer and non-volatile semiconductor memory including page buffer - Google Patents

Abstract

On the one hand, a non-volatile memory device which is capable of being operated in programming pattern and reading pattern is disclosed. The memory device comprises memory cell arrays which are provided with a plurality of non-volatile memory cells, a plurality of word lines and a plurality of bit lines, internal data output lines which are used for outputting data which is read from the bit lines of the memory array and a page buffer memory which is operably connected between the bit lines of the memory cell arrays and the internal data output lines, wherein the page buffer memory comprises check nodes which are selectively connected on the bit lines, latch circuits which are selectively connected on the check nodes and is used for latching nodes, a latch input path which is used for setting logic voltage of the latch nodes in programming pattern and reading pattern and a latch output path which is separated from the latch input path and is used for setting logic voltage of the internal data output lines according to the logic voltage of the latch nodes.

Description

Page-buffer and the nonvolatile semiconductor memory that comprises page-buffer

Technical field

The present invention briefly relates to a kind of semiconductor memory devices, more particularly, and the page-buffer circuit that the present invention relates in non-volatile semiconductor memory device, use and other circuit.

Background technology

In recent years, the demand of electrically programmable and electrically erasable nonvolatile memory device sharply increases.Even the feature of this equipment also can be kept the ability of the data of being stored at least partially in lacking power supply.It is very universal that the use of so-called flash memory has become, but particularly not exclusively, in environment such as the portable set of digital camera, cell phone, personal digital assistant (PDA) and kneetop computer.Flash memory such as the NAND type can be stored lot of data in relatively little scope.

As discussing in the background, present the potential basic operation principle of flashing storage unit and flash memory device below.Yet, it should be clearly understood that following discussion only is exemplary and do not limit and/or define scope of the present invention in arbitrary mode.

The operating principle of flashing storage unit is at first described referring to figs. 1A to Fig. 1 C.Figure 1A illustrates the Typical Disposition that flashing storage unit transistor wherein is connected to the word line and the bit line of memory device, Figure 1B shows the transistorized circuit symbol of flashing storage unit, and Fig. 1 C shows the transistorized threshold voltage characteristic of flashing storage unit.

Concentrate referring to figs. 1A to Fig. 1 C, the flashing storage unit transistor comprises the source area 4 and the drain region 5 on the surface that is positioned at substrate 3.In this example, substrate is the P type, and source area and drain region 4 and 5 are N+ types.On the channel region of definition between source area and drain region 4 and 5, arrange grid structure.Grid structure comprises floating grid 1 and control grid 2.Although not shown, tunnel effect (tunneling) dielectric layer is inserted between the surface of floating grid 1 and substrate P-sub, and another thin oxide layer (or control dielectric) is inserted between floating grid 1 and the control grid 2.In graphic example, provide drain voltage Vd from bit line BL, provide control gate pole tension Vcg from word line WL, and source voltage Vs is connected to the reference potential such as ground.

The transistorized threshold voltage of flashing storage unit defines the logical value of its storage.Just, when the flashing storage unit transistor was in its original state (being also referred to as " wiping " state), shown in Fig. 1 C, threshold voltage vt h was relatively low.In this state, cell transistor is designated as has logical value " 1 ", and it is usually corresponding to conducting (ON) state of conventional crystal tube apparatus.On the other hand, when cell transistor was in its " programming " state (PGM), threshold voltage vt h was higher relatively.This high threshold voltage state is designated as has logical value " 0 ", its usually corresponding to the conventional crystal tube apparatus by (OFF) state.

For cell transistor is changed (programming) from its original state is its programming state, utilizes to be known as Fowler-Nordheim (Fowler-Nordheim, FN) processing of tunnel effect.In brief, between control grid 2 and substrate P-sub, produce big relatively positive potential difference, and cause excited electron in the lip-deep raceway groove of substrate P-sub to be pushed over this raceway groove and subside in the floating grid 1.The electronics of these negative chargings serves as the barrier between control grid 2 and the suprabasil raceway groove, therefore increases the threshold voltage of cell transistor, shown in Fig. 1 C.Can cell transistor be brought back to its original state by between control grid and substrate P-sub, forming big negative electricity potential difference, thereby the FN tunnel effect that is produced pulls back the electronics of being subside across the thin oxide layer between floating grid 1 and substrate P-sub, therefore eliminates electronic barrier and has reduced threshold voltage vt h.

Referring now to Fig. 2, transistorized conducting of a large amount of flash cells that occurs in flash memory device and cutoff threshold voltage Vth show that usually bell curve distributes.For example, the threshold voltage vt h of the cell transistor that is wiped free of (having logical value " 1 ") can-3v and-distribute between the 1v, thereby the threshold voltage vt h of programmed unit transistor (having logical value " 0 ") can+1v and+distribute between the 3v.

Referring now to Fig. 3 A, by transistorized " string " that the is connected in series 6 qualitative NAND flash memories of flashing storage unit, wherein a plurality of strings 6 in parallel constitute the memory block 7 of flash memory.As shown in the figure, each string 6 comprises a plurality of flashing storage unit transistors that the bit line B/L in the memory block 7 is connected in series.Word line W/L is connected to the control grid of each row of the cell transistor in memory block 7.For example, flash memory device can be included in 16 or 32 cell transistors in each string 6, and 4224 strings (B/L0......B/L4223) in each memory block 7.

In the both sides of each string 6 is to have to receive to go here and there to select signal SSL and ground to select the string select transistor of the control grid of signal GSL.Usually, cell transistor read and programme in use to select signal SSL and GSL.And, be the common source polar curve CSL of source electrode line voltage that the cell transistor string 6 of each memory block 7 is set at the end of each string.

The table of Fig. 3 B briefly illustrate for wipe, programming and read operation, the different voltage conditions of the signal shown in Fig. 3 A.In this table, " Sel.W/L (selected W/L) " representative will be performed the selected word line of programming or read operation, and " Unsel.W/L (not selecting W/L) " represents the residue word line of memory block.For erase operation, " Sel.W/L (selected W/L) " representative will be performed the word line of the selected memory block of erase operation, and the word line of the remaining memory piece of " Unsel.W/L (not selecting W/L) " representative in memory cell array.

Below with reference to Fig. 3 B and 4 NAND flash programming operation is described.Here, go here and there and select signal SSL to be set to VDD, ground selects signal GSL to be set to 0v, common source polar curve CSL voltage is set to (for example, 1.5v), global voltage is set to 0v between VSS and the VDD.Usually, a word line generation one-time programming, and therefore be that each programming operation is selected a word line to each memory block.Here, selected word line W/L receives program voltage Vpgm, and remaining unselected word line W/L receives voltage Vpass, and wherein Vpgm is greater than Vpass.Vpgm is that sufficiently high voltage (for example, 18v), thereby produces the FN tunnel effect when the bit line B/L voltage of arbitrary cell transistor of selected word line is 0v.In other words, when the bit line B/L voltage of arbitrary cell transistor of selected word line was 0v, the voltage difference that program voltage Vpgm produces enough initial FN tunnel effect (for example, 18v), thereby placed cell transistor the state that is programmed.On the other hand, when the bit line B/L of arbitrary cell transistor voltage is VDD, as not enough voltage difference (for example, result 10v) and forbid the FN tunnel effect.So, this unit is called " forbidding programming ".Simultaneously, place conducted state by voltage Vpass is enough high with the cell transistor that will not select, but be not able to produce the height of FN tunnel effect.

Now with reference to Fig. 3 B and 5 explanation read operations.In this case, go here and there and select signal SSL to be set to Vread, ground selects signal GSL to be set to Vread, and common source polar curve CSL voltage is set to 0v, and integral body (bulk) voltage is set to 0v.As programming, read operation takes place once on a word line usually, therefore, selects a word line for each read operation for each memory block.Here, selected word line W/L is set to 0v, and voltage Vread is read in simultaneously remaining unselected word line W/L reception.In this example, Vread is 4.5v, and it surpasses the threshold voltage distribution of " 1 " and " 0 " cell transistor.Therefore, the cell transistor that is coupled to the unselected word line becomes conduction.On the other hand, the 0v voltage that is applied to selected word line drops between the threshold voltage distribution of " 1 " and " 0 " cell transistor.So, " 1 " cell transistor of only being connected to selected word line becomes conduction, thereby the residue cell transistor of selected word line is non-conduction.The result is the voltage difference between the bit line B/L of memory block.In the example that in the table of Fig. 3 B, provides, when being " 0 " state cell transistor on selected word line, reading the bit line B/L voltage of about 1.2v, and when on selected word line, being the one state cell transistor, read bit-line voltage less than 0.8v.

Now with reference to Fig. 3 B and 6 erase operation is described.In this case, bit line B/L, string are selected signal SSL, select signal GSL, common source polar curve CSL and do not select the word line of memory block all to be set to quick condition.On the other hand, selected word line voltage is set to 0v, and global voltage is set to Verase (for example, 19-21v).So, between control grid and integral body, form negative electricity pressure reduction, thereby produce FN tunnel effect across the gate oxide between floating grid and substrate.Therefore, threshold voltage distribution is reduced to the one state of wiping from " 0 " state of programming.Attention is after erase operation, and all cell transistors of selected memory block all are in the one state of wiping.

As mentioned above, the reading and programming of a word line ground execute store piece in memory block.But in some applications, say so more accurately and in memory block, carry out these operations " face page by page ".In Fig. 7, briefly show this notion.In an example shown, with bit line BL＜k:0〉be divided into even number and odd bit lines BL_E＜k:0〉and BL_O＜k:0.The cell transistor of every word line constitutes the page of memory block, and in the example of Fig. 7, every word line is connected to the odd number page and the even number page of memory block.As describing in detail more below, use the page-buffer PB＜k:0 that is included in the page-buffer piece〉send the data of reading from flash memory blocks, and send programming data to flash memory blocks.Usually, for each of odd and even number bit line to a page-buffer PB is provided.

Fig. 8 shows the block diagram of core parts of an example of NAND type flash memory, wherein uses so-called " Y-gating (Y-gate) " technology to visit the bit line of storer.As shown in the figure, via bit line BL＜255:0〉with page-buffer piece PBB＜31:0〉be connected to memory cell array MCARR.Each page-buffer piece PBB is connected in eight bit lines BL.Though do not have shown in Figure 8ly, in fact every bit lines BL is made of a pair of odd and even number bit line, as previously described with Figure 7.

With a plurality of page-buffer demoder PBDE＜31:0〉be coupled to operability each page-buffer piece PBB＜31:0, y address wire Ya＜7:0, y address wire Yb＜31:0 and global data bus GDB.As being described in more detail below, usually with y address wire Ya＜7:0〉be applied to all page-buffer demoder PBDE＜31:0, thereby with y address wire Yb＜31:0 independently each bar be applied to each page-buffer demoder PBDE＜31:0.In other words, page-buffer demoder PBDE0 receives y address Ya＜7:0〉and Yb0, page-buffer demoder PBDE receives Y address Ya＜7:0〉and Yb1, or the like.With internal data line IDB＜255:0〉be coupled to page-buffer piece PBB＜31:0〉and page-buffer demoder PBDE＜31:0 between.In the example of Fig. 8, between every couple of corresponding page buffer piece PBB and page-buffer demoder PBDE, provide eight internal data line IDB.

Also will be applied to page buffer piece PBB＜31:0〉be data input select signal DI and nDI and latch signal LCH＜7:0, their function is described below in conjunction with Fig. 9.

Fig. 9 shows the schematic circuit diagram of page-buffer PB shown in Figure 8 and page-buffer demoder PBDE.For convenience of explanation, Fig. 9 shows the page-buffer PB＜7:0 of be arranged side by side (that is, being arranged in juxtaposition at word-line direction) 〉.But in practice, page-buffer is one piles up (that is, being arranged in juxtaposition in bit line direction) on another.

The page-buffer demoder PBDE0 of Fig. 9 is included in the first transistor that connects between global data bus GDB and the public internal data line IDBC, and at page-buffer PB＜7:0〉the inner wire IDB of correspondence and public internal data line between a plurality of transistor secondses of connecting.As shown in the figure, the grid of the first transistor receives y address signal Yb0, and the grid of the correspondence of transistor seconds receives y address signal Ya＜7:0 simultaneously 〉.Therefore clearly, use y address Yb＜31:0〉select page-buffer piece PBB＜31:0 in any one, and use address Ya＜7:0 select the bit line BL in the selected page-buffer piece PBB.

Page-buffer PB0 comprises having and latchs node CMNLA and the latch cicuit of node CMNLAn is latched in counter-rotating.Control first and second transistors of page-buffer PB0 respectively by data input select signal DI and nDI, and these transistors are connected to latching between node CMNLAn and the CMNLA of internal data line IDB0 and counter-rotating.Select signal PBSLT to control another transistor by page-buffer, and this transistor is connected latchs between node CMNLA and the detection node NSEN0.By another transistorized operation of being controlled by load control signal PLOAD, the detection node MSEN0 that is connected to the memory cell strings of memory cell array optionally is connected to voltage VDD.At last, other two transistor series are connected between internal data line IDB and the reference voltage V SS.The voltage that go up to be occurred by detection node NSEN0 is controlled in these two transistors, simultaneously by latch signal LCH＜0〉control another.

In brief, in programming mode, the latch cicuit storage of page-buffer PB0 is by the logical value of the voltage appointment of data input select signal DI and nDI and internal data line IDB, the bit line that then this logical value (that is, latching the voltage that occurs on the node CMNLA) is sent to memory cell strings is used for programming.Similarly, in read operation, the voltage that is detected that will occur on detection node NSEN0 temporarily is stored in the latch cicuit, then this voltage is sent to global data bus GDB via internal data line IDB.Notice that internal data line IDB is as sharing the input and output line.

Above-mentioned traditional, nonvolatile memories equipment is subjected to the influence of some shortcomings, and specifically, along with reducing of the layout areas of various circuit, it is more integrated to satisfy the needs of higher storage device capacity that memory devices becomes.Here do not attempt exhaustive, but some examples of these shortcomings of bar opinion below.

Figure 10 shows the parasitic capacitive coupling that produces between internal data line.As mentioned above, and as shown in figure 10, on the bit line direction, promptly between page-buffer demoder PBDE and memory cell array MCARR, be arranged in juxtaposition page-buffer＜7:0 of (piling up) each page-buffer piece PBB 〉.Thereby also show by detection node block signal SOBLK control respectively with detection node SON＜7:0〉selectively be coupled to bit line BL＜7:0 a plurality of transistors.

The internal data line IDB of each page-buffer PB all in page-buffer piece PBB to extending parallel to each other.Along with reducing of the layout areas of page-buffer PB, the spacing P between the adjacent inner data line IDB diminishes, and therefore, capacitive couplings increases between adjacent inner data line IDB.The coupled noise that produces between adjacent inner data line IDB can cause distorted signals and error in data.

The big stray capacitance of internal data line IDB can also latch node with the low electric capacity of the latch cicuit of each page-buffer PB and produce electric charge and share condition.In some cases, this can cause the upset of data.And the heavy output load of internal data line IDB makes must increase the output driving force of page-buffer, when space and energy resource have in limited time this very difficulty.

And, refer again to Fig. 8, shown in the bus zone of example comprise 40 y address wires.The bus zone of big layout area that must be by device holds the line of relatively large quantity, thereby has occupied valuable space resources.

Summary of the invention

According to an aspect of the present invention, provide a kind of non-volatile memory devices that can in programming mode and readout mode, operate.This memory devices comprise have a plurality of Nonvolatile memery units, the memory cell array of many word lines and multiple bit lines.This memory devices also comprises: the internal data output line is used to export the data of reading from the bit line of memory array; And page-buffer, be connected to its operability between the bit line and internal data output line of memory cell array.Page-buffer comprises: detection node, and it optionally is connected to bit line; Latch cicuit, it has the node that latchs that optionally is connected to detection node; Latch the input path, the logic voltage of node is latched in its setting; With latch outgoing route, it separates and is provided with according to the logic voltage that latchs node logic voltage of internal data output line from latching the input path.

According to another aspect of the present invention, the non-volatile memory devices that is provided comprises memory cell array, and this array comprises: a plurality of Nonvolatile memery units; Page-buffer, it comprises that latch cicuit is used for temporary transient the storage from the Nonvolatile memery unit of memory cell array data of reading and the data that will programme and deposit in; The internal data incoming line, data that its output is read from memory cell array and temporarily be stored in it page-buffer; Latch the input path, it separates with the internal data output line and latch cicuit is set when data programing being entered the Nonvolatile memery unit of memory cell array and when from the Nonvolatile memery unit sense data of memory cell array.

Still according to another aspect of the present invention, provide a kind of non-volatile memory devices that comprises memory cell array, this memory cell array comprises: a plurality of Nonvolatile memery units; Input data bus, its input will be programmed into the data of the Nonvolatile memery unit of memory cell array; Output data bus, it separates with input data bus and exports the data of reading from the Nonvolatile memery unit of memory cell array; Latch cicuit is used for temporary transient the storage from the Nonvolatile memery unit of memory cell array data of reading and the data that will programme and deposit in; The internal data output line, it is connected to output data bus; Latch the input path, it is connected to input data bus, and latch cicuit is set when data programing being entered the Nonvolatile memery unit of memory cell array; And output driving circuit, its sense data that will temporarily be stored in the latch cicuit sends to the internal data output line.

According to another aspect of the present invention, provide a kind of non-volatile memory devices that comprises memory cell array, this memory cell array comprises: a plurality of Nonvolatile memery units; Many word lines; And multiple bit lines.Memory devices also comprises internal data output line and a plurality of page-buffers that are connected with memory cell array and internal data output line.The a plurality of page-buffers of arranged in succession are to define corresponding a plurality of page-buffer zones that are arranged in juxtaposition, wherein each page-buffer comprises the latch cicuit of the data that temporary transient storage is read from memory cell array, and is connected the address gate between latch cicuit and the internal data output line.Address gate will optionally output to the internal data output line from the data of the latch cicuit of each page-buffer in response to address signal.

According to another aspect of the present invention, provide a kind of non-volatile memory devices that comprises memory cell array, this memory cell array comprises: a plurality of Nonvolatile memery units; Many word lines; And multiple bit lines, described multiple bit lines longitudinal extension on first direction.Described memory devices also comprises: share the internal data output line, the data that its output is read from memory cell array; A plurality of internal data incoming lines; With a plurality of page-buffers, be connected between the memory cell array to each page-buffer operability; Share the internal data output line; With many internal data incoming lines.

Also according to another aspect of this aspect, provide a kind of non-volatile memory devices that comprises memory cell array, this memory cell array comprises: a plurality of Nonvolatile memery units; And page-buffer, it comprises local data's incoming line and latch cicuit.Data that latch cicuit is read from the Nonvolatile memery unit of memory cell array with temporary transient storage in response to local data's incoming line and the data that will programme and deposit in.Described memory devices also comprises: the global data incoming line, and it provides external input signal, and wherein external input signal comprises programming signal that is used for the program memory cells array and the control signal that is used for the readout memory cell array; Gate circuit, it optionally exports external input signal to local data's incoming line according to the address signal that offers gate circuit.

Also according to another aspect of this aspect, provide a kind of non-volatile memory devices that comprises memory cell array, this memory cell array comprises: a plurality of Nonvolatile memery units; Many word lines; And multiple bit lines.Memory devices of living in also comprises: internal data output line, the data that its output is read from memory cell array; A plurality of page-buffers, with its operability be connected between memory cell array and the internal data incoming line; With a plurality of address wires, with its operability be connected at least one gate circuit in a plurality of page-buffers.

According to another aspect of the present invention, provide a kind of page-buffer that is used for non-volatile memory devices.This page-buffer comprises latch cicuit, and this circuit comprises: latch node; The internal data incoming line, the voltage of node is latched in its control; The internal data output line, its with latch node and electrically separate; And output driving circuit, it controls the voltage of inner output data line according to the voltage that latchs node.

Also according to another aspect of the present invention, provide a kind of non-volatile semiconductor memory device that comprises memory cell array, described memory cell array has: a plurality of electrically programmable erasable memory cells; Many word lines; And multiple bit lines.Described memory devices also comprises at least one the page-buffer piece with internal data output line and a plurality of page-buffers.Page-buffer is connected respectively to bit line and selects at least one in the address and enable in response to a plurality of buffers.The corresponding data of data on the storage of each page-buffer and its bit line that latchs at it on node.The internal data output line is shared between a plurality of page-buffers and by the data-driven on the node of latching of the page-buffer that enables.The internal data output line is separated electrically with the node that latchs of page-buffer.

Description of drawings

According to the following detailed description of reference accompanying drawing, of the present invention above and other aspects and characteristics will become very obvious, wherein:

Figure 1A shows the synoptic diagram of flashing storage unit, the circuit symbol of flashing storage unit and the threshold voltage characteristic figure of flashing storage unit respectively to 1C;

Fig. 2 shows the threshold voltage distribution of flashing storage unit;

Fig. 3 A and 3B show the table of the wiping of the synoptic diagram of NAND flashing storage unit piece and explanation NAND flashing storage unit piece, programming and read-out voltage respectively;

Fig. 4 shows the synoptic diagram of the programming of the NAND flashing storage unit piece shown in the key drawing 3A;

Fig. 5 shows the synoptic diagram of reading of the NAND flashing storage unit piece shown in the key drawing 3A;

Fig. 6 shows the synoptic diagram of wiping of the NAND flashing storage unit piece shown in the key drawing 3A;

Fig. 7 shows the synoptic diagram of memory block and page-buffer piece;

Fig. 8 shows the synoptic diagram of traditional, nonvolatile memories equipment;

Fig. 9 shows the page-buffer that comprises and the synoptic diagram of page-buffer demoder in the traditional, nonvolatile memories equipment of Fig. 8;

Figure 10 shows the schematic layout pattern of the page-buffer in the page-buffer piece that comprises in the traditional, nonvolatile memories equipment of Fig. 8;

Figure 11 shows the block diagram according to the non-volatile semiconductor memory device of the embodiment of the invention;

Figure 12 shows the synoptic diagram of the example of the memory array that comprises in the nonvolatile memory in Figure 11;

Figure 13 shows the example of the page-buffer piece that comprises in the nonvolatile memory in Figure 11;

Figure 14 shows the synoptic diagram of the example of the page-buffer that comprises in the page-buffer piece of Figure 13;

Figure 15 shows the synoptic diagram of the example of the page-buffer demoder that comprises in the nonvolatile memory in Figure 11;

Figure 16 A and 16B show the process flow diagram of the readout mode of nonvolatile memory according to an embodiment of the invention;

Figure 17 shows the timing diagram of the readout mode of nonvolatile memory according to an embodiment of the invention;

Figure 18 shows the process flow diagram of programming non volatile memories pattern according to an embodiment of the invention;

Figure 19 shows the timing diagram of programming non volatile memories pattern according to an embodiment of the invention; With

Figure 20 shows the timing diagram of the erasing mode of nonvolatile memory according to an embodiment of the invention.

Embodiment

Below, will be by preferred but non-limiting example illustrates the present invention.

Figure 11 shows the block diagram according to the non-volatile semiconductor memory device of the embodiment of the invention.

With reference to Figure 11, the non-volatile semiconductor memory device of this example comprises memory cell array MCARR, page-buffer piece NWPBB＜63:0 〉, first and second overall incoming line GDI and the nGDI, overall situation output line GDOUT, y address signal line Yp＜7:0 〉, Yq＜7:0 and Yr＜7:0, sensing latch signal wire LCH＜7:0〉and page-buffer demoder NWDE＜63:0.

Memory cell array MCARR comprises matrix array, word line WL (not shown in Figure 11) and the bit line BL＜511:0 of memory cell 〉.In the example of present embodiment, memory cell is the flashing storage unit transistor.

With inner incoming line IDI＜63:0〉and nIDI＜63:0 and inner output line IDOUT＜63:0 be connected page-buffer demoder NWDE＜63:0 and corresponding page buffer piece NWPBB＜63:0 between.

In the scheduled operation interim such as readout mode, programming mode and erasing mode, the first overall incoming line GDI and the second overall incoming line nGDI send the input data of opposite logic states.As describing in detail in the back, each page-buffer demoder NWDE＜63:0〉will import data GDI and nGDI with y address date Yq＜7:0 and Yr＜7:0 decode, to export inner incoming line IDI＜63:0〉and nIDI＜63:0 data.

And, each page-buffer demoder NWDE＜63:0〉provide with at inner output line IDOUT＜63:0 on the corresponding data of data give overall output line GDOUT.

Page-buffer piece NWPBB＜63:0〉in response to latch signal line LCH＜7:0〉and y address Yp＜7:0.As describing in detail in the back, page-buffer piece NWPBB＜63:0〉be used for temporary transient storage and subsequently will with inner incoming line IDI＜63:0 and nIDI＜63:0 on the corresponding input data of data send to bit line BL＜511:0, and temporarily store and subsequently will with bit line BL＜511:0 on the corresponding output data of data send to inner output line IDOUT＜63:0.

Figure 12 shows according to an embodiment of the invention, the synoptic diagram of the part of the memory cell array MCARR among Figure 11.Specifically, Figure 12 shows the related circuit of memory cell strings with the first bit line BL0 of Figure 11.Dispose bit line BL＜511:1 similarly 〉.

As mentioned above, memory cell array MCARR generally includes the matrix array of memory cell MC, many word line WL＜n-1:0〉and multiple bit lines BL＜511:0.The memory cell MC of the non-volatile semiconductor memory device of present embodiment is a NAND type flashing storage unit.

Figure 12 shows the even number of the bit line BL0 that is connected to composition Figure 11 and first and second string STe0 and the STo0 of odd bit lines BLe0 and BLo0.Each string STe0 and STo0 are included in the transistor at the two ends of the memory cell MC that is connected to selection wire SSL and GSL.As shown in the figure, selection wire SSL and GSL are abreast to word line WL＜n-1:0〉advance.And each string STe0 and STo0 stop at common source polar curve CSL place.

Even number and odd bit lines are connected to bit line controll block BLCONBK.For convenience of explanation with simplify before Figure 11 of explanation, the formation parts as memory cell array MCARR here bit line controll block BLCONBK are described.But, bit line controll block BLCONBK can also be regarded as independent different circuit of with memory cell array MCARR.

Read, programming and erase mode of operation each in, bit line controll block BLCONBK selects one of even bitlines BLe0 and odd bit lines BLo0, and selected bit line is connected to bit line BL0.By the transistor 515 of detection node block signal SOBLK control and the transistor 513 and 514 of selecting signal BLSLTe and odd bit lines to select signal BLSLTo control respectively by even bitlines, carry out this operation.

In addition, bit line controll block BLCONBK be used for read, programming and erase mode of operation, precharge or regulate the voltage of even bitlines BLe0 and odd bit lines BLo0.This is provided transistor 511 and 512.Promptly, transistor 511 comes optionally bit line power voltage BLPWR to be connected to even bitlines BLe0 in response to even number shielded signal SHLDe, and transistor 512 comes optionally bit line power voltage BLPWR to be connected to odd bit lines BLo0 in response to even number shielded signal SHLDo.

Figure 13 shows the example of page-buffer piece NWPBB0 shown in Figure 11.Residue page-buffer piece NWPBB＜63:1〉have a similar configuration.

The page-buffer piece NWPBB0 of Figure 13 comprises a plurality of page-buffer NWBUF＜7:0 〉, inner output line IDOUT0, the first inner incoming line IDI0 and the second inner incoming line nIDI0.Page-buffer NWBUF＜7:0〉storage sends to bit line BL＜7:0 respectively〉and from bit line BL＜7:0 the data that receive.

Inner output line IDOUT0 is the public inner output line that is used for page-buffer piece NWPBB0, and transmission and page-buffer NWBUF＜7:0〉any one in the corresponding output data of data of storing.

The first inner incoming line IDI0 and the second inner incoming line nIDI0 provide according to the input data and are controlled at page-buffer NWBUF＜7:0〉in the signal of data storage.

In order to minimize required layout area, the page-buffer NWBUF＜7:0 that will in page-buffer piece NWPBB0, comprise〉place with the structure of piling up, that is, be arranged in parallel between page-buffer demoder NWDE0 and the memory cell array MCARR.

Each page-buffer NWBUF＜7:0 with page-buffer piece NWPBB〉be connected to inner incoming line IDI0 and nIDI0 and a corresponding bit lines BL＜7:0〉between.And each all is equipped with transistor 870a, its in response to bit line cut-off signals BLSHF with corresponding bit lines BL＜7:0 be connected to corresponding detection node NSEN＜7:0.

And, each page-buffer NWBUF＜7:0〉the corresponding y address signal Yp＜7:0 of reception 〉.Opposite with traditional memory devices, in the example of present embodiment, with these address signals Yp＜7:0〉be directly connected to corresponding page buffer NWBUF＜7:0〉(also referring to Figure 11).As describing in detail in the back, this has produced two kinds of benefits, promptly reduces the quantity of the line that occurs and reduce the total amount of the y address wire of storer in the bus zone of storer.Here, with Yp＜7:0〉address signal is called the buffer selecting address signal.

As shown in Figure 13, preferably inner output line IDOUT0 is piled up page-buffer NWBUF＜7:0 therein〉direction in extend.So, from each page-buffer NWBUF＜7:0〉variation to the transmission linear distance of inner output line IDOUT0 is minimized.Subsequently when from page-buffer NWBUF＜7:0〉when inner output line IDOUT0 was written into data, this minimizing increased signal conformance, thus strengthened the detection limit (margin) of nonvolatile memory.

And, in the example of present embodiment, at page-buffer NWBUF＜7:0〉between share inner output line IDOUT0.The advantage that this configuration produces is the internal data line IDB＜7:0 that can avoid with the legacy memory (see figure 10)〉the relevant problem of intercoupling (parasitic coupling).

Figure 14 shows the example of the page-buffer NWBUF0 of Figure 13.Dispose remaining page-buffer NWBUF＜7:1 similarly 〉.

As shown in Figure 14, page-buffer NWBUF0 comprise detection node NSEN0, latch units 810, latch transmitting element 820, latch driver element 825, detect response unit 830, output driver element 840, buffer selected cell 850, detect unit 860 is set, bit line turn-offs unit 870 and inner output line IDOUT0.The data that provide from bit line BL0 are provided detection node NSEN0, and are connected with bit line BL0 by bit line shutoff unit 870.

Bit line turn-offs unit 870 and controls the connection of bit line BL0 to detection node NSEN0 in response to bit line cut-off signals BLSHF.Best, use in response and turn-offed transistor 870a by the bit line of the low voltage nmos of gate and realize that bit line turn-offs unit 870 in bit line cut-off signals BLSHF.

What latch units 810 comprised storage data corresponding with the data of bit line BL0 latchs node NLAT.

Select address Yp0 and enable to latch driver element 825 in response to buffer so that the predetermined driving voltage that latchs to be provided.In this example, latching driving voltage is ground voltage VSS, and is independent of and is offering the first and second inner incoming line IDI0 that latch transmitting element 820 and the data on the nIDI0.The driver element 825 that latchs of this example comprises and latchs driving transistors 825a, and latchs that driving transistors 825a preferably selects address Yp0 in response to buffer and by the nmos pass transistor of gate, and has the source electrode that is connected to ground voltage VSS.

The transmitting element 820 that latchs of this example comprises that first and second latch transmission transistor 820a and 820b.In response to the first inner incoming line IDI0, first latch send transistor 820a provide from latch driving transistors 825a provide come latch the node N810a of driving voltage to latch units 810.Best, latch first and to send transistor 820a and be connected to and latch driving transistors 825a, and latch first in response to the data on the first inner incoming line IDI0 and to send transistor 820a and carry out gate.Therefore, if when buffer selects address Yp0 in logic " H " state, the data of logic state " H " are put on the first inner incoming line IDI0, then first latch and send transistor 820a ground voltage VSS is provided the node N810a to latch units 810.

In response to the second inner incoming line nIDI0, second of this example latchs and sends transistor 820b and provide from latching driving transistors 825a and provide the driving voltage that latchs that comes to latch node NLAT to latch units 810.Best, with the second latch transistor 820b with latch driving transistors 825a and be connected in series, and in response to the data on the second inner incoming line nIDI0 to the second latch transistor 820b gate.Therefore, if the data with logic state " H " when buffer selects address Yp0 in logic " H " state put on the second inner incoming line nIDI0, then second latch and send transistor 820b and provide ground voltage VSS to latch node NLAT to latch units 810.

That is, in the example of present embodiment, when conducting first is latched when sending transistor 820a, with the data storage of logic " H " state on logic node NLAT.On the other hand, when conducting first is latched when sending transistor 820b, with the data storage of logic " L " state on logic node NLAT

In Figure 14, RBIN1 and RBIN2 represent will latch the buffer input path that driving voltage sends to latch units 810 by it.Promptly, to latch and send transistor 820a and be appointed as first buffer input path RBIN1 by latching driving transistors 825a and first, and will latch and send transistor 820b and be appointed as second buffer to the transmit path that latchs node NLAT and import path RBIN2 by latching driving transistors 825a and second to the transmit path that latchs node NLAT.

The detection response unit 830 that is driven this example by detection node NSEN0 detects response voltage to latching transmitting element 820 optionally to send, thereby control store is in the data that latch on the node NLAT.Best, detecting response voltage is ground voltage VSS.Detect response unit 830 and comprise that for example detecting response transistor 830a detects transistor 830b with output.

Best, detect response transistor 830a be in response on detection node NSEN0 data and by the nmos pass transistor of gate.Output detects transistor 830b, and is provided with the source electrode that is connected to ground voltage VSS.In the time will detecting response transistor 830a conducting, output detects transistor 830b and comes to provide the detection response voltage to latch units 810 by latching transmitting element 820 in response to sensing latch signal LCH.And, latch node NLAT in response to detecting the response voltage storage data corresponding with detection node NSEN0.

Detection is provided with unit 860 detection node NSEN0 is arranged on the predetermined voltage that is provided with.In this example, it is supply voltage VDD that voltage is set, and detects and unit 860 to be set to comprise detecting transistor 860a is set.Best, detect be provided with transistor 860a be have the supply voltage of being connected to VDD (for example, source electrode 2.2V) and in response to detecting signalization/PLOAD by the PMOS transistor of gate.

Select address Yp0 to enable to export driver element 840 in response to buffer.When being enabled, output driver element 840 drives inner output line IDOUT0 to predetermined driving voltage in response to being stored in the data that latch on the node NLAT.As in Figure 14, obviously illustrating, inner output line IDOUT0 is separated with RBIN2 and isolates electrically from latching node NLAT and buffer input path RBIN1.

Output driver element 840 comprises for example first output driving transistors 840a and the second output driving transistors 840b.Come the gate first output driving transistors 840a by the data of storing on the node NLAT that latch in latch units 810.In this example, the first output driving transistors 840a is switched on when the data of storing on the node NLAT latching of latch units 810 are logic " H ".The second output driving transistors 840b and the first output driving transistors 840a are connected in series.Select address Yp0 to come the gate second output driving transistors 840b in response to buffer to drive inner output line IDOUT0 to driving voltage.In this example, driving voltage is the ground voltage VSS that is connected to the source electrode of the first output driving transistors 840a.Therefore, according to present embodiment, when the data of storing on latching node NLAT are logic " H " state, select address Yp0 to change logic " H " state in response to buffer and drive inner output line to ground voltage VSS.

Being connected of node NLAT and detection node NSEN0 latched in 850 controls of this routine buffer selected cell.In this example, buffer selected cell 850 comprises that buffer selects transistor 850a, and it is in response to that buffer is selected signal PBSLT and by the nmos pass transistor of gate.When the voltage level of buffer being selected signal PBSLT becomes logic " H " state, will select transistor 850a to send to detection node NSEN0 by buffer in the data that latch on the node NLAT, wherein can send it to bit line BL0 subsequently.

Figure 15 shows the example of page-buffer demoder NWDE0 shown in Figure 11.Can dispose remaining page-buffer demoder NWDE＜63:1 similarly 〉.

Page-buffer demoder NWDE0 has two kinds of major functions.The first, page-buffer demoder NWDE0 optionally sends the output data corresponding with the data on inner output line IDOUT0 to overall output line GDOUT.The second, page-buffer demoder NWDE0 sends data to the first inner incoming line IDI0 corresponding with the input data on the first overall incoming line GDI and the second overall incoming line nGDI and the second inner incoming line nIDI0 respectively.

Page-buffer demoder NWDE0 in the example of Figure 15 comprises first to the 3rd logic gate 1201,1203 and 1205, phase inverter 1206 and the demoder transistor 1207.

Here, with y address signal Yq＜7:0〉be called main separation and select the address, and with y address signal Yr＜7:0 be called the secondary address (seeing Figure 11) of selecting.

1201 pairs of main separations of first decoder logic gates are selected address Yq0 and secondary selection address Yr0 actuating logic computing, and the output logic operation result is as piece decoded signal/BLDEC.In this example, first decoder logic gates 1201 is main separation to be selected the NAND door of address Yq0 and the secondary address Yr0 of selection execution NAND computing, and first decoder logic gates, 1201 output NAND operation results are as piece decoded signal/BLDEC.In this case, when main separation being selected address Yq0 and the secondary address Yr0 both of selection and be activated to logic " H " state, piece decoded signal/BLDEC is activated to logic " L " state.

Enable second decoder logic gates 1203 in response to piece decoded signal/BLDEC, and second decoder logic gates 1203 provides logic operation result to the first inner incoming line IDI0 according to the data on the first overall incoming line GDI.In this example, second decoder logic gates 1203 is that the piece decoded signal/BLDEC and the first overall incoming line GDI are carried out the NOR door that NOR operates.In this case, when piece decoded signal/BLDEC is in logic " L " state (, when main separation is selected address Yq0 and the secondary address Yr0 both of selection for logic " H " state), second decoder logic gates 1203 will be in the data reversal on the first overall incoming line GDI and the result that counter-rotating is provided to the first inner incoming line IDI0.

Enable the 3rd decoder logic gates 1205 in response to piece decoded signal/BLDEC, and the 3rd decoder logic gates 1205 provides logic operation result to the second inner incoming line nIDI0 according to the data on the second overall incoming line nGDI.In this example, the 3rd decoder logic gates 1205 is that the piece decoded signal/BLDEC and the second overall incoming line nGDI are carried out the NOR door that NOR operates.In this case, when piece decoded signal/BLDEC is in logic " L " state (, when main separation is selected address Yq0 and the secondary address Yr0 both of selection for logic " H " state), the 3rd decoder logic gates 1205 is reversed in the data on the second overall incoming line nGDI and the data of counter-rotating is offered its second inner incoming line nIDI0.

Phase inverter 1206 inverse block decoded signal/BLDEC are with gate demoder transistor 1207.So, in this example, when piece decoded signal/BLDEC being activated to logic " L " state, demoder transistor 1207 provides data on the inner output line IDOUT0 to overall output line GDOUT.

In the example of present embodiment, nonvolatile memory comprises 64 page-buffer demoder NWDE＜63:0 〉.Select address Yq＜7:0 according to main separation〉and the secondary address Yr＜7:0 of selection combination, select page-buffer demoder NWDE＜63:0 independently 〉.Use main separation to select address Yq＜7:0〉at 64 page-buffer demoder NWDE＜63:0 among select one in 8 groups (every group has 8 buffer demoders), and use secondary selection address Yr＜7:0 be chosen in 8 page-buffer demoders that comprise in selected group.And, as previously mentioned, use buffer to select address Yp＜7:0〉select in 8 page-buffers related independently one with selected buffer demoder.

So, in example of the present invention, the sum of column address bus is 24, and relatively advantages are very obvious with 40 column address conductors in the conventional memory device shown in Fig. 8.

And, as mentioned above, with inner output line IDOUT0 with latch node NLAT and buffer input path RBIN1 and separate electrically with RBIN2.Therefore, can be with (promptly at selected page-buffer, the distortion minimization of the data that latch the last storage of node NLAT NWBUF0), otherwise storage and data that be recharged on inner output line IDOUT0 may cause this distortion in other page-buffers (for example, NWBUF＜7:1 〉).

The example of the reading of the foregoing description, programming and erase mode of operation will be described now.Also can be in each explanation below with reference to before described Figure 11 to 15.

At first the read operation pattern is described with reference to Figure 16 A and 16B.

Figure 16 A shows operation pages buffer NWBUF is stored in the method for the data among the selected memory cell MCsel (seeing Figure 12) with output process flow diagram.

At step S910, the data of node NLAT to logic " H " state (" first logic state ") or logic " L " state (" second logic state ") are latched in initialization.Can carry out the initialization of latching node NLAT by the first inner incoming line IDI0 and the second inner incoming line nIDI0.

Normal read at the example of present embodiment goes out in the operator scheme, is initialized as the data of second logic state with latching node NLAT.Be initialized as second logic state in order to latch node NLAT, buffer selects address Yp0 to become logic " H " pulse, and the second inner incoming line nIDI0 also becomes logic " H " pulse.In this case, the first inner incoming line IDI0 keeps logic " L " state.Then, will latch the data that node NLAT is initialised to logic " L " state, that is, and second logic state.

On the other hand, in the erase check read operation pattern of the example of present embodiment, be initialized as the data of first logic state with latching node NLAT.For initialization is latched node NLAT to first logic state, buffer selects address Yp0 to become logic " H " pulse, and the first inner incoming line IDI0 also becomes logic " H " pulse.In this case, the second inner incoming line nIDI0 keeps logic " L " state.Then, node NLAT be will latch and logic " H " state, the i.e. data of first logic state will be initialised to.

At step S950, will be corresponding with the data in being stored in selected memory cell MCsel, on the bit line BL0 development (develope) data storage latching on the node NLAT.

Figure 16 B shows the step S951, the S953 that can be used as the step S950 among Figure 16 A and be performed and the process flow diagram of S955.In this example, preferably consider the execution of step S951, but it can be omitted.

At step S951, adjust detection node NSEN0 to supply voltage VDD by detecting the transistor 860a that is provided with that unit 860 is set, that is, voltage is set.Control of Voltage is set detects response unit 830 (LCH is enabled in response to the sensing latch signal) to provide the detection response voltage to latching transmitting element 820.And, bit line cut-off signals BLSHF is changed into logic " L " state.

In this example, step S951 comprises step S951a and S951b.At step S951a, the voltage level that will detect signalization/PLAOD in the preset time section remains on the first stand-by voltage VPRE1, to prevent following dash (undershooting) of supply voltage VDD.At step S951b, will detect signalization/PLOAD and change into logic " L " state.

At step S953, detect response unit 830 and will detect response voltage in response to the data that on bit line BL0, develop and offer and latch transmitting element 820.In this example, step S953 comprises step S953a, S953b and S953c.

At step S953a, detect signalization/PLOAD and become logic " H " state.So, discharge the state that is provided with of detection node NSEN0, and detection node NSEN0 is changed into quick condition.And, at step S953b, bit line is turn-offed transistor 870a conducting, thereby the detection node NSEN0 that will float is connected to bit line BL0.Therefore, detection node NSEN0 is received in the data that bit line BL0 goes up development.

Subsequently, if selected memory cell MCsel is that then the voltage level with detection node NSEN0 approximately remains on supply voltage VDD by the unit.On the other hand, if selected memory cell MCsel is an onunit, then the voltage level with detection node NSEN0 approximately remains on ground voltage VSS.

At step S953c, detecting response unit 830 optionally provides the detection response voltage to latching transmitting element 820 according to detection node NSEN0.Promptly, if when selected memory cell MCsel produces sensing latch signal LCH as " H " pulse when the voltage level of unit and detection node NSEN0 approximately remains on supply voltage VDD, then detecting response unit 830 provides and detects response voltage (being VSS in this example) and give and latch transmitting element 820.On the other hand, when selected memory cell MCsel is the voltage level of onunit and detection node NSEN0 when approximately remaining on ground voltage VSS, will detect response voltage as " H " pulse yet and offer and latch transmitting element 820 even produce sensing latch signal LCH.

At step S955, overturn and latch node NLAT in response to offering the detection response voltage that latchs transmitting element 820.

S910 discusses as integrating step, goes out in the operator scheme in normal read, is initialized as the data of second logic state with latching node NLAT.In this case, at step S955, the first inner incoming line IDI0 is in logic " H " state and the second inner incoming line nIDI0 is in logic " L " state.Therefore, when selected memory cell MCsel is by the unit, promptly during programmed cells, will latchs node NLAT and be turned to logic " H " state (first logic state) from logic " L " state (second logic state).But, when selected memory cell MCsel is an onunit, during the unit promptly wiped, latchs node NLAT and keep logic " L " state (second logic state).

On the other hand, as also integrating step S910 is illustrated, in erase check read operation pattern, be initialised to the data of first logic state with latching node NLAT.In this case, at step S955, the first inner incoming line IDI0 is logic " L " state and the second inner incoming line nIDI0 is logic " H " state.Therefore, if selected memory cell MCsel is by the unit, during the promptly non-unit of wiping, will latchs node NLAT and be turned to logic " L " state (second logic state) from logic " H " state (first logic state).On the other hand, if selected memory cell MCsel is an onunit, during the unit promptly wiped, will latchs node NLAT and keep logic " H " state (first logic state).

Get back to Figure 16 A, at step S970, by latch the data of storing on the node NLAT control output driver element 840.Therefore, optionally inner output line IDOUT0 is driven into driving voltage, that is, and ground voltage VSS.That is, are logic " H " if be stored in the data that latch on the node NLAT, then select address Yp0 that inner output line IDOUT0 is driven into ground voltage VSS in response to buffer.But, are logic " L " if be stored in the data that latch on the node NLAT, even then when buffer selects address Yp0 to become logic " H " state, inner output line IDOUT0 also keeps its initial logic state, it is supply voltage VDD.

Timing diagram with reference to Figure 17 describes the example that normal read goes out operator scheme in detail below.

Figure 17 is that normal read goes out operator scheme (readout mode) timing diagram, shows various node voltages and signal voltage at the non-volatile memory devices shown in the example from Figure 11 to Figure 15.And, in the following description will be with reference to these figure of front.

In readout mode, fetch the data that in selected memory cell MCsel, write, export the data of being fetched then.

For illustrative purposes, readout mode shown in Figure 17 is divided into six intervals, that is, bit line discharges and page-buffer reseting interval (being called " READ1 at interval " afterwards), bit-line pre-charge (are called " READ2 at interval ") at interval afterwards, bit line develops at interval (being called " READ3 at interval " afterwards), assay intervals (being called " READ4 at interval " afterwards), recover interval (being called " READ5 at interval " afterwards) and data retrieval (is called " READ6 at interval ") at interval afterwards.

And, for illustrative purposes, will be divided into " READ1 is at interval " page-buffer reseting interval (being called " READ1a is at interval " afterwards) and bit line discharges and (be called " READ1b is at interval " afterwards) at interval.In READ1a interim, the node NLAT that latchs of page-buffer is reset to logic " L " state, that is, and ground voltage VSS.Subsequently,, even bitlines BLe0, odd bit lines BLo0 and bit line BL0 are discharged into ground voltage VSS in READ1b interim, that is, and the data of logic " L " state.

As described below, latch resetting of node NLAT in READ1a interim.In READ1a interim, because buffer selects address Yp0 to be in logic " H " state, so driving transistors 825a (tR1) is latched in conducting.And, because main separation is selected address Yp0 and the secondary address Yr0 both of selection is logic " H ", so piece decoded signal/BLDEC becomes logic " L " state (tR2).In this case, the first overall incoming line GDI is a logic " H " and the second overall incoming line nGDI is logic " L ".Therefore, the first inner incoming line IDI0 is logic " L ", and the second inner incoming line nIDI0 be logic " H " (tR3).Therefore, end first and latch transmission transistor 820a, and transmission transistor 820b is latched in conducting second.Therefore, the node N810a of latch units 810 is changed into logic " H " state, and will latch node NLAT and reset to logic " L " state.

To be described in the discharge of bit line BLe0, BLo0 and BL0 during the READ1b now.For convenience, suppose to be chosen in the memory cell MCsel of the top among the left memory cell strings STe0 (Figure 12) here.

In READ1b interim, with read-out voltage VREAD (for example, 5V) put on unselected word line WL＜n-2:0 〉, and ground voltage VSS put on selected word line WLn-1.And, read-out voltage VREAD is put on string selection wire SSL and ground selection wire GSL, and ground voltage VSS is put on common source polar curve CSL.

And bit-line voltage line BLPWR keeps ground voltage VSS, and selects the voltage level of signal BLSLTe and detection node block signal SOBLK to change into supply voltage VDD even number shielded signal SHLDe, odd number shielded signal SHLDo, even bitlines.Therefore, bit line BLe, BLe0 and BLo0 are discharged into ground voltage VSS, that is, and the data of logic " L " state.

Subsequently, in READ2 interim, even bitlines BLe0 and bit line BL0 are pre-charged to predetermined pre-charge voltage (for example, 0.8V) to detect the data value in selected memory cell MCsel.

And, in REEAD2 interim, first voltage is put on selected word line WLn-1, and second voltage is put on remaining unselected word line WL＜n-2:0.In this example, first voltage is ground voltage VSS, and second voltage is read-out voltage VREAD.Therefore, control the conduction and cut-off state of selected memory cell MCsel by being stored in wherein data.That is, if the data of storing in selected memory cell MCsel are logical ones, then selected memory cell MCsel is a conducting state, and if the storage data are logical zeroes, then selected memory cell MCsel is a cut-off state.

In READ2 interim, even number shielded signal SHLDe is changed into logic " L " state with by the nmos pass transistor 511 that is used for even bitlines BLe0 is connected to bit-line voltage line BLPWR (tR4).Therefore, discharge the discharge of even bitlines BLe0 and bit line BL0.At this moment, SHLDo remains on supply voltage VDD with the odd number shielded signal, thereby nmos pass transistor 512 keeps conducting state.Therefore, odd bit lines BLo0 is remained on ground voltage VSS, and as the shielding line work between the even bitlines BLe0.

And the voltage that will detect signalization/PLOAD in the preset time section drops to the first stand-by voltage VPRE1 from supply voltage, drops to ground voltage VSS (tR5) then.Therefore, detect transistor 860a conducting is set, thereby detection node NSEN0 is changed into supply voltage VDD, it is for being provided with voltage.

According to the example of present embodiment, the stand-by voltage VPRE1 that detects signalization/PLOAD approximately is 1.0V, and it is between ground voltage VSS and supply voltage VDD.In preset time, will detect signalization/PLOAD and remain on the first stand-by voltage VPRE1, thereby reduce owing to dashing the power noise that causes down.

In this case, bit line cut-off signals BLSHF is changed into the second stand-by voltage VPRE2, it is between supply voltage VDD and ground voltage VSS.So, detection node NSEN0 becomes each other with bit line BL0 and is connected electrically.As mentioned above, the bit line of bit line cut-off signals BLSHF gate on the second stand-by voltage VPRE2 turn-offs transistor 870a, thereby allows to provide the electric current that comes to make bit line BL0 and BLe0 be precharged to given voltage level owing to transistor 860a is set from detection.Here, given voltage level turn-offs the threshold voltage of transistor 870a than the low bit line of the second stand-by voltage VPRE2.

In addition, select the voltage level of signal BLSLTe and detection node block signal SOBLK to change into read-out voltage VREAD even bit, turn-off transistor 870a thereby there are enough electric currents to flow through bit line.

Subsequently, execution interval READ3, its neutrality line BL0 detects data and the development dataset of storing in selected memory cell MCsel.

More accurately, in READ3 interim, bit line cut-off signals BLSHF is ground voltage VSS, so that turn-off transistor 780a (tR6) by bit line.Like this, bit line BL0 becomes with detection node NSEN0 and isolates electrically, and bit line BL0 continues development dataset.

If selected memory cell MCsel is an onunit, will discharge into common source polar curve CSL in the data on the bit line BL0.Therefore, the voltage level of bit line BL0 approximately is ground voltage VSS.On the other hand, if selected memory cell is by the unit, the voltage level of bit line BL0 remain unchanged substantially (except because the variation that leakage current causes) then.

, detect transistor 860a maintenance conducting state is set in the most of the time at interval at READ3, but before READ3 finishes at interval, end (tR8) immediately.Therefore, detection node NSEN0 keeps supply voltage VDD and becomes quick condition.

Subsequently, carry out READ4 at interval, data that will on bit line BL0, develop wherein, promptly corresponding with the voltage level of bit line data are stored in the latching on the node NLAT of page-buffer NWBUF0.

Here, the quick condition of the detection node NSEN0 that initial maintenance produced in READ3 interim, and bit line cut-off signals BLSHL is changed into the 3rd stand-by voltage VPRE3, turn-off transistor 870a with the conducting bit line.

According to the example of present embodiment, the 3rd stand-by voltage VPRE3 is between ground voltage VSS and supply voltage VDD, and the predetermined voltage difference that the ratio second stand-by voltage VPRE2 is low and the detection limit is corresponding.Thereby, determine the voltage level of detection node NSEN0 according to the voltage level that on bit line BL0, develops.

In this case, the data value on the first inner incoming line IDI0 is changed into logic " H " state (tR9), thereby transmission transistor 820a is latched in conducting first.

In response to sensing latch signal LCH, latch node NLAT with data storage on detection node NSEN0 as determined by the voltage level of bit line BL0, this data are corresponding with the data of storing in selected memory cell MCsel.

That is, when selected memory cell MCsel was onunit, the voltage level of bit line BL0 and detection node NSEN0 approached ground voltage VSS.Therefore, even sensing latch signal LCH is enabled logic " H " state, also keep logic " L " state in the data that latch on the node NLAT.

On the other hand, when selected memory cell MCsel is when ending the unit, voltage level at bit line BL0 and detection node NSEN0 may be owing to the influence of leakage current when precharge voltage level descends slightly, because can not turn-off transistor 870a by the conducting bit line owing to the difference between the second and the 3rd stand-by voltage VPRE2 and VPRE3, so voltage level is remained on logic " H " state.Therefore, if sensing latch signal LCH is enabled logic " H " state, the data that then will latch on the node NLAT are turned to logic " H " state.

Subsequently, carry out READ5 at interval, bit line BL0 and detection node NSEN0 wherein reset.

In READ5 interim, SHLDe becomes supply voltage VDD with the even number shielded signal, and selects signal BLSLTe and detection node block signal SOBLK to change into supply voltage VDD from read-out voltage VREAD0 even bitlines.Therefore, bit line BL0 and detection node NSEN0 are reset to ground voltage VSS (tR11).

And, with unselected word line WL＜n-2:0 〉, string selection wire SSL and ground selection wire GSL become ground voltage VSS from read-out voltage VREAD.

Subsequently, carry out READ6 at interval, wherein (in READ4 interim store) data corresponding with latching node NLAT are outputed to overall output line GDOUT by inner output line IDOUT0.

During READ6, select address Yp0 and piece decoded signal/BLDEC with the form activation buffer of independent pulse signal.So, the data corresponding with latching node NLAT are sent to overall output line GDOUT by inner output line IDOUT0.

In the example of present embodiment, before activation block decoded signal/BLDEC, overall output line GDOUT is pre-charged to supply voltage VDD by output line pre-charge circuit (not shown).

If selected memory cell MCsel is an onunit, are logic " L " then in the data that latch on the node NLAT, therefore, the data that send on overall output line GDOUT become logic " H " state.On the other hand, if selected memory cell MCsel is by the unit, are logic " H " states then in the data that latch on the node NLAT, therefore, the data that will transmit on overall output line GDOUT discharge into logic " L " state.

Now with reference to the process flow diagram of Figure 18 program operation mode (programming mode) according to the embodiment of the invention is described.Carrying out programming mode is loaded among the selected memory cell MCsel of memory cell array with the data with input.

At step S1110, node NLAT is latched in initialization.Node NLAT be will latch by the first inner incoming line IDI0 or the second inner incoming line nIDI0 and the data of first logic state (that is logic " H " state) or the data of second logic state (that is logic " L " state) will be initialised to.In this example, will latch node NLAT by the first inner incoming line IDI0 and be initialised to the programming illegal state, it is first logic state (that is logic " H " state).

At step S1130, latch transmitting element 820 by first or second inner incoming line IDI0 or the nIDI0, will be as providing the driving voltage that latchs of the ground voltage VSS that comes to offer latch units 810 from latching driver element 825, latch units 810 is used and is latched driving voltage with first logic state (promptly, logic " H " state) or the data of second logic state (that is logic " L " state) be loaded into and latch on the node NLAT.

More particularly, if the input data are logic " H ", then buffer selects address Yp0 to become logic " H " pulse, and the first inner incoming line IDI0 also becomes logic " H " pulse.In this case, the second inner incoming line nIDI0 keeps logic " L " state.Then, latch node NLAT and keep the programming illegal state, it is logic " H " " state.

On the other hand, if the input data are logic " L ", then buffer selects address Yp0 to become logic " H " pulse, and the second inner incoming line nIDI0 also becomes logic " H " pulse.In this case, the first inner incoming line IDI0 keeps logic " L " state.To latch node NLAT then and change into logic " L " state from logic " H " state.

Therefore, in the example of present embodiment, refuse to take a passenger fashionablely when actual figure, the first inner incoming line IDI0 and the second inner incoming line nIDI0 have opposite logic state.If the data with logic " H " state when buffer selects address Yp0 to be in logic " H " state send to the first inner incoming line IDI0, then with data storage the latching on the node NLAT of logic " H " state in latch units 810.If the data with logic " H " state send to the second inner incoming line nIDI0 on the contrary, then with data storage the latching on the node NLAT of logic " L " state in latch units 810.

At step S1150, send to bit line BL0 with being loaded in the data that latch on the node NLAT.This process is described in detail below as step S1151 and S1153.

At step S1151, control buffer selected cell 850 is connected to detection node NSEN0 will latch node NLAT, and finally arrives bit line BL0.That is, buffer selects signal PBSLT to change into logic " H " voltage level, thereby the conducting buffer is selected transistor 850a.To send to detection node NSEN0 in the data that latch on the node NLAT then.

At step S1153, the control bit line turn-offs unit 870 so that detection node NSEN0 is connected with bit line BL0.More particularly, in this example, bit line cut-off signals BLSHF changes into logic " H " thereby voltage level conducting bit line turn-offs transistor 870a.To send to bit line BL0 in the data on the detection node NSEN0 then.

At step S1170, selected memory cell MCsel is programmed with corresponding with the data that are sent to bit line BL0.

Illustrate in greater detail the example of programming mode referring now to the timing diagram of Figure 19.

Figure 19 is the programming mode timing diagram, shows various signal voltages and node voltage at the non-volatile memory devices shown in the example of Figure 11 to 15.Once more will be in the following description with reference to previous drawings.

For the purpose of explaining, the timing diagram of Figure 19 is divided into eight intervals, that is, page-buffer is set at interval (being called " PROG1 at interval " afterwards), data are written at interval (being called " PROG2 at interval " afterwards), high voltage enables at interval (being called " PROG3 at interval " afterwards), bit line is set at interval (being called " PROG4 at interval " afterwards), programming execution interval (being called " PROG5 at interval " afterwards), recover (to be called " PROG6 at interval " afterwards) at interval, check readout interval (being called " PROG7 at interval " afterwards), with Y sweep spacing (being called " PROG8 at interval " afterwards).

PROG1 at interval in, before being written into the data that the outside applies, will latch node NLAT and be adjusted into the programming illegal state.In the present embodiment, the programming illegal state represents that a kind of particular data that applies for the outside does not need the state of performance element programming.In this example, when the outside applies the data of logic " H " state, do not need the unit programming.

In this example, in PROG1 interim, buffer selects address Yp0 to be in logic " H " state (tP1), thereby driving transistors 825a is latched in conducting.And because main separation is selected address Yq0 and the secondary address Yr0 both of selection is in logic " H " state, activation block decoded signal/BLDEC is to logic " L " state.In this case, the first overall incoming line nGDI is the effective impulse with logic " L " state, and the second overall incoming line nGDI is in logic " H " state.Therefore, the first inner incoming line IDI0 is the effective impulse with logic " H " state (tP2), and the second inner incoming line nIDI0 is in logic " L " state.Therefore temporary transient conducting first is latched and is sent transistor 820a, and second latchs and send transistor 820b and be in cut-off state.By this way, latch node NLAT and be set to the illegal state of programming, that is, and logic " H " state.

Carry out PROG2 subsequently at interval, wherein the data that the outside is applied are loaded into latching on the node NLAT of page-buffer NWBUF0.

In PROG2 interim,, the data storage corresponding with the data of outside input latched on the node NLAT in response to the first inner incoming line IDI0 or the second inner incoming line nIDI0.And, be provided at the data that latch the last storage of node NLAT by buffer input path RBIN1 and RBIN2.Be stored in the logic state that latchs the data on the node NLAT in response to the first inner incoming line IDI0 and be stored in the logic state that latchs the data on the node NLAT in response to the second inner incoming line nIDI0 opposite.That is, in this example, being stored in the data that latch on the node NLAT in response to the first inner incoming line IDI0 is logic " H ", is logic " L " and be stored in the data that latch on the node NLAT in response to the second inner incoming line nIDI0.

At PROG2 moment tP4 at interval, it is logic " H " that buffer is selected address Yp0.Because main separation is selected address Yq0 and the secondary address Yr0 both of selection is logic " H ", so piece decoded signal/BLDEC is logic " L ".At this moment, the first overall incoming line GDI or the second overall incoming line nGDI are changed into logic " H " state.

That is,, then the second overall incoming line nGDI is changed into logic " L " state if the input data are logic " L ".Or rather, the first inner incoming line IDI0 is changed into logic " L " state, and the second inner incoming line nIDI0 is changed into logic " H " state.Therefore, the data storage with logic " L " state is latching on the node NLAT.

On the other hand, if the input data are logic " H ", then the first overall incoming line GDI is changed into logic " L " state.Or rather, the second inner incoming line nIDI0 is changed into logic " L " state, and the first inner incoming line IDI0 is changed into logic " H " state.Therefore, the data storage with logic " H " state is latching on the node NLAT.

Carry out PROG3 subsequently at interval.Here, enable one group of high voltage pumping source (pumping) circuit (not shown) of in non-volatile semiconductor memory device, comprising.Usually, these circuit are used to produce the voltage bigger than supply voltage VDD.In the example of present embodiment, high voltage pump pump circuit group comprise be used to produce program voltage (VPGM, for example, 20V), by voltage (VPASS, for example, 7 to 9V), read-out voltage (VREAD, for example, the 5V) circuit of Denging.And high voltage pump pump circuit group can also comprise the circuit that is used to produce rising (boosting) the voltage VPP (not shown) that is used by the row decoder (not shown).For reference, the supply voltage VDD in the example of present embodiment is about 2.2V.

In PROG4 interim, adjust the even bitlines BLe0 that is connected to selected memory cell MCsel, promptly selected bit line, to latching the corresponding voltage level of storing on the node NLAT of data.And, adjust the odd bit lines BLo0 be not connected to selected memory cell MCsel, i.e. bit selecting line not is to the programming illegal state.

And in PROG4 interim, the voltage level of bit-line voltage line BLPWR is increased to supply voltage VDD (tP5).And the voltage level of even number shielded signal SHLDe and odd number shielded signal SHLDo is increased to read-out voltage VREAD (tP6).Therefore, under the situation that does not cause voltage to descend, the voltage level of even bitlines BLe0 and odd bit lines BLo0 is become supply voltage VDD, it is the voltage of bit-line voltage line BLPWR.

And even bitlines selects the voltage level of signal BLSLTe and detection node block signal SOBLK also to be increased to read-out voltage VREAD.The voltage level of bit line cut-off signals BLSHF is increased to voltage " VDD+Vt1 ".In this example, voltage " Vt1 " is the predetermined voltage of about 1.5V.

And at PROG4 moment tP7 at interval, after through the preset time section, the voltage level of even number shielded signal SHLDe is reduced to ground voltage VSS once more.And, select signal PBSLT to change into the first reference voltage V REF1 (tP8) afterwards at buffer, it changes into the 5th voltage (tP9) once more.In the example of present embodiment, the 5th voltage equals " VDD+Vt1 ", and the first reference voltage V REF1 approximately is 1.3V, and it is between ground voltage VSS and the 5th voltage.

To send to the even bitlines BLe0 that is connected in selected memory cell MCsel latching the data of storing on the node NLAT.That is, if be logic " L " latching the data of storing on the node NLAT, then the voltage of even bitlines BLe0 becomes " 0V ".And if be logic " H " latching the data of storing on the node NLAT, then bit line BLe0 remains supply voltage VDD.

Carry out PROG5 subsequently, the data storage that wherein will send to even bitlines BLe0 is in selected memory cell MCsel.

After will in the preset time section, putting on selected word line WLn-1, will put on selected word line (tP10) as the program voltage VPGM of tertiary voltage by voltage VPASS.Program voltage VPGM allows the data corresponding with the voltage level of even bitlines BLe0 (being bit line BL0) to be programmed in selected memory cell MCsel.And, will put on unselected word line WL＜n-2:0 by voltage VPASS〉(tP11).Therefore, do not select memory cell MC to keep their conducting state and be not programmed.

If being sent to the data of even bitlines BLe0 in PROG5 interim is logic " H ", then keep the programming illegal state.On the contrary, are logic " L " if be sent to the data of even bitlines BLe0, then selected memory cell MCsel is programmed by the F-N tunnel effect.Therefore, in this example, the memory of data unit MCsel that has wherein stored logic " L " state can be appointed as " programmed cells ".

And in PROG5 interim, the selection wire SSL that will go here and there changes into supply voltage VDD, and ground selection wire GSL is ground voltage VSS, and common source polar curve CSL has the voltage of about 1.5V.

Carry out PROG6 subsequently, wherein with word line WL＜n-1:0 〉, bit line BL0, BLe0 and BLo0 and detection node NSEN0 discharge into ground voltage VSS.

That is, in PROG6 interim, bit-line voltage line BLPWR keeps ground voltage VSS.And, select signal BLSLTe, detection node block signal SOBLK and bit line cut-off signals BLSHF to change into supply voltage VDD even number shielded signal SHLDe, odd number shielded signal SHLDo, even bitlines.Therefore, with word line WL＜n-1:0 〉, bit line BL0, BLe0 and BLo0 and detection node NSEN0 discharge into ground voltage VSS.

And, select signal PBSLT to change into ground voltage VSS buffer so that bit line BL0 is separated electrically from latching node NLAT.

Carry out PROG7 subsequently at interval to detect (check) data programmed in memory cell MCsel.

The operation of carrying out in PROG7 interim with before the operation carried out in the readout mode of explanation much at one.But PROG7 puts on predetermined check read-out voltage selected word line WLn-1 and can ignore resetting of page-buffer NWBUF0 with different being of readout mode at interval.Since PROG7 interim performed remaining operation similar with in readout mode those, describe in detail to avoid repetition so omitted it here.

Carry out PROG8 subsequently at interval, wherein determine whether to have used and latching the data of storing on the node NLAT selected memory cell MCsel that correctly programmed in PROG7 interim.

That is, in PROG8 interim, if be logic " H " latching the data of storing on the node NLAT, then the data with logic " L " state output to overall output line GDOUT, pass through signal thereby produce.And if are logic " L " in the data that latch on the node NLAT, then the data with logic " H " state output to overall output line GDOUT, thereby produce failure signal.

When PROG8 interim produces failure signal, repeat from PROG4 at interval to PROG8 program cycles at interval.Therefore, when producing, finish programming mode by signal.

The example of erase mode of operation (erasing mode) is described below referring now to the timing diagram of Figure 20.

Figure 20 is the erasing mode timing diagram, shows the various signal voltages and the node voltage of the non-volatile memory devices shown in the example in Figure 11 to 15.As preceding, will be in the explanation of back with reference to the figure of these fronts.

For illustrative purposes, the erasing mode timing diagram of Figure 20 is divided into six intervals, promptly wipes execution interval (be called afterwards " ERS1 at interval "), first and recover at interval (being called " ERS2 at interval " afterwards), second and recover at interval (being called " ERS3 at interval " afterwards), the first check readout interval (being called " ERS4 at interval " afterwards), the second check readout interval (being called " ERS5 at interval " afterwards) and Y sweep spacing (being called " ERS6 at interval " afterwards).

ERS1 at interval in, erasing voltage VERS is put on the integral body of memory cell MC, and the 6th voltage is put on selected word line with the memory cell obliterated data from correspondence.In this example, erasing voltage VERS approximately is 20V, and the 6th voltage approximately is 0.3V (tE1).And, the unselected word line is adjusted to quick condition.So owing to approach erasing voltage VERS (tE2) with the voltage of whole these unselected word lines of coupling.Therefore, in the memory cell that is connected to the unselected word line, do not carry out erase operation.

And in the ERS1 interval, even number shielded signal SHLDe, odd number shielded signal SHLDo, even bitlines select signal BLSLTe and odd bit lines to select signal BLSLTo change into voltage " VERS-Vt2 " (tE3 is to tE6), and detection node block signal SOBLK keeps supply voltage VDD (tE7).In this case, the threshold voltage of voltage " Vt2 " expression high voltage nmos transistor.In this example, Vt2 approximately is 1.3V.

Carry out ERS2 and ERS3 subsequently, the voltage of integral body of wherein controlling bit line BL0 and memory cell MC is to detect the data store in selected memory cell.

That is, in ERS2 interim, CSL discharges with the common source polar curve.Or rather, ERS2 is a time period, and the integral body of memory cell MC is floated and the voltage of " VERS-Vt " that charged on common source polar curve CSL discharges into ground voltage VSS during it.

And, in ERS3 interim, integral body and bit line BL0, BLe0 and BLo0 are discharged.Promptly, bit-line voltage line BLPWR is changed into ground voltage VSS (tE8), and select signal BLSLTe and odd bit lines to select signal BLSLTo change into supply voltage (tE9 is to tE12) even number shielded signal SHLDe, odd number shielded signal SHLDo, even bitlines.Therefore, bit line BL0, BLe0 and BLo0 are discharged into ground voltage VSS.

Carry out ERS4 and ERS5 subsequently at interval, wherein will latch node NLAT arbitrary non-obliterated data with detection of stored device unit MC is set.So, data among the detection of stored device unit MC and it is stored in latch on the node NLAT.

That is,, detect among the memory cell MC that is connected to even bitlines BLe0 the data that are not wiped free of in ERS1 interim after being set to logic " H " state will latching node NLAT in ERS4 interim.The operation of carrying out in ERS4 interim and class of operation performed in normal readout mode are seemingly.But, as illustrated in conjunction with readout mode in front, ERS4 at interval with normal readout mode with respect in that to latch the value that resets on the node NLAT different.That is, in normal readout mode, will latch node NLAT and reset to logic " L " state, reset to logic " H " state and will latch node NLAT in the performed operation of ERS4 interim.

In the different detections that are to carry out by the activation of the second inner incoming line nIDI0 sense data of performed operation of ERS4 interim in ERS4 interim with normal readout mode.Very similar at the remaining operation that ERS4 interim is performed with those performed in readout mode operations, therefore, omit its detailed description here to avoid repetition.

ERS5 is so a kind of time period at interval, wherein detects among the memory cell MC be connected to odd bit lines BLo0 the data of not wiping in ERS1 interim.The performed operation of ERS5 interim be not carry out the setting of latching node NLAT in that the performed operation of ERS4 interim is different.ERS5 interim performed remaining operation with very similar in those performed operations of ERS4 interim, therefore, omitted its detailed description here to avoid repetition.

Carry out ERS6 subsequently at interval, wherein use the data that detected in ERS4 and ERS5 interim and make determining about the erase operation of whether correctly having carried out memory cell MC.

If at ERS6 interim logic node NLAT is logic " H ", then the data with logic " L " state output to overall output line GDOUT, pass through signal thereby produce.On the contrary, be logic " L " if latch node NLAT, then the data with logic " H " state output to overall output line GDOUT, thereby produce failure signal.

Therefore, when producing, finish erasing mode by signal.

In ERS6 interim, when detecting memory cell for onunit at interval, latch node NLAT and keep logic " H " state about ERS4 and ERS5.If even bitlines BLe0 is connected to by unit (non-wiping), then will latchs node NLAT and discharge into ground voltage VSS in ERS4 interim.Therefore, being onunit even the memory cell MC that will be connected to odd bit lines BLo0 in ERS5 interim detects, also is logic " L " in the data that latch on the node NLAT.

Similarly, when being connected to odd bit lines BLo0 by the unit, be onunit even be connected to the memory cell MC of even bitlines BLe0, the data that latching on the node NLAT in ERS5 interim also become " L ".

Therefore, have only when even bitlines BLe0 and odd bit lines BLo0 are detected as just to produce when being connected to onunit and pass through signal.

Though for illustration purpose discloses the preferred embodiments of the present invention, it should be appreciated by those skilled in the art under the situation that does not depart from scope and spirit of the present invention, can carry out various modifications, interpolation and replacement.As just an example, though illustrate and illustrated NAND type non-volatile semiconductor memory device in this manual, but should be clearly to those skilled in the art, technology main idea of the present invention can also be applied to the non-volatile semiconductor memory device of other types, as AND N-type semiconductor N memory devices.Therefore, the technical scope of protection of the present invention must be defined by the technology main idea of appended claims.Aspect this, term " is connected to " and its similar term should not be understood that and need directly connect between element.

Claims (81)

1. the non-volatile memory devices that can operate in programming mode and readout mode comprises:

Memory cell array, it comprises a plurality of Nonvolatile memery units, many word lines and multiple bit lines;

The internal data output line is used to export the data of reading from the bit line of memory array;

Page-buffer, be connected to its operability between the bit line and internal data output line of memory cell array, wherein page-buffer comprise the detection node that optionally is connected to bit line, have the latch cicuit that latchs node that optionally is connected to detection node, be provided with the logic voltage that latchs node latch the input path with from latch the input path separate and be provided with according to the logic voltage that latchs node the internal data output line logic voltage latch outgoing route.

2. memory devices according to claim 1, wherein said internal data output line is isolated electrically from latching node.

3. memory devices according to claim 2 wherein optionally is connected to first reference potential according to the described logic voltage that latchs node with described internal data output line.

4. memory devices according to claim 3 also comprises the first transistor that is connected in series between first reference potential and the internal data output line, and the grid of wherein said the first transistor is connected to and latchs node.

5. memory devices according to claim 4 also comprises the transistor seconds that is connected in series between the first transistor and the internal data output line.

6. memory devices according to claim 5 also comprises global data bus, wherein described internal data output line optionally is connected to global data bus by the 3rd transistor.

7. memory devices according to claim 6 is wherein controlled the described second and the 3rd transistorized each conducted state by the bit line address signal.

8. memory devices according to claim 4, wherein at least by be connected in series in the described transistor seconds that latchs between the node and second reference potential partly limit latch the input path.

9. memory devices according to claim 8 is wherein controlled the conducted state of described transistor seconds by data input signal.

10. memory devices according to claim 9, wherein said data input signal is the internal data input signal, and wherein said memory devices also comprises the decoder circuit that receives bit line address signal and external data input signal and output internal data input signal.

11. memory devices according to claim 10 also comprises global data bus, wherein described internal data output line optionally is connected to global data bus via the 3rd transistor.

12. memory devices according to claim 11 is wherein controlled the 3rd transistorized conducted state by the output of described decoder circuit.

13. memory devices according to claim 10 is wherein exported the internal data input signal by decoder circuit on the internal data incoming line, and wherein with the internal data incoming line internally DOL Data Output Line isolate electrically.

14. memory devices according to claim 1, wherein said Nonvolatile memery unit is a flashing storage unit.

15. memory devices according to claim 1, wherein said memory cell array are NAND type array of flash memory cells.

16. a non-volatile memory devices comprises

Memory cell array, it comprises a plurality of Nonvolatile memery units;

Page-buffer, it comprises latch cicuit, is used for the temporary transient data of reading from the Nonvolatile memery unit of memory cell array that store and deposits the data of Nonvolatile memery unit in programming;

The internal data incoming line, data that its output is read from memory cell array and temporarily be stored in it page-buffer;

Latch the input path, it separates with the internal data output line, and when data programing being entered the Nonvolatile memery unit of memory cell array and when from the Nonvolatile memery unit sense data of memory cell array latch cicuit is set.

17. memory devices according to claim 16, wherein with described latch the input path internally Data In-Line isolate electrically.

18. memory devices according to claim 16, wherein the voltage according to latch cicuit optionally is connected to first reference potential with described internal data output line.

19. memory devices according to claim 18 also comprises global data bus, wherein according to address signal described internal data output line optionally is connected to global data bus.

20. memory devices according to claim 19, wherein said memory cell array comprises multiple bit lines, and wherein address signal is the bit line address signal.

21. memory devices according to claim 20 also comprises decoder circuit, it receives the bit line address signal and controls the selectivity connection of global data bus to the internal data output line.

22. memory devices according to claim 21, wherein said decoder circuit also receive external data input signal and output internal data input signal, and wherein control by the internal data input signal and latch the input path.

23. memory devices according to claim 16, wherein said Nonvolatile memery unit is a flashing storage unit.

24. memory devices according to claim 16, wherein said memory cell array are NAND type array of flash memory cells.

25. a non-volatile memory devices comprises:

Memory cell array, it comprises a plurality of Nonvolatile memery units;

Input data bus, its input will be programmed into the data of the Nonvolatile memery unit of memory cell array;

Output data bus, it separates with input data bus and exports the data of reading from the Nonvolatile memery unit of memory cell array;

Latch cicuit is used for the temporary transient data of reading from the Nonvolatile memery unit of memory cell array that store and deposits the data of Nonvolatile memery unit in programming;

The internal data output line, it is connected to output data bus;

Latch the input path, it is connected to input data bus, and when data programing being entered the Nonvolatile memery unit of memory cell array latch cicuit is set; With

Output driving circuit, its sense data that will temporarily be stored in the latch cicuit sends to the internal data output line.

26. non-volatile memory devices according to claim 25, wherein said output driving circuit comprise the on-off circuit that latchs the node gate by latch cicuit.

27. memory devices according to claim 26, wherein by the internal data input signal of internal data incoming line control described latch the input path, and wherein with the internal data incoming line internally DOL Data Output Line isolate electrically.

28. non-volatile memory devices according to claim 25, wherein said memory cell are the flash memory unit.

29. memory devices according to claim 25, wherein said memory cell array are NAND type array of flash memory cells.

30. a non-volatile memory devices comprises:

Memory cell array, it comprises a plurality of Nonvolatile memery units, many word lines and multiple bit lines;

The internal data output line;

A plurality of page-buffers, it is connected with memory cell array and internal data output line, arrange one after the other that wherein a plurality of page-buffers are to define a plurality of page-buffers that are arranged in juxtaposition, wherein each page-buffer comprise the latch cicuit of the data that temporary transient storage is read from memory cell array and be connected latch cicuit and the internal data output line between address gate, and wherein address gate will optionally output to the internal data output line from the data of the latch cicuit of each page-buffer in response to address signal.

31. memory devices according to claim 30 wherein one after the other is arranged in juxtaposition described page-buffer zone in assigned direction, and wherein said internal data output line longitudinal extension on assigned direction.

32. memory devices according to claim 31, wherein said bit line longitudinal extension on assigned direction.

33. memory devices according to claim 31 wherein is applied directly to described address signal the address gate of page-buffer.

34. memory devices according to claim 31 also comprises a plurality of internal data incoming lines that are connected to page-buffer, wherein with described internal data incoming line internally Data In-Line isolate electrically.

35. memory devices according to claim 31, wherein said memory cell is a flashing storage unit.

36. memory devices according to claim 31, wherein said memory cell array are NAND type array of flash memory cells.

37. a non-volatile memory devices comprises:

Memory cell array, it comprises a plurality of Nonvolatile memery units, many word lines and multiple bit lines, wherein multiple bit lines longitudinal extension on first direction;

Share the internal data output line, the data that its output is read from memory cell array;

A plurality of page-buffers are connected to each page-buffer operability between memory cell array and the shared internal data output line,

Wherein a plurality of page-buffers of arranged in succession to be being limited to a plurality of page-buffers zone of the correspondence that is arranged in juxtaposition on the first direction, and internal data output line longitudinal extension on the first direction adjacent with a plurality of page-buffers wherein.

38., also comprise the decoder circuit that is connected to many internal data incoming lines and shared internal data output line according to the described memory devices of claim 37.

39. according to the described memory devices of claim 38, wherein said decoder circuit receiver address signal and data input signal, and on many internal data incoming lines, export inner input data according to address signal and data input signal.

40. according to the described memory devices of claim 39, wherein said decoder circuit will be shared the internal data output line according to address signal and optionally be connected to overall output line.

41. according to the described memory devices of claim 37, wherein said memory cell is a flashing storage unit.

42. according to the described memory devices of claim 37, wherein said memory cell array is a NAND type array of flash memory cells.

43. a non-volatile memory devices comprises:

Memory cell array, it comprises a plurality of Nonvolatile memery units;

Page-buffer, it comprises local data's incoming line and latch cicuit, wherein latch cicuit data of reading from the Nonvolatile memery unit of memory cell array with temporary transient storage in response to local data's incoming line and will programme and deposit the data of Nonvolatile memery unit in;

The global data incoming line, it provides external input signal, and wherein external input signal comprises programming signal that is used for the program memory cells array and the control signal that is used for the readout memory cell array; With

Gate circuit, it optionally exports external input signal to local data's incoming line according to the address signal that offers gate circuit.

44. according to the described memory devices of claim 43, the latch mode of the latch cicuit of wherein said local data incoming line control page-buffer.

45. according to the described memory devices of claim 44, wherein said local data incoming line comprises being connected to and is connected in series in the first local incoming line that first of latch cicuit latchs the grid of the first transistor between node and the first node, and is connected to and is connected in series in the second local incoming line that second of latch cicuit latchs the grid of the transistor seconds between node and the first node.

46. according to the described memory devices of claim 45, also comprise the 3rd transistor that is connected in series between first node and the reference potential, wherein the 3rd transistorized grid is connected to first address signal line.

47. according to the described memory devices of claim 46, wherein said gate circuit forms the part of the decoder circuit that is connected to second address signal line.

48. according to the described memory devices of claim 44, wherein said memory cell is a flashing storage unit.

49. according to the described memory devices of claim 44, wherein said memory cell array is a NAND type array of flash memory cells.

50. a non-volatile memory devices comprises:

Memory cell array, it comprises a plurality of Nonvolatile memery units, many word lines and multiple bit lines;

The internal data output line, the data that its output is read from memory cell array;

A plurality of page-buffers are connected to its operability between memory cell array and the internal data output line; With

Many address wires are connected in to its operability at least one gate circuit in a plurality of page-buffers.

51. according to the described memory devices of claim 50, wherein at least one gate circuit comprises first address gate, and wherein each page-buffer comprise the latch cicuit of the data that temporary transient storage is read from memory cell array and be connected first reference voltage and the internal data output line between address gate, and wherein the address wire of each page-buffer of extend past is connected to first address gate of described each page-buffer.

52. according to the described memory devices of claim 51, wherein at least one gate circuit also comprises second address gate that is connected between the latch cicuit and second reference potential, and wherein the address wire of each page-buffer of extend past is also connected to second address gate of described each page-buffer.

53. according to the described memory devices of claim 50, wherein the described page-buffer of arranged in succession to be being limited to a plurality of page-buffers zone of the correspondence that is arranged in juxtaposition on the first direction, and wherein a plurality of address wire longitudinal extension on the second direction vertical with first direction.

54. according to the described memory devices of claim 53, wherein a plurality of page-buffers limit the first page-buffer piece, and wherein memory devices also is included in the second direction position adjacent to the second page-buffer piece of the first page-buffer piece, and wherein many address wires are also intersected the corresponding gate circuit that extends and be connected to more than second page-buffer of the second page-buffer piece.

55. according to the described memory devices of claim 54, wherein said internal gate output line longitudinal extension on first direction.

56., also be included in the second internal data output line of longitudinal extension on the first direction adjacent with the second page-buffer piece according to the described memory devices of claim 55.

57. according to the described memory devices of claim 50, wherein said memory cell is a flashing storage unit.

58. according to the described memory devices of claim 50, wherein said memory cell array is a NAND type array of flash memory cells.

59. comprising, a page-buffer that is used for non-volatile memory devices, this page-buffer include the latch cicuit that latchs node; The internal data incoming line, the voltage of node is latched in its control; The internal data output line, its with latch the node electrical isolation; And output driving circuit, it controls the voltage of internal data output line according to the voltage that latchs node.

60. according to the described page-buffer of claim 59, wherein said output driving circuit optionally is connected to first reference potential with the internal data output line according to the voltage that latchs node.

61., comprise also that at least one is connected in series in to latch between the node and second reference potential and transistor that comprise the grid that is connected to the internal data incoming line according to the described page-buffer of claim 59.

62. according to the described page-buffer of claim 61, wherein at least one transistor is included in and latchs the first transistor and the transistor seconds that is connected in series between the node and second reference potential, wherein control the conducted state of the first transistor, and wherein control the conducted state of transistor seconds by address wire by the internal data incoming line.

63. a non-volatile semiconductor memory device comprises:

Memory cell array, it has a plurality of electrically programmable erasable memory cells, many word lines and multiple bit lines; With

At least one page-buffer piece, it comprises a plurality of page-buffers and internal data output line, page-buffer is connected respectively to bit line, and select at least one in the address and enable in response to a plurality of buffers, the corresponding data of data on the storage of each page-buffer and its bit line that latchs at it on node, the internal data output line is shared between a plurality of page-buffers and by the data-driven on the node of latching of the page-buffer that enables, the node that latchs of internal data output line and page-buffer is isolated electrically.

64. according to the described memory devices of claim 63, wherein each page-buffer comprises:

Latch units, it has the node of latching; With

The output driver element, it is selected address in response at least one buffer and enables, this output drive unit drives internal data output line with in that to latch the data of storing on the node corresponding.

65. according to the described memory devices of claim 64, wherein each page-buffer also comprises:

The first and second internal data incoming lines; With

Latch transmitting element, it comprises by gate respectively and latchs the transmission transistor to first and second of the first and second internal data incoming lines, wherein first and second latch send transient response in the first and second internal data incoming lines so that the anti-phase voltage that latchs node that latchs node and page-buffer to be set respectively.

66. according to the described memory devices of claim 65, wherein each page-buffer also comprises and latchs driver element, this latch that driver element is selected the address in response to buffer and by gate and be used for by predetermined buffer input path provide with the outside data independence that applies latch driving voltage to latching transmitting element, wherein buffer input path and internal data output line are isolated electrically.

67. according to the described memory devices of claim 66, wherein each page-buffer also comprises the detection response unit, it provides the preset detection response voltage to latching transmitting element in response to the data on the bit line, wherein detects response voltage and enough causes the data upset of storing on the node latching.

68. according to the described memory devices of claim 67, the wherein said transmitting element that latchs comprises:

First latchs the transmission transistor, and it will latch driving voltage or detect response voltage and offer latch units in response to the data on the first internal data incoming line; With

Second latchs the transmission transistor, and it optionally will latch driving voltage or detect response voltage and offer latch units in response to the data on the second internal data incoming line.

69. according to the described memory devices of claim 68, wherein said detection response unit comprises:

Detect response transistor, its in response to the data on the bit line by gate;

Output detects transistor, and it is connected in series with detecting response transistor, and wherein output detects transient response and controls the data corresponding with the data on the bit line in the sensing latch signal that is used to select page-buffer and be stored in and latch node.

70. according to the described memory devices of claim 68, wherein each page-buffer also comprises:

Detection node, it is connected to and is used for the data corresponding with the data on the bit line are offered the bit line that detects response unit;

Detection is provided with the unit, is used to adjust detection node to voltage is set.

71. according to the described memory devices of claim 70, wherein each page-buffer comprises that also being used to control bit line turn-offs the unit to the bit line of the connection of detection node.

72. according to the described memory devices of claim 71, wherein said bit line turn-offs the unit and comprises in response to the bit line cut-off signals and turn-offed transistor so that bit line is connected with detection node by the bit line of gate.

73. according to the described memory devices of claim 72, wherein each page-buffer comprises that also control latchs the buffer selected cell that is connected of node and detection node.

74. according to the described memory devices of claim 73, wherein said buffer selected cell comprises in response to page-buffer to be selected signal and is selected transistor to latch being connected of node and detection node with control by the buffer of gate.

75. according to the described memory devices of claim 63, wherein a plurality of page-buffers that comprise in identical page-buffer piece are arranged in parallel on the first direction, and internal data output line longitudinal extension on first direction wherein.

76., also comprise according to the described memory devices of claim 63:

The first overall incoming line;

The second overall incoming line, it has in the given operation interim logic state opposite with the logic state of the first overall incoming line; With

The page-buffer demoder, it is selected address and pair selection address in response to main separation and enables, and wherein this page-buffer demoder offers the first and second internal data incoming lines with the data corresponding with the data on the first and second overall incoming lines respectively when being enabled.

77. according to the described memory devices of claim 76, wherein said page-buffer demoder comprises:

First decoder logic gates, it is selected the address and secondary selects address actuating logic computing main separation, and selects address and secondary selection address when main separation and export effective piece decoded signal when effective;

Second decoder logic gates, it enables in response to the piece decoded signal, and is used in response to the data on the first overall incoming line logic operation result being offered the first internal data incoming line; With

The 3rd decoder logic gates, it enables in response to the piece decoded signal, and is used in response to the data on the second overall incoming line logic operation result being offered the second internal data incoming line.

78. according to the described memory devices of claim 77, wherein said first decoder logic gates is the NAND door, and the described second and the 3rd decoder logic gates is the NOR door.

79., also comprise according to the described memory devices of claim 63:

Overall situation output line; With

The page-buffer demoder, it is selected address and pair selection address in response to main separation and enables, and wherein described page-buffer demoder offers overall output line with the data on the internal data output line when being enabled.

80. according to the described memory devices of claim 79, wherein said page-buffer demoder comprises:

First decoder logic gates is used for main separation is selected the address and secondary selected address actuating logic computing, and selects address and secondary selection address when main separation and export effective piece decoded signal when effective; With

The demoder transistor is used for will offering overall output line in the data on the inner output data line in response to the piece decoded signal.

81. according to the described memory devices of claim 63, wherein said memory cell array is a NAND type array of flash memory cells.

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