CN105989886A - Nonvolatile semiconductor memory device - Google Patents

Abstract

The invention provides a nonvolatile semiconductor memory device. The device is used for inhibiting breakdown of low-voltage transistors which form a bit line selection circuit. A NAND (Not AND) string unit (NU) and the transistors (BLSe, BLSo, BLASe and BIASo) which form the bit line selection circuit are formed in a P well. When an erasing action is carried out, the transistors (BLSe, BLSo, BLASe and BIASo) are set in a floating state. When an erasing voltage is applied to the P well, the transistors (BLSe, BLSo, BLASe and BIASo) are boosted. When the erasing voltage is discharged from the P well, the gates of the transistors (BLSe, BLSo, BLASe and BIASo) are connected with a reference potential through a discharge circuit (410). The gate voltage is discharged following the voltage mode of the P well.

Description

Nonvolatile semiconductor memory device

Technical field

The present invention relates to a kind of Nonvolatile semiconductor memory device, particularly relate to a kind of and non-(Not AND, is called for short NAND) type flash memory (flash memory).

Background technology

NAND type flash memory is to comprise memory block array (memory block array) and constitute, This memory block array is to form multiple NAND string (string) along column direction configuration.NAND goes here and there It is to comprise multiple memory cell (memory cell) of being connected in series and the selection crystal being connected to its two ends Manage (transistor) and constitute, one of them end company by bit line (bit line) side selection transistor Being connected to bit line, another end selects transistor to be connected to source electrode by source electrode line (source line) side Line.The reading of data (data) or programming (program) (write) are by connecing with NAND series winding Bit line carry out.

Fig. 1 is the structure chart of the bit line select circuitry of the NAND type flash memory representing prior art. Herein, even bitlines BLe and this pair of bit lines of odd bit lines BLo are shown.Bit line select circuitry 10 Have: the 1st selector 20, comprise bit line selection transistor BLC, this bit line selection transistor BLC For even bitlines BLe or odd bit lines BLo being connected to read (sence) circuit；And the 2nd Selector 30, comprises even number bias transistor (bias transistor) BIASe and odd number bias transistor BIASo, even bitlines select transistor BLSe and odd bit lines to select transistor BLSo, and this is even Number bias transistor BIASe and odd number bias transistor BIASo is used for dual numbers bit line BLe and odd number Bit line BLo applies bias-voltage VPRE, and this even bitlines selects transistor BLSe for by even bitlines BLe is connected to bit line selection transistor BLS, and this odd bit lines selects transistor BLSo for by odd number Bit line BLo is connected to bit line selection transistor BLC.This kind of bit line select circuitry 10 is connected to read electricity Road 40.Herein, the 2nd selector 30 is formed at and is formed the p-well (well) of cell array (cell array) On the different P substrate in region, when erasing move, by applying erasing electricity to selection block (p-well) Pressure, thus all bit lines boost to erasing voltage.On the other hand, owing to P substrate is 0V (ground connection (Ground, guide number D)), therefore constitute the even number bias transistor BIASe of the 2nd selector 30 And odd number bias transistor BIASo, even bitlines select transistor BLSe and odd bit lines to select crystal Pipe BLSo comprises grid (gate) thickness of oxidation film and grid length length and high pressure high voltage (High Voltage, is called for short HV) transistor.

In patent document the 1st, patent document 2 and non-patent literature 1, as in figure 2 it is shown, make bit line select The 2nd selector 30A selecting circuit 10A comprises low-voltage (Low Voltage is called for short LV) transistor, It between the 2nd selector 30A and the 1st selector 20, is provided with and comprises high voltage (HV) transistor The relay 32 of BLS.Constitute the transistor BIASe of the 2nd selector 30A, BIASo, BLSe, BLSo is formed on the block of the memory array (memory array) of NAND string location NU 50th, i.e. in p-well 60, transistor BIASe, BIASo, BLSe, BLSo be with memory cell phase Low-voltage (LV) that formed in same technique (process), that grid length is short and grid oxidation film is thin Transistor.The outside of the p-well 60 in formation memory cell array for the transistor BLS configuration of relay 32, Make the transistor BLC of the 1st selector 20 and the transistors separated of the 2nd selector 30A.By by 2 selectors 30A are set to the structure of low-voltag transistor, thus cut down shared by the 2nd selector 30A Layout (layout) area, it is achieved the miniaturization of overall memory-size (memory size).Another Aspect, when erasing move, applies erasing voltage or the erasing pulse of about about 20V to p-well 60 (pulse) grid of all transistors, but now, constituting the 2nd selector 30A is set to float (floating), the grid of transistor boosts near erasing voltage because of the Capacitance Coupled with p-well 60. Therefore, big electricity will not be applied to the grid oxidation film of transistor BIASe, BIASo, BLSe, BLSo Potential difference, thus avoid grid oxidation film puncture (break down).

Prior art literature

Patent document

Patent document 1: No. 5550609 publications of Japanese Patent No.

Patent document 2: Japanese Patent Laid-Open 2011-23661 publication

Non-patent literature 1:K. Feitian .Et al., " uses the 151mm of 24n CMOS technology²64Gb MLC nand memory ", IEEE ISSCC, technical literature summary P198-199, the 11st Phase, 2011 (K.Fukuda.Et al., " A 151mm²64Gb MLC NAND Memory in 24n, CMOS Technology”,IEEE International Solid-State Circuit Conference,Digest of Technical Paper P198-199,Session 11,2011)

Content of the invention

[inventing problem to be solved]

As described above, by by the transistor BIASe of the 2nd selector 30A, BIASo, BLSe, BLSo is formed in the block 50 i.e. p-well 60 of memory array such that it is able to cut down the 2nd selection The area occupied of portion 30A.But, the structure of this kind the 2nd selector 30A produces following problem.

When erasing move, the transistor BIASe of the 2nd selector 30A, BIASo, BLSe, BLSo is set as quick condition, the grid voltage of transistor BIASe, BIASo, BLSe, BLSo Vgate is when the erasing voltage Vers applying p-well 60 rises, because of the electricity with P-well voltage Vpw Hold coupling and gradually boost.Peak value (peak) for example, 20V of the erasing voltage Vers being applied Left and right, erasing voltage Vers keeps crest voltage within fixing period, so that from memory cell to P Trap 60 fully discharges electronics.At the end of the applying of erasing voltage Vers, P-well voltage Vpw is put Electricity, thus with this responsively, the grid voltage Vgate of transistor is also gradually reduced.

But, the grid of transistor BIASe, BIASo, BLSe, BLSo is connected with and crosses P Trap 60 and the distribution that extends, therefore grid voltage Vgate sometimes by and be positioned at immediately below distribution P-type silicon substrate or other traps between parasitic capacitance and adjacent distribution between parasitic capacitance Impact, and do not follow the reduction of P-well voltage Vpw and decline.

Fig. 3 be schematically show P-well voltage Vpw and transistor BIASe, BIASo, BLSe, The chart (graph) of the grid voltage Vgate of BLSo.P-well voltage Vpw indicated by the solid line, uses Dotted line represents grid voltage Vgate.In moment t0, the wordline (word line) to selected block WL applies 0V, and transistor BIASe, BIASo, BLSe, BLSo are set as quick condition.? Moment T1, applies erasing voltage Vers to p-well 60.For example apply voltage to p-well periodically to become Big erasing pulse.The applying of response erasing pulse, P-well voltage Vpw starts boosting.Meanwhile, Grid voltage Vgate with p-well capacity coupled transistor BIASe, BIASo, BLSe, BLSo Boosting.At moment T2, P-well voltage Vpw boosts to about 20V, in the period of moment T2～T3 In, keep the set time process that erasing is required, extract electronics from floating grid out to p-well 60.

At the period T2～T3 wiping, transistor BIASe, BIASo, BLSe, BLSo's Grid voltage Vgate is configured to below fixed potential according to the coupling ratio with p-well 60.Such as Fig. 3 Shown in, if potential difference Va of P-well voltage Vpw and the grid voltage Vgate of transistor not being set to Below fixed value, then transistor can because of time dependent behavior puncture through when dielectric breakdown characteristics (Time Dependent Dielectric Breakdown, is called for short TDDB) and destroyed.TDDB is as follows Described phenomenon: even if high voltage not being applied to the grid of transistor, if but apply voltage for a long time, Then transistor still can puncture.Therefore, in the way of meeting Va ＜ TDDB, transistor AND gate P is set Coupling ratio between trap.

At moment T3, the applying of erasing voltage Vers terminates, and P-well voltage Vpw is discharged.When opening When beginning to discharge, discharge path is connected to p-well 60, discharges electric charge by this discharge path, therefore P-well voltage Vpw comparatively quickly declines.On the other hand, transistor BIASe, BIASo, BLSe, It on the grid of BLSo, is not connected with the discharge path for discharging its electric charge, and then, on grid Being connected to the distribution with parasitic capacitance, therefore the velocity of discharge of grid voltage Vgate compares P-well voltage Vpw is slow.Its result, at moment T4, when P-well voltage Vpw reaches 0V, the grid of transistor Pole tension Vgate still be voltage Vb, if Vb ＞ TDDB, it is likely that promote transistor BIASe, BIASo, BLSe, BLSo are breakdown.

Therefore, it is an object of the invention to solve described problem of the prior art, a kind of semiconductor is provided Storage device, it is for suppressing to constitute the puncturing of low-voltag transistor of bit line select circuitry.

[solving the technological means of problem]

The semiconductor storage of the present invention includes: memory cell array, is formed with multiple and channel of a nand string, Described is that the memory cell that can electrically rewrite is connected and is formed by connecting with channel of a nand string；Erasing parts, erasing is described Memory cell in the selected block of memory cell array；And bit line select circuitry, select to divide Not with the described bit line being connected with channel of a nand string, at least 1 bit line constituting described bit line select circuitry selects Transistor is formed in trap, and described trap forms memory cell, and described erasing parts include: the 1st parts, Erasing voltage is applied to the trap of selected block；2nd parts, by shape in the trap of selected block Described at least 1 bit line selection transistor becoming is set to quick condition；And the 3rd parts, making During the tension discharge of trap of the block selecting, make described in the grid of at least 1 bit line selection transistor put Electricity is to reference potential.

Preferably, described 3rd parts are at the grid of described at least 1 bit line selection transistor and base Discharge path is generated between quasi-current potential.

Preferably, described 3rd parts comprise the 1st discharge transistor, described 1st discharge transistor For generating electric discharge road between the grid and reference potential of described at least 1 bit line selection transistor Footpath, and described 1st discharge transistor turns on when the voltage of described trap is discharged.

Preferably, described 3rd parts comprise at least 1 diode, described at least 1 diode It between the grid and reference potential of described at least 1 bit line selection transistor, is connected in series in described 1st discharge transistor.

Preferably, described at least 1 diode during discharging interior make described in the choosing of at least 1 bit line Selecting and producing fixing potential difference between the grid of transistor and described trap, described fixing potential difference is less than Described at least 1 bit line selection transistor through when dielectric breakdown.

Preferably, described 3rd parts comprise the 2nd discharge transistor and the 3rd discharge transistor, institute State the 2nd discharge transistor between described trap and reference potential generate discharge path, the described 3rd Discharge transistor for described trap with between the source electrode line that channel of a nand string is connected jointly and reference potential Generate discharge path, for the 1st discharge transistor, the 2nd discharge transistor and the 3rd discharge transistor Each grid, supply share electric discharge enable signal.

Preferably, when the voltage of described trap and the voltage of described source electrode line pass through the 2nd discharge transistor And the 3rd discharge transistor and when till being discharged to reference potential, described at least 1 diode has ratio The big threshold value of the threshold value of described at least 1 bit line selection transistor.

Preferably, described at least 1 bit line selection transistor comprises the idol for selecting even bitlines Digit line selects transistor and for selecting the odd bit lines of odd bit lines to select transistor, described idol Digit line selects transistor and described odd bit lines to select the voltage of the common points with both for the transistor It is discharged to the mode of reference potential and turn on.

Preferably, described at least 1 diode comprises at least 1 bit line selection crystalline substance described in resistance to pressure ratio The high transistor of body pipe.

Preferably, described bit line select circuitry comprises the even number bias that dual numbers bit line applies bias-voltage Transistor and the odd number bias transistor applying bias-voltage to odd bit lines, described 3rd parts make institute State even number bias transistor and each gate discharge of described odd number bias transistor.

(effect of invention)

According to the present invention, generate between the grid and reference potential of at least 1 bit line selection transistor and put Power path, therefore the grid voltage of bit line selection transistor follows the erasing voltage of p-well, even if by position Line options transistor is set to low voltage configuration, it is also possible to avoid it to puncture.

Brief description

Fig. 1 is the structure chart of the bit line select circuitry of the NAND type flash memory representing prior art；

Fig. 2 is the structure chart of the bit line select circuitry of the NAND type flash memory representing prior art；

Fig. 3 is P-well voltage and the bit line select circuitry of the NAND type flash memory representing prior art The chart of grid voltage of transistor；

Fig. 4 is the frame of an integrally-built case of the NAND type flash memory representing the embodiment of the present invention Figure；

Fig. 5 is to represent the equivalent circuit diagram that NAND goes here and there；

Fig. 6 is the summary section representing memory cell array structure；

Fig. 7 is that the even bitlines representing and constituting bit line select circuitry selects the floating of transistor and the knot of electric discharge Structure schematic diagram；

Fig. 8 is the time diagram that the time relationship to erasing voltage during erasing move and electric discharge illustrates (time chart)；

Fig. 9 is the graph of a relation of grid voltage and the P-well voltage representing the transistor constituting bit line select circuitry.

Description of reference numerals:

10th, 10A: bit line select circuitry；

20: the 1 selectors；

30th, the 30A: the 2 selector；

32: relay；

40: reading circuit；

50th, BLK (0)～BLK (m): block；

60th, 230:P trap；

100: flash memory；

110: memory array；

120: input/output (i/o) buffer；

130: address register；

140: cache memory；

150: controller；

160: word line selection circuit；

170: page buffer/reading circuit；

180: column select circuit；

190: internal voltage generating circuit；

200: system clock produces circuit；

210: silicon substrate；

220:N trap；

222:n+ diffusion zone；

250th, 260:n type diffusion zone；

270:p+ diffusion zone；

280: contact site；

290th, 292: diffusion zone；

300: drive circuit；

400: discharge circuit；

410: the 1 discharge circuits；

420: the 2 discharge circuits；

Ax: row address information；

Ay: column address information；

BIASe: even number biases transistor；

BIASo: odd number biases transistor；

BL0～BLn: bit line；

BLC: bit line selection transistor；

BLe: even bitlines；

BLo: odd bit lines；

BLS: bit line selection transistor；

BLSe: even bitlines selects transistor；

BLSo: odd bit lines selects transistor；

C1, C2, C3: control signal；

CLK: internal system time clock；

D1, D2: diode；

DEN: electric discharge enables signal；

FEN: float and enable signal；

H, L: level；

L1, L2: distribution；

MC0～MC31: memory cell；

N: node；

NU:NAND string location；

Q1: drive transistor；

Q2, Q3, Q4, Q5: discharge transistor；

SGD, SGS: select gate line；

SL: source electrode line；

T0, T1, T2, T3, T4: the moment；

TD: bit line side selects transistor；

TS: source electrode line side selects transistor；

WL0～WL31: wordline；

Va: potential difference；

Vb: voltage；

Vers: erasing voltage；

Vgate: grid voltage；

Vpass: pass through voltage；

VPRE: imagination current potential；

Vprog: program voltage；

Vpw:P trap voltage；

Vread: read-out voltage；

Vth: threshold value.

Detailed description of the invention

Hereinafter, embodiments of the present invention are described in detail with reference to the attached drawings.In addition, should be noted that, attached In figure, emphasize for the ease of understanding to represent each several part, the ratio (scale) with actual components (device) And differ.

Fig. 4 is the block diagram of a configuration example of the NAND type flash memory representing the embodiment of the present invention.As Shown in this Fig. 4, flash memory 100 includes: memory array 110, be formed be arranged in rectangular Multiple memory cell；Input/output (i/o) buffer (buffer) 120, is connected to outside input/output terminal I/O；Address register (address register) 130, receives from the ground of input/output (i/o) buffer 120 Location data；Cache memory (cache memory) 140, keeps the data of input/output；Control Device 150, generate control signal C1, C2, C3 etc., this control signal C1, C2, C3 etc. be based on From input/output (i/o) buffer 120 order data (command data) and external control signal is (not The chip of diagram enables or address latch enables (address latch enable) etc.) control each several part； Word line selection circuit 160, is decoded to row address information Ax from address register 130 (decode), and carry out the selection of block and the selection etc. of wordline based on decoded result；Page buffer / reading circuit 170, is kept the data being read by bit line, or keeps programming data by bit line Deng；Column select circuit 180, is decoded to the column address information Ay from address register 130, and Carry out the selection etc. of bit line based on this decoded result；Internal voltage generating circuit 190, generate be used for into Voltage needed for the reading of row data, programming (write) and erasing etc. (program voltage Vprog, passes through (pass) voltage Vpass, read-out voltage Vread, erasing voltage Vers (including erasing pulse etc.))； And system clock produces circuit 200, produce internal system time clock CLK.

Memory array 110 have along column direction configuration multiple block BLK (0), BLK (1) ..., BLK(m).It in one of them end of block, is configured with page buffer/reading circuit 170.But, Page buffer/reading circuit 170 can also be configured the end in both sides in another end of block or configuration Portion.

It in 1 block, is formed by connecting as it is shown in figure 5, be formed with multiple multiple memory cell are connected NAND string location NU, in 1 block, be arranged with n+1 string location NU in the row direction. String location NU includes: multiple memory cell MCi of being connected in series (i=0, the 1st ..., 31)；Bit line side Select transistor TD, be connected to one of them end i.e. memory cell MC31；And source electrode line side selects Transistor TS, is connected to another end i.e. memory cell MC0, and bit line side selects the leakage of transistor TD Pole (drain) is connected to corresponding 1 bit lines BL, and source electrode line side selects the source electrode of transistor TS to connect In shared source electrode line SL.The control gate of memory cell MCi is connected to wordline WLi, in bit line side The grid selecting transistor TD is connected with selection gate line SGD, selects transistor TS in source electrode line side On be connected with selection gate line SGS.Word line selection circuit 160 is selecting block based on row address Ax When, by selection gate line SGS, SGD of this block optionally drive selection transistor TD, TS。

Memory cell typically have metal-oxide semiconductor (MOS) (Metal Oxide Semiconductor, It is called for short MOS) structure, this MOS structure includes: as the source/drain of N-type diffusion zone, is formed In p-well；Tunnel (tunnel) oxide-film, is formed on the raceway groove (channel) of source/drain interpolar； Floating grid (charge accumulation layer), is formed on tunnel oxide film；And control gate, pass through dielectric medium Film and formed on the floating gate.When floating grid is not accumulated have electric charge when, be i.e. written with data " 1 " When, threshold value is in negative state, and the control gate of memory cell is that 0V turns on.When in floating grid When accumulation has electronics, when being i.e. written with data " 0 ", threshold transitions (shift) is just, memory cell Control gate is that 0V disconnects.Wherein, memory cell is not limited to store single position, it is possible to storage is many Individual position.

Column select circuit 180 comprises the bit line select circuitry 30A shown in Fig. 2.Bit line select circuitry 30A It is formed in the p-well of memory cell in mode described later.Preferably, bit line select circuitry 30A It is respectively formed in the p-well of each block.The action of bit line select circuitry 30A is reading, is programming, is wiping When controlled by controller 150.For example, in the case of carrying out the reading of the selected page, when When even bitlines BLe is chosen, odd bit lines BLo is non-selection, even bitlines selection transistor BLSe, Bit line selection transistor BLS turns on, and odd bit lines selects transistor BLSo to disconnect, and even number biases crystal Pipe BIASe disconnects, odd number bias transistor BIASo conducting, from imagination power supply VPRE supply shielding (shield) current potential.And, when odd bit lines BLo is chosen, even bitlines BLe is non-selection, Odd bit lines selects transistor BLSo, bit line selection transistor BLS conducting, and even bitlines selects crystal Pipe BLSe disconnects, and odd number bias transistor BIASo disconnects, even number bias transistor BIASe conducting, From imagination power supply VPRE supply screen potential.When programming, odd number bias transistor BIASo, even number Bias transistor BIASe can supply the program-inhibit voltage from imagination power supply VPRE to writing prohibition Bit line.

Table below is the table of the case representing the bias-voltage applying when each action of flash memory (table):

When reading operation, apply certain positive voltage to bit line, apply certain voltage (example to selected wordline Such as 0V), be applied through voltage Vpass (such as 4.5V) to non-selection wordline, to select gate line SGD, SGS applies positive voltage (such as 4.5V), makes bit line side select transistor TD, source electrode line side to select crystal Pipe TS turns on, and applies 0V to common source line.When programming (write) action, to selected word Line applies high-tension program voltage Vprog (15V～20V), applies middle electricity to non-selected wordline Position (such as 10V), makes bit line side select transistor TD conducting, makes source electrode line side select transistor TS Disconnect, and supply current potential corresponding with the data of " 0 " or " 1 " to bit line BL.When erasing move, 0V is applied to the selected wordline in block, applies high voltage (such as 20V) to p-well as wiping Except voltage Vers, the electronics of floating grid is drawn to substrate, in units of block, thus wipes data.

Fig. 6 is the summary section representing memory cell array, should be noted that, herein the company of illustrate only It is connected to the even number of the NAND string location NU and composition bit line select circuitry 30A of even bitlines BLe Bit line selection transistor BLSe and even number bias transistor BIASe.Shape in the silicon substrate 210 of p-type Become N trap 220, in N trap 220, form p-well 230.1 p-well 230 corresponds to 1 block, Form the transistor constituting NAND string location NU in p-well 230.And then, in p-well 230, The even bitlines forming the 2nd selector 30A shown in pie graph 2 selects transistor BLSe and even number inclined Piezoelectric crystal BIASe.

Source electrode line SL is connected to the N-shaped diffusion zone 250 that source electrode line side selects transistor TS, even bit Line BLe is connected to the N-shaped diffusion zone 260 that bit line side selects transistor TD.The p+ of p-well 230 expands The n+ diffusion zone 222 dissipating region 270 with N trap 220 is connected to the contact site that N trap/p-well shares (contact)280.The contact site 280 sharing is connected to internal voltage generating circuit 190, for example, wiping It is applied in erasing voltage Vers during except action, or made the tension discharge of p-well by contact site 280. And, even bitlines BLe is connected to diffusion zone 290, and this diffusion zone 290 is formed in p-well 230 The even bitlines being formed selects the common points of transistor BLSe and even number bias transistor BIASe, Imagination power supply VPRE is connected to another diffusion zone 292 of even number bias transistor BIASe.Even number Bit line selection transistor BLSe and even number bias transistor BIASe is by the work identical with memory cell The N-type MOS transistor of the low-voltage that skill is formed.

Fig. 7 is the figure representing discharge circuit and the drive circuit being connected to bit line select circuitry.Wherein should stay Meaning, has been shown here only and has selected transistor BLSe with the even bitlines constituting bit line select circuitry 30A The discharge circuit connecting and drive circuit.PW in Fig. 7 refers to p-well.Constitute bit line select circuitry 30A Other odd bit lines select transistor BLSo, even number bias transistor BIASe and odd number bias crystal Pipe BIASo is connected to select the discharge circuit as transistor BLSe and drive circuit with even bitlines.

Column select circuit 180 comprises drive circuit 300 and discharge circuit 400.Drive circuit 300 and putting Electricity circuit 400 is formed in the silicon substrate of p-type, or is formed in the trap different from p-well 230.? It with on the node N that even bitlines selects the grid of transistor BLSe to be connected, is connected with by distribution L1 Drive circuit 300.Drive circuit 300 comprises the driving transistor Q1 being connected to the N-type of node N.? Drive on the grid of transistor Q1, be connected with floating and enable signal FEN, in the phase carrying out erasing move Interior, enable of floating signal FEN migrates to L level (level), drives transistor Q1 to disconnect.Thus, Even bitlines selects transistor BLSe to be set as quick condition.In addition, drive circuit 300 is when reading Or be suitably driven driving transistor Q1 during programming, but the description thereof will be omitted herein.

And then, it on the grid that even bitlines selects transistor BLSe, is connected with puts by distribution L2 Electricity circuit 400.Discharge circuit 400 includes making even bitlines select transistor BLSe's when erasing move 1st discharge circuit 410 of gate discharge and make p-well the 230th, source electrode line SL and imagination power supply VPRE The 2nd discharge circuit 420 of node discharge.

1st discharge circuit 410 includes and 2 that even bitlines selects the gate series of transistor BLSe to be connected Individual diode D1, D2 and discharge transistor Q2.Discharge transistor Q2 be connected to diode D2 with It between reference potential (GND), is connected with electric discharge on its gate and enables signal DEN.When electric discharge enables When signal DEN is set to H level, discharge transistor Q2 turns on, and even bitlines selects transistor BLSe Grid be electrically connected to reference potential by distribution L2, between node N and reference potential generate electric discharge Path.

Diode D1, D2 are respectively provided with threshold value Vth, by 2 diodes D1, D2 are connected in series, Thus the grid of dual numbers bit line selection transistor BLSe applies the electricity partially from reference potential skew 2Vth Pressure.Diode D1, D2, when P-well voltage Vpw is discharged, make the voltage follower p-well of node N Voltage Vpw, substantially diminishing 2Vth from P-well voltage Vpw, and when P-well voltage Vpw is discharged to greatly When causing 0V, even bitlines is made to select transistor BLSe conducting.In this example, by 2 diode D1, D2 is connected in series, but this is a case, and the quantity of diode may not be defined in this.Number for diode For amount, as long as the difference of node N and P-well voltage Vpw is below the breakdown voltage of TDDB and ratio Even bitlines selects the big value of the threshold value of transistor BLSe.In addition, diode D1, D2 and put Electric transistor Q2 comprises voltage ratio even bitlines and selects the high transistor of transistor BLSe.

2nd discharge circuit 420 comprises to be connected to the discharge transistor Q3 of p-well 230, is connected to source electrode line The discharge transistor Q4 of SL and the discharge transistor Q5 being connected to imagination power supply VPRE.At electric discharge crystal It on each grid of pipe Q3, Q4, Q5, is jointly connected with electric discharge and enables signal DEN, when electric discharge enables letter When number DEN is H level, discharge transistor Q3, Q4, Q5 turn on, p-well the 230th, source electrode line SL, Imagination current potential VPRE is electrically connected to reference potential, discharges.Discharge transistor Q3, Q4, Q5 bag Even bitlines containing voltage ratio selects the high transistor of transistor BLSe.

It follows that the erasing move of the present embodiment is described with reference to the time diagram of Fig. 8.When from outside master When machine (host) device is to flash memory 100 transmission erasing order and row address etc., controller 150 The block that selection should be wiped, performs erasure sequence (sequence).At moment T0, drive circuit 300 will Enable of floating signal FEN migrates to L level, makes driving transistor Q1 disconnect.Thus, selected Transistor BIASe, BIASo, BLSe, BLSo in the p-well 230 of block become quick condition.And And, the bit line side of selected block selects transistor TD and source electrode line side to select transistor TS to be set as Quick condition, applies 0V to wordline.Then, at moment T1, by internal voltage generating circuit 190 institute The erasing voltage Vers producing is applied to p-well 230 and N trap 220 by contact site 280.With wiping Except the applying of voltage Vers, P-well voltage Vpw reaches about 20V at moment T2～T3, during this period, The memory cell of selected block is wiped free of.At moment T3, terminate the applying of erasing voltage Vers, Moment T3～T4, electric discharge enables signal DEN and migrates to H level, discharge transistor Q2, Q3, Q4, Q5 turns on.Thus, each grid and the benchmark electricity at transistor BIASe, BIASo, BLSe, BLSo Discharge path is generated between Wei, and then, at p-well the 230th, source electrode line SL, imagination power supply VPRE and base Discharge path is generated between quasi-current potential, each grid of transistor BIASe, BIASo, BLSe, BLSo, P-well, source electrode line SL, imagination power supply VPRE are discharged by each discharge path.

Fig. 9 is the grid representing P-well voltage Vpw and transistor BIASe, BIASo, BLSe, BLSo The figure of the relation of pole tension Vgate.As explanation in Fig. 8, at moment T3, erasing voltage Vers executes Adding end, meanwhile, electric discharge enables signal DEN and becomes effectively (active), p-well, source electrode line SL, vacation Think the electric charge of each grid of power supply VPRE and transistor BIASe, BIASo, BLSe, BLSo by putting Power path and be discharged to reference potential.

The grid voltage Vgate of transistor BIASe, BIASo, BLSe, BLSo because of with p-well 230 Capacitance Coupled and decline, in addition, because of distribution L2, diode D1, D2 and discharge transistor Q2 The generation of discharge path and promote electric discharge.Grid voltage Vgate will not with the potential difference with p-well 230 The mode exceeding about 2Vth follows P-well voltage Vpw.That is, the electric discharge slope of grid voltage Vgate is big Cause to be similar to the electric discharge slope of P-well voltage Vpw, follow P-well voltage Vpw with the difference of 2Vth.Cause And, interior during discharging, the voltage applying transistor BIASe, BIASo, BLSe, BLSo is to become Obtain the little mode of breakdown voltage than TDDB and be controlled.

And, at moment T4, P-well voltage Vpw, source electrode line SL, the node of imagination power supply VPRE Till being discharged to substantially 0V.On the other hand, the grid of transistor BIASe, BIASo, BLSe, BLSo Till pole tension Vgate is discharged to about 2Vth by diode D1, D2.Herein, if even bitlines Transistor BLSe and odd bit lines is selected to select the electric discharge of common points BLn of transistor BLSo slow, And causing its voltage to maintain high state, then the even bitlines of low-voltage selects transistor BLSe and odd number Bit line selection transistor BLSo is likely to occur and punctures.But, if P-well voltage Vpw becomes 0V, Then the voltage of bit line BL also will become 0V, if grid voltage Vgate is 2Vth, then even bitlines selects Transistor BLSe and odd bit lines select transistor BLSo conducting, the therefore electrical connection of common points BLn In GND, the tension discharge of common points BLn therefore can be made to about 0V.

So, according to the present embodiment, when erasing move, the transistor of bit line select circuitry 30A is made Each grid of BIASe, BIASo, BLSe, BLSo boosts by the Capacitance Coupled with p-well 230, Subsequently, when making P-well voltage discharge, each grid is made to lead in the way of the electric discharge following P-well voltage Overdischarge path and discharge, transistor BIASe, BIASo, BLSe, BLSo therefore can be suppressed because of TDDB Deng and the phenomenon that punctures.

In addition, in described embodiment, show that memory cell stores the example of the data of 1, but store Unit also can store the data of multidigit.And then, in described embodiment, show that NAND string is formed at base The example on plate surface, but NAND string also can three-dimensionally be formed at substrate surface.

As described above, have been described in detail the preferred embodiment of the present invention, but the present invention is not limited to Specific embodiment, can carry out various deformation, change in the range of the purport of the present invention.

Last it is noted that various embodiments above is only in order to illustrating technical scheme, rather than right It limits；Although the present invention being described in detail with reference to foregoing embodiments, this area common Skilled artisans appreciate that it still can the technical scheme described in foregoing embodiments be modified, Or equivalent is carried out to wherein some or all of technical characteristic；And these modifications or replacement, and The essence not making appropriate technical solution departs from the scope of various embodiments of the present invention technical scheme.

Claims (10)

1. a semiconductor storage, it is characterised in that include:

Memory cell array, is formed with multiple and channel of a nand string, and described is the storage list that can electrically rewrite with channel of a nand string Unit is connected in series；

Erasing parts, wipe the memory cell in the selected block of described memory cell array；And

Bit line select circuitry, select respectively with the described bit line being connected with channel of a nand string,

At least 1 bit line selection transistor constituting described bit line select circuitry is formed in trap, described trap Form memory cell,

Described erasing parts include:

1st parts, apply erasing voltage to the trap of selected block；

2nd parts, will at least 1 bit line selection transistor described in formation in the trap of selected block It is set to quick condition；And

3rd parts, when making the tension discharge of trap of selected block, make described at least 1 bit line Select the gate discharge of transistor to reference potential.

2. semiconductor storage according to claim 1, it is characterised in that

Described 3rd parts are raw between the grid and reference potential of described at least 1 bit line selection transistor Become discharge path.

3. semiconductor storage according to claim 1 and 2, it is characterised in that

Described 3rd parts comprise the 1st discharge transistor, described 1st discharge transistor for described extremely Generate discharge path between the grid of few 1 bit line selection transistor and reference potential, and the described 1st puts Electric transistor turns on when the voltage of described trap is discharged.

4. semiconductor storage according to claim 3, it is characterised in that

Described 3rd parts comprise at least 1 diode, and described at least 1 diode is described at least 1 It between the grid of individual bit line selection transistor and reference potential, is connected in series in described 1st discharge transistor.

5. semiconductor storage according to claim 4, it is characterised in that

Described at least 1 diode during discharging interior make described in the grid of at least 1 bit line selection transistor Producing fixing potential difference between pole and described trap, described fixing potential difference is less than described at least 1 position Line options transistor through when dielectric breakdown.

6. semiconductor storage according to claim 1 and 2, it is characterised in that

Described 3rd parts comprise the 2nd discharge transistor and the 3rd discharge transistor, described 2nd electric discharge crystalline substance Body pipe is for generating discharge path between described trap and reference potential, and described 3rd discharge transistor is used for With described trap with between the source electrode line that channel of a nand string is connected jointly and reference potential generate discharge path, for Each grid of the 1st discharge transistor, the 2nd discharge transistor and the 3rd discharge transistor, supply shares Electric discharge enables signal.

7. semiconductor storage according to claim 6, it is characterised in that

When the voltage of described trap and the voltage of described source electrode line pass through the 2nd discharge transistor and the 3rd electric discharge crystalline substance Body pipe and when till being discharged to reference potential, described at least 1 diode has than described at least 1 position The big threshold value of the threshold value of line options transistor.

8. semiconductor storage according to claim 6, it is characterised in that

Described at least 1 bit line selection transistor comprises for selecting the even bitlines of even bitlines to select crystalline substance Body pipe and for select odd bit lines odd bit lines select transistor, described even bitlines select crystal Pipe and described odd bit lines select the side of the tension discharge of the common points with both for the transistor to reference potential Formula and turn on.

9. semiconductor storage according to claim 1 and 2, it is characterised in that

Described at least 1 diode comprises the high crystal of at least 1 bit line selection transistor described in resistance to pressure ratio Pipe.

10. semiconductor storage according to claim 1 and 2, it is characterised in that

Described bit line select circuitry comprises the even number bias transistor and right that dual numbers bit line applies bias-voltage Odd bit lines applies the odd number bias transistor of bias-voltage, and described 3rd parts make described even number bias crystal Pipe and each gate discharge of described odd number bias transistor.