CN100524770C - Layout structure of non-volatile memory - Google Patents
Layout structure of non-volatile memory Download PDFInfo
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- CN100524770C CN100524770C CNB2006100864305A CN200610086430A CN100524770C CN 100524770 C CN100524770 C CN 100524770C CN B2006100864305 A CNB2006100864305 A CN B2006100864305A CN 200610086430 A CN200610086430 A CN 200610086430A CN 100524770 C CN100524770 C CN 100524770C
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Abstract
The layout structure of non-volatile includes following parts: substrate; multiple flush type bit lines along row direction; multiple transistors as memory cells; multiple word lines along column direction, multiple contact windows of bit line; and at least two virtual word lines. Being located at the substrate, an isolation structure defines out drive region. Flush type bit lines are located at substrate of the drive region. Being setup at the substrate, transistors arranged in 2D array are located between flush type bit lines. Each word line is connected to each transistor in same column in series. Contact windows of bit line are located on flush type bit lines. Being parallel in word lines, two virtual word lines are positioned on the isolation structure at two sides of the drive region.
Description
Technical field
The invention relates to a kind of layout structure of semiconductor subassembly, and particularly relevant for a kind of layout structure of non-voltile memory.
Background technology
Along with science and technology development with rapid changepl. never-ending changes and improvements, when the function of computer microprocessor more and more stronger, when program that software carried out and computing are more and more huger, the demand of internal memory is also just more and more higher, particularly about requirement to the accuracy of the layout guideline (layout rules) of memory subassembly, in order to make the trend that satisfies this demand, improve the technology of making memory subassembly, become semiconductor science and technology and continued toward the actuating force of high integration challenge.
Generally speaking, in the manufacture process of whole memory array, have many variance factors, can cause bad influence the yield and the reliability thereof of processing procedure.For instance, because the restriction of photoetching process, can make the assembly of fringe region of memory array and critical size (the Critical Dimension of its central area assembly, CD) produce deviation (bias), directly or indirectly cause defective (as leakage current, short circuit etc.), influence the yield and the reliability thereof of processing procedure.Therefore, how to avoid above-mentioned because of processing procedure limits the variety of problems of deriving, be the direction that industry is endeavoured to develop always.
Summary of the invention
The object of the present invention is to provide a kind of layout structure of non-voltile memory, can avoid the problem of aforementioned key size deviation, and can improve lithographic process window, and can save arrangement space.
For achieving the above object, the layout structure of non-voltile memory provided by the invention comprises:
One substrate have an isolation structure in this substrate, and this isolation structure defines an active area;
Many embedded type bit line of line direction are arranged in this substrate of this active area;
As a plurality of transistors of memory cell, on this substrate between described a plurality of embedded type bit line, and be arranged in two-dimensional array;
Many character lines of column direction, wherein each character line described a plurality of transistors of same row of connecting;
A plurality of character line contact holes, alternate configurations is in first end and second end of described a plurality of character lines;
Article at least two, the virtual character line lays respectively on this isolation structure of these active area both sides, and is arranged in parallel with described a plurality of character lines; And
A plurality of bit line contacting windows are on the described a plurality of embedded type bit line between described a plurality of virtual character lines and the described a plurality of character line.
The layout structure of described non-voltile memory, wherein each described a plurality of isolation structure comprises shallow slot isolation structure or field oxide.
The layout structure of described non-voltile memory, wherein each described a plurality of embedded type bit line comprises a doped region.
The layout structure of described non-voltile memory, the material of wherein said a plurality of character lines and this two virtual characters line comprises doped polycrystalline silicon.
The present invention proposes a kind of layout structure of non-voltile memory in addition, and it comprises:
One substrate have an isolation structure in this substrate, and this isolation structure defines an active area;
Many embedded type bit line of line direction are arranged in this substrate of this active area;
As a plurality of transistors of memory cell, on this substrate between described a plurality of embedded type bit line, and be arranged in two-dimensional array;
Many character lines of column direction, wherein each character line described a plurality of transistors of same row of connecting;
A plurality of character line contact holes, alternate configurations is in first end and second end of described a plurality of character lines;
A plurality of bit line contacting windows are on the described a plurality of embedded type bit line between described a plurality of character lines; And
Article at least two, the virtual character line lays respectively on this isolation structure of these active area both sides, and is arranged in parallel with described a plurality of character lines.
The layout structure of described non-voltile memory, wherein each described a plurality of isolation structure comprises shallow slot isolation structure or field oxide.
The layout structure of described non-voltile memory, wherein each described a plurality of embedded type bit line comprises a doped region.
The layout structure of described non-voltile memory, the material of wherein said a plurality of character lines and this two virtual characters line comprises doped polycrystalline silicon.
In other words, the layout structure of non-voltile memory provided by the invention, it comprises: many embedded type bit line of substrate, line direction, a plurality of transistors as memory cell, many character lines of column direction, a plurality of bit line contacting window, a plurality of character line contact hole and at least two virtual character lines.Wherein, have an isolation structure in the substrate, and isolation structure defines an active area.Embedded type bit line is arranged in the substrate of active area.Transistor and is arranged in two-dimensional array on the substrate between each embedded type bit line.The connect transistor of same row of each bar character line.Article at least two, the virtual character line lays respectively on the isolation structure of active area both sides, and is arranged in parallel with character line.In addition, a plurality of character line contact hole alternate configurations are in first end and second end of each character line; Bit line contacting window is on the embedded type bit line between virtual character line and the character line.
Described according to preferred embodiment of the present invention, above-mentioned isolation structure for example is shallow slot isolation structure or field oxide.
Described according to preferred embodiment of the present invention, each above-mentioned embedded type bit line for example is a doped region.
Described according to preferred embodiment of the present invention, the material of above-mentioned character line and virtual character line for example is a doped polycrystalline silicon.
The present invention proposes a kind of layout structure of non-voltile memory in addition, and it comprises: many embedded type bit line of substrate, line direction, a plurality of transistors as memory cell, many character lines of column direction, a plurality of bit line contacting window, a plurality of character line contact hole and at least two virtual character lines.Wherein, have an isolation structure in the substrate, and isolation structure defines an active area.Embedded type bit line is arranged in the substrate of active area.Transistor and is arranged in two-dimensional array on the substrate between each embedded type bit line.The connect transistor of same row of each bar character line.Bit line contacting window is on the embedded type bit line between the character line.A plurality of character line contact hole alternate configurations are in first end and second end of a plurality of character lines.In addition, at least two virtual character lines lay respectively on the isolation structure of active area both sides, and are arranged in parallel with character line.
Described according to preferred embodiment of the present invention, above-mentioned isolation structure for example is shallow slot isolation structure or field oxide.
Described according to preferred embodiment of the present invention, each above-mentioned embedded type bit line for example is a doped region.
Described according to preferred embodiment of the present invention, the material of above-mentioned character line and virtual character line for example is a doped polycrystalline silicon.
Therefore layout structure of the present invention is a configuration virtual character line on isolation structure, can avoid the problem of character line and the critical size generation deviation of the character line of its central area of the fringe region of active area.In addition, virtual character line of the present invention is to be disposed on the isolation structure, but not on the active area, therefore can not take the usable floor area of assembly, can save the processing procedure cost.In addition, virtual character line of the present invention below can not form transistor, therefore can not produce problem or other spin-off effects of leakage current, nor can the electrical property efficiency of assembly be impacted.
Description of drawings
Fig. 1 is the top view according to the layout structure of the non-voltile memory that one embodiment of the invention illustrated.
Fig. 2 is the top view according to the layout structure of the non-voltile memory that another embodiment of the present invention illustrated.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Fig. 1 is the top view according to the layout structure of the non-voltile memory that one embodiment of the invention illustrated.Have 3 memory cell in Fig. 1 in each column of memory cells, right the present invention is not limited thereto.
Please refer to Fig. 1, the layout structure of the non-voltile memory of present embodiment mainly includes: many embedded type bit line of substrate 100, line direction (buried bit line) 102, as a plurality of transistors 104 of memory cell, many character lines of column direction (word line) 106 and virtual character line (dummyword line) 108.Wherein, line direction is vertical with column direction usually.Has an isolation structure 110 in the substrate 100, to define active area 112.This isolation structure 110 for example be shallow slot isolation structure (shallow trench isolation, STI) or field oxide (field oxide, FOX).Embedded type bit line 102 is disposed in the substrate 100 of active area 112, and wherein each bar embedded type bit line 102 for example is a doped region.In addition, transistor 104 and is arranged in two-dimensional array (2D array) on the substrate 100 between each embedded type bit line 102.Each transistor 104 is as a memory cell, it can comprise a grid structure of character line 106 belows and the part (as source/drain region) of two embedded type bit line 102 that are adjacent, or comprises the part (as grid) between two adjacent embedded type bit line 102 of a character line 106 and the part (as source/drain region) of this two embedded type bit line 102.
In addition, each transistor 104 of the same row of each bar character line 106 series connection.The material of character line 106 for example is a doped polycrystalline silicon.In addition, there are a plurality of bit line contacting windows 114 to be disposed on the flush type character line 102 at active area 112 edges, and electrically connect with embedded type bit line 102.The layout structure of the non-voltile memory of present embodiment also can comprise a plurality of character line contact holes 116, it is first end and second end of the character line 106 of alternate configurations on isolation structure 110, in order to electrically connect the plain conductor (do not illustrate) of character line 106 to the upper strata.
In addition, virtual character line 108 has two at least, lays respectively on the isolation structure 110 of active area 112 both sides, and is arranged in parallel with character line 106.The material of this virtual character line 108 for example is a doped polycrystalline silicon.In addition, the bit line contacting window 114 on the above-mentioned flush type character line 102 that is disposed at active area 112 edges promptly is between virtual character line 108 and character line 106.
What be worth detailed description is, critical size (critical dimension except the character line of the character line of the fringe region that can avoid active area and its central area, CD) produce deviation (bias) problem outside, virtual character line of the present invention is to be disposed on the isolation structure, but not on the active area, therefore can not take the usable floor area of assembly, can save the processing procedure cost.
On the other hand, virtual character line of the present invention is to be disposed on the isolation structure, below the virtual character line, can not form transistor, therefore can not produce problem or other spin-off effects (side-effect) of leakage current (leakage), nor can the electrical property efficiency of assembly be impacted.
Fig. 2 is the top view according to the layout structure of the non-voltile memory that another embodiment of the present invention illustrated.In Fig. 2, the member identical with Fig. 1 is to represent with same label.
Please refer to Fig. 2, what this another embodiment was different with the foregoing description is, its bit line contacting window 114a is on the embedded type bit line between the character line 106 102, but not is disposed on the flush type character line 102 between active area 112 edge virtual character lines 108 and the character line 106.Therefore, the distance between virtual character line 108 and the character line 106 can comparatively shorten, and therefore can improve lithographic process window (window).
In sum, the present invention has following advantage at least:
1. layout structure of the present invention can avoid the critical size of the character line of the character line of fringe region of active area and its central area to produce the problem of deviation.
2. layout structure of the present invention is simply and not numerous and diverse, and it is to be to be disposed on the isolation structure with the virtual character line, but not on the active area, therefore can not take the usable floor area of assembly, can save the processing procedure cost.
3. layout structure of the present invention does not dispose transistor below the virtual character line, therefore can not produce problem or other spin-off effects of leakage current, nor can the electrical property efficiency of assembly be impacted.
4. layout structure of the present invention also can only be disposed at bit line contacting window on the embedded type bit line between the character line, therefore can improve lithographic process window.
Though the present invention describes as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this technical staff, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking content that claim defines.
Claims (8)
1. the layout structure of a non-voltile memory comprises:
One substrate have an isolation structure in this substrate, and this isolation structure defines an active area;
Many embedded type bit line of line direction are arranged in this substrate of this active area;
As a plurality of transistors of memory cell, on this substrate between described a plurality of embedded type bit line, and be arranged in two-dimensional array;
Many character lines of column direction, wherein each character line described a plurality of transistors of same row of connecting;
A plurality of character line contact holes, alternate configurations is in first end and second end of described many character lines;
Article at least two, the virtual character line lays respectively on this isolation structure of these active area both sides, and is arranged in parallel with described many character lines; And
A plurality of bit line contacting windows are on described many embedded type bit line between described at least two virtual character lines and described many character lines.
2. the layout structure of non-voltile memory as claimed in claim 1, wherein said isolation structure comprises shallow slot isolation structure or field oxide.
3. the layout structure of non-voltile memory as claimed in claim 1, wherein each described many embedded type bit line comprises a doped region.
4. the layout structure of non-voltile memory as claimed in claim 1, the material of wherein said many character lines and these at least two virtual character lines comprises doped polycrystalline silicon.
5. the layout structure of a non-voltile memory comprises:
One substrate have an isolation structure in this substrate, and this isolation structure defines an active area;
Many embedded type bit line of line direction are arranged in this substrate of this active area;
As a plurality of transistors of memory cell, on this substrate between described many embedded type bit line, and be arranged in two-dimensional array;
Many character lines of column direction, wherein each character line described a plurality of transistors of same row of connecting;
A plurality of character line contact holes, alternate configurations is in first end and second end of described many character lines;
A plurality of bit line contacting windows are on described many embedded type bit line between described many character lines; And
Article at least two, the virtual character line lays respectively on this isolation structure of these active area both sides, and is arranged in parallel with described many character lines.
6. the layout structure of non-voltile memory as claimed in claim 5, wherein said isolation structure comprises shallow slot isolation structure or field oxide.
7. the layout structure of non-voltile memory as claimed in claim 5, wherein each described many embedded type bit line comprises a doped region.
8. the layout structure of non-voltile memory as claimed in claim 5, the material of wherein said many character lines and these at least two virtual character lines comprises doped polycrystalline silicon.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100864305A CN100524770C (en) | 2006-06-19 | 2006-06-19 | Layout structure of non-volatile memory |
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| CNB2006100864305A CN100524770C (en) | 2006-06-19 | 2006-06-19 | Layout structure of non-volatile memory |
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| CN101093834A CN101093834A (en) | 2007-12-26 |
| CN100524770C true CN100524770C (en) | 2009-08-05 |
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| WO2018106233A1 (en) * | 2016-12-07 | 2018-06-14 | Intel Corporation | Integrated circuit device with crenellated metal trace layout |
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