CN100524669C - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN100524669C CN100524669C CNB200610089954XA CN200610089954A CN100524669C CN 100524669 C CN100524669 C CN 100524669C CN B200610089954X A CNB200610089954X A CN B200610089954XA CN 200610089954 A CN200610089954 A CN 200610089954A CN 100524669 C CN100524669 C CN 100524669C
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- Engineering & Computer Science (AREA)
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Abstract
The invention discloses a semiconductor element and preparing method, which comprises the following steps: a. forming metal film on the silicon substrate; b. forming film multi-layer substrate with conductive layer and insulating layer in multiple-level plane on the metal film; c. attaching support component on the film multi-layer substrate through adhesive component; d. removing silicon substrate and metal film; e. integrating film multi-layer substrate and support component; f. assembling the multi-layer substrate on the packing substrate to fix; g. reducing coherence of adhesive component to strip support component and adhesive component from multi-layer substrate; h. assembling at least one semiconductor chip on the multi-layer substrate.
Description
The application is that the name submitted on March 14th, 2003 is called the dividing an application of application for a patent for invention No.03120430.9 of " semiconductor device and manufacture method thereof ".
Technical field
Present invention relates in general to a kind of semiconductor device, relate in particular to a kind of manufacture method of semiconductor device, the micro-structural insert structure (interposer) that this semiconductor device utilization adopts silicon substrate to make encapsulates.
Background technology
In the semiconductor device of the above-mentioned type, semiconductor chip is installed on the insert structure.Therefore, along with having meticulousr and the more latest development of the semiconductor chip of thin structure, making great efforts to provide insert structure with thinner meticulousr structure (wiring substrate or reset substrate (rearranging substrate)).Insert structure is normally by forming insulating barrier and making as the lamination of the conductive layer of interconnection.
In recent years, the photoetching technique that has proposed to adopt the retrofit technology for example to be used in the semiconductor chip manufacturing equipment is made insert structure.In general, in this insert structure manufacturing process that adopts photoetching technique, interconnection pattern and insulating barrier are layered on the side of silicon substrate, and the pad of outside connection terminal (land) is formed on another side of silicon substrate.Being in pad (land) on the opposite sides of silicon substrate and interconnection pattern is electrically connected by the through hole that passes silicon substrate and form.
By using silicon substrate, the similar mode of technology that the wiring pattern of insert structure and insulating barrier could adopt and make semiconductor chip forms.Therefore, such advantage is to form the insert structure of meticulous and sandwich construction.
According to the above-mentioned insert structure manufacture method that adopts silicon chip, must carry out in silicon substrate, forming through hole so that the step of the through hole of the front of formation connection insert structure and side, must carry out insulation processing, wherein the SiO2 layer is formed on the inner surface of these through holes, and fills these through holes with coating.This silicon substrate has certain thickness, so that keep enough intensity during this insert structure manufacture process.Therefore, for the through hole that forms the silicon substrate that runs through such and on the inner surface of these through holes, insulate and electroplating processes, then to use expensive equipment and increase process time.This causes the manufacturing cost of insert structure to increase.
The setting of silicon substrate self is used for keeping intensity, and is unnecessary for the function of insert structure.But, because silicon substrate thickness itself is greater than the thickness of wiring pattern and insulating barrier, so the integral thickness of insert structure becomes relatively large owing to the thickness of silicon substrate.
In addition, in the processing step that electrodeposited coating is filled in the through hole, be difficult to prevent to occur the space technically in electrodeposited coating, these spaces can cause conductivity to descend and reliability reduces.
In addition, because silicon substrate is extremely thin, so be difficult to during manufacture process, insert structure be handled as a monomer.
Also have, silicon substrate be provided be attached to one on the side insert structure and be attached in the semiconductor device of the insulating barrier on the opposite side, the problem of existence is that insert structure self may warpage.In this case, be difficult on insert structure, install LSI chip with little spaced electrodes.
Summary of the invention
Therefore, overall purpose of the present invention is to provide a kind of method, semi-conductor device manufacturing method that can eliminate the problems referred to above.
Of the present invention another more specifically purpose be to provide a kind of method, semi-conductor device manufacturing method with insert structure, cancelled the silicon substrate that is used for keeping during manufacture intensity in this insert structure.
To achieve these goals, the invention provides a kind of method, semi-conductor device manufacturing method that adopts the wiring substrate, this method may further comprise the steps:
A. form the peelable resin bed of one deck on silicon substrate, the adhesiveness of this peelable resin bed makes and peels off from described silicon substrate easily;
B. on described peelable resin bed, form the wiring substrate;
C., a plurality of semiconductor chips are installed on described wiring substrate;
D. form a plurality of semiconductor device by seal described a plurality of semiconductor chip with sealing resin;
Thereby e. obtain the semiconductor device individuality by still keeping described silicon substrate from sealing resin one these semiconductor device of side cutting;
F. each semiconductor device individuality is peeled off with described silicon substrate, thereby described silicon substrate and described peelable resin bed are separated; And
G. run through the hole of described peelable resin bed or the terminal that is located on the wiring substrate is come out by formation by removing this peelable resin bed.
According to foregoing invention, peel off resin bed by formation, thereby silicon substrate can be easy to peel off from semiconductor device.Therefore, no longer need to carry out by processing the step that silicon chip comes out the terminal of wiring plate.Also have, the thickness of semiconductor device can reduce by a silicon substrate thickness.
The present invention also provides a kind of method, semi-conductor device manufacturing method that adopts the wiring substrate, and this method may further comprise the steps:
A. form the peelable resin bed of one deck on silicon substrate, the adhesiveness of this peelable resin bed makes easily from the wiring substrate desquamation;
B. on described peelable resin bed, form the wiring substrate;
C., a plurality of semiconductor chips are installed on described wiring substrate;
D. form a plurality of semiconductor device by seal described a plurality of semiconductor chip with sealing resin;
Thereby e. make acquisition semiconductor device individuality by still keep silicon substrate from sealing resin one these semiconductor device of side cutting;
F. each semiconductor device individuality is peeled off with silicon substrate, thereby described silicon substrate and described peelable resin bed are separated.
According to foregoing invention, peel off resin bed by formation, thereby silicon substrate and peelable resin can be easy to peel off from semiconductor device.Therefore, no longer need to carry out by processing the step that silicon chip comes out the terminal of wiring plate.Also have, the thickness of semiconductor device can reduce by a silicon substrate thickness that is removed.Also have, can remove strippable resin bed.
The present invention also provides a kind of method, semi-conductor device manufacturing method that adopts the wiring substrate, and this method may further comprise the steps:
A. form the peelable resin bed of one deck on silicon substrate, the adhesiveness of this peelable resin bed makes and peels off from silicon substrate easily;
B. on described peelable resin bed, form the wiring substrate;
C., a plurality of semiconductor chips are installed on described wiring substrate;
D. form a plurality of semiconductor device by seal described a plurality of semiconductor chip with sealing resin;
E. make the silicon substrate attenuation by grinding process;
F. these semiconductor device and described silicon substrate are peeled off, described peelable resin bed is attached on this thinning silicon substrate, thereby silicon substrate and peelable resin bed are separated;
G. obtain the semiconductor device individuality by these semiconductor device of cutting; And
H. run through the hole of peelable resin bed or the terminal that is located on the wiring substrate is come out by formation by removing this peelable resin bed.
According to foregoing invention, thereby, silicon substrate attenuation silicon substrate has flexibility by being become, and owing to the low-adhesion with peelable resin bed acts synergistically, so can be easy to from semiconductor device, silicon substrate be peeled off.Therefore, no longer need to carry out by processing the step that silicon chip comes out the terminal of wiring plate.Also have, the thickness of this semiconductor device can reduce the thickness of a silicon substrate that is removed.
The present invention also provides a kind of method, semi-conductor device manufacturing method that adopts the wiring substrate, and this method may further comprise the steps:
A. form the peelable resin bed of one deck on silicon substrate, the adhesiveness of this peelable resin bed makes easily and the wiring substrate desquamation;
B. on described peelable resin bed, form the wiring substrate;
C., a plurality of semiconductor chips are installed on described wiring substrate;
D. form a plurality of semiconductor device by seal described a plurality of semiconductor chip with sealing resin;
E. make the silicon substrate attenuation by grinding process;
F. these semiconductor device and described silicon substrate are peeled off, described peelable resin bed is attached on this thinning silicon substrate, thereby silicon substrate and peelable resin bed are separated; And
G. obtain the semiconductor device individuality by these semiconductor device of cutting.
According to foregoing invention, thereby, silicon substrate attenuation silicon substrate has flexibility by being become, and owing to the low-adhesion with peelable resin bed acts synergistically, so can be easy to from semiconductor device, silicon substrate be peeled off.Therefore, no longer need to carry out by processing the step that silicon chip comes out the terminal of wiring plate.Also have, the thickness of this semiconductor device can reduce the thickness of a silicon substrate that is removed.
The present invention also provides a kind of method, semi-conductor device manufacturing method that adopts the wiring substrate, and this method may further comprise the steps:
A. form the peelable resin bed of one deck on silicon substrate, the adhesiveness of this peelable resin bed makes and peels off from silicon substrate easily;
B. on described peelable resin bed, form the wiring substrate;
C., a plurality of semiconductor chips are installed on described wiring substrate;
D. form a plurality of semiconductor device by insulating resin being filled between described a plurality of semiconductor chip and the wiring substrate;
E. a kind of frame shaped member is sticked on the silicon substrate, make this frame shaped member surround in described a plurality of semiconductor device each, this frame shaped member is made by the higher material of its ratio of rigidity wiring substrate;
F. by from frame shaped member one these semiconductor device of side cutting but keep silicon substrate, thereby obtain the semiconductor device individuality;
G. each semiconductor device individuality is peeled off with described silicon substrate, thereby described silicon substrate and described peelable resin bed are separated; And
H. run through the hole of peelable resin bed or the terminal that is located on the wiring substrate is come out by formation by removing described peelable resin bed.
According to foregoing invention, because the rigidity of frame shaped member so semiconductor device can be kept smooth basically, therefore can prevent the semiconductor chip distortion.
The present invention also provides a kind of method, semi-conductor device manufacturing method that adopts the wiring substrate, and this method may further comprise the steps:
A. form the peelable resin bed of one deck on silicon substrate, the adhesiveness of this peelable resin bed makes easily from the wiring substrate desquamation;
B. on described peelable resin bed, form the wiring substrate;
C., a plurality of semiconductor chips are installed on described wiring substrate;
D. form semiconductor device by insulating resin being filled between described a plurality of semiconductor chip and the described wiring substrate;
E. frame shaped member is bonded on the described silicon substrate, makes described frame shaped member surround in described a plurality of semiconductor device each, described frame shaped member is made greater than the material of described wiring substrate by rigidity;
F. make the silicon substrate attenuation by grinding process;
G. peel off these semiconductor device, described peelable resin bed is attached to by on this silicon substrate of described step f) attenuation simultaneously, thereby the wiring substrate is separated with peelable resin bed; And
H. obtain the semiconductor device individuality by these semiconductor device of cutting.
According to foregoing invention, the rigidity by frame shaped member can keep smooth basically with semiconductor device, therefore can prevent the semiconductor chip distortion.
The present invention also provides a kind of semiconductor device, and this device comprises:
A thin-film multilayer substrate;
Be installed at least one semiconductor chip on the described thin-film multilayer substrate;
A package substrate that is connected with described thin-film multilayer substrate; And
Be located at the external connection terminals on the package substrate,
Wherein said thin-film multilayer substrate is fixed on the described package substrate.
According to foregoing invention, thin-film multilayer substrate self by a kind of material for example scolder be fixed on the package substrate, therefore can save the silicon substrate of the intensity that is used to keep this thin-film multilayer substrate.Therefore, can reduce the height (thickness) of this semiconductor device.Also have, the current-carrying part that passes silicon substrate need not be provided, therefore can prevent the defective that produces by these current-carrying parts, and can reduce manufacturing cost.
The present invention also provides a kind of method of making semiconductor device, and this method may further comprise the steps:
A. on silicon substrate, form metal film layer;
B. form the thin-film multilayer substrate by formation conductive layer and insulating barrier in a plurality of horizontal planes on metal film layer;
C. by bonding part support component is attached on the described thin-film multilayer substrate;
D. make described silicon substrate attenuation by back side grinding;
E. after the grinding of the described back side, remove silicon substrate and metal film layer;
F. with the thin-film multilayer substrate together with support component individuation (individualize);
G. the thin-film multilayer substrate is installed on the package substrate and with described thin-film multilayer substrate and is fixed on the described package substrate;
H. reduce the adhesiveness of bonding part, and peel off support component and bonding part from described thin-film multilayer substrate; And
I. semiconductor chip is installed on the described thin-film multilayer substrate.
According to the invention described above, even removed silicon substrate, described thin-film multilayer substrate also remains flat condition, therefore can make and handle easily, and can not make described thin-film multilayer substrate distortion.
The present invention also provides a kind of semiconductor device, and this device comprises:
The thin-film multilayer substrate;
Be installed at least one semiconductor chip on the described thin-film multilayer substrate;
The package substrate that is connected with described thin-film multilayer substrate; And
Be located at the external connection terminals on the package substrate,
Wherein said semiconductor chip is sealed on the described thin-film multilayer substrate by sealing resin, and semiconductor chip backside is exposed from sealing resin, and
Described thin-film multilayer substrate is fixed on the package substrate.
According to foregoing invention, because described thin-film multilayer substrate remains on flat condition by sealing resin, and installs described semiconductor chip on it, so can save the silicon substrate that in manufacture process, is provided for keeping rigidity.Therefore, can reduce the height (thickness) of this semiconductor device.Also have, need not to form the current-carrying part that passes silicon substrate.Therefore the defective relevant can be prevented, therefore manufacturing cost can be reduced with these current-carrying parts.
The present invention also provides a kind of method of making semiconductor device, and this method may further comprise the steps:
A. on silicon substrate, form metal film layer;
B. form the thin-film multilayer substrate by formation conductive layer and insulating barrier in a plurality of horizontal planes on metal film layer;
C., at least one semiconductor chip is installed on described thin-film multilayer substrate;
D. with resin described semiconductor chip is sealed on the described thin-film multilayer substrate;
E. remove silicon substrate and metal film layer;
F. make thin-film multilayer substrate individuation (individualizing); And
G. the thin-film multilayer substrate of individuation is installed on the package substrate and with this thin-film multilayer substrate and is fixed on the package substrate.
According to the invention described above, even removed silicon substrate in manufacture process, described thin-film multilayer substrate also can remain flat condition by semiconductor chip and sealing resin, therefore can easily handle described thin-film multilayer substrate.
Brief description of drawings
Figure 1A-1F demonstrates the several steps according to the insert structure manufacture method of first embodiment of the invention;
Fig. 2 A-2C demonstrates the several steps according to the insert structure manufacture method of first embodiment of the invention;
Fig. 3 is for wherein being formed with the plane graph at the silicon chip of the protection of the adhesiveness shown in Fig. 1 resin bed;
Fig. 4 A-4E demonstrates employing each step according to the semiconductor making method of the insert structure of first embodiment of the invention;
Fig. 5 demonstrates wherein a plurality of LSI chips and is installed in according to the embodiment on the insert structure of first embodiment of the invention;
Fig. 6 A-6E demonstrates employing each step according to the semiconductor making method of the insert structure of second embodiment of the invention;
Fig. 7 shows to send as an envoy to have semiconductor device separation steps attached to the resin bed on the silicon chip;
Fig. 8 demonstrates underfilling (underfill material) is filled in the embodiment between semiconductor chip and the insert structure;
Fig. 9 demonstrates the preferred size of sealing resin;
Figure 10 demonstrates the first step of molding resin as shown in Figure 9;
Figure 11 demonstrates second step of molding resin as shown in Figure 9;
Figure 12 demonstrates the third step of molding resin as shown in Figure 9;
Figure 13 demonstrates the 4th step of molding resin as shown in Figure 9;
Figure 14 A-14G demonstrates each step according to the method, semi-conductor device manufacturing method of third embodiment of the invention;
Figure 15 A and 15B demonstrate the step that resin bed is peeled off with silicon chip;
Figure 16 A-16D demonstrates each step according to the method, semi-conductor device manufacturing method of four embodiment of the invention;
Figure 17 demonstrates resin wherein and is filled in embodiment between framework and the semiconductor chip;
Figure 18 demonstrates by a plurality of semiconductor chips and passive component are installed in the semiconductor device that forms on the insert structure of the present invention;
Figure 19 demonstrates the semiconductor device that has wherein adopted insert structure of the present invention and is installed in embodiment on the card (package board);
Figure 20 demonstrates the embodiment that wherein is provided with radiator on semiconductor device as shown in Figure 19;
Figure 21 is the cutaway view of semiconductor device, and wherein a plurality of LSI chips are installed on the insert structure that adopts Semiconductor substrate formation;
Figure 22 is the cutaway view according to the semiconductor device of fifth embodiment of the invention;
Figure 23 is the cutaway view of modification of the semiconductor device of fifth embodiment of the invention;
Figure 24 demonstrates the first step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 25 is the zoomed-in view by the circular portion of " A " among Figure 24 expression;
Figure 26 demonstrates second step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 27 is the cutaway view in the structure of the film of adhesiveness shown in Figure 26;
Figure 28 demonstrates the third step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 29 demonstrates the 4th step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 30 demonstrates the 5th step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 31 demonstrates the 6th step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 32 demonstrates the 7th step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 33 demonstrates the 8th step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 34 demonstrates the 9th step of the method that is manufactured on the semiconductor device shown in Figure 22;
Figure 35 is the cutaway view in the modification of the semiconductor device shown in Figure 22;
Figure 36 is the cutaway view according to the semiconductor device of sixth embodiment of the invention;
Figure 37 demonstrates the first step of the method that is manufactured on the semiconductor device shown in Figure 36;
Figure 38 demonstrates second step of the method that is manufactured on the semiconductor device shown in Figure 36;
Figure 39 demonstrates the third step of the method that is manufactured on the semiconductor device shown in Figure 36;
Figure 40 demonstrates the 4th step of the method that is manufactured on the semiconductor device shown in Figure 36;
Figure 41 demonstrates the 5th step of the method that is manufactured on the semiconductor device shown in Figure 36;
Figure 42 demonstrates the 6th step of the method that is manufactured on the semiconductor device shown in Figure 36;
Figure 43 demonstrates the 7th step of the method that is manufactured on the semiconductor device shown in Figure 36;
Figure 44 demonstrates the cutaway view in the modification of the semiconductor device shown in Figure 36;
Figure 45 demonstrates the technology of grinding at the back side of the LSI of the semiconductor device shown in Figure 36 chip;
Figure 46 demonstrates in the step of grinding after the back side of the LSI of the semiconductor device shown in Figure 36 chip;
Figure 47 is the cutaway view of the modification of film wiring layer;
Figure 48 demonstrates the crackle that may occur in the film wiring layer;
Figure 49 demonstrates the first step of the modification of making the film wiring layer;
Figure 50 demonstrates second step of the modification of making the film wiring layer;
Figure 51 demonstrates the third step of the modification of making the film wiring layer;
Figure 52 shows the step of the film wiring layer individuation of sening as an envoy to, and this film wiring layer is separated;
Figure 53 is the plane graph of the silicon chip of the film wiring layer that is formed with individuation on it;
Figure 54 demonstrates the step of support component that the film wiring layer of Figure 52 is posted in cutting on it;
Figure 55 shows the first step of the film wiring layer individuation of sening as an envoy to, and wherein this film wiring layer is formed on the silicon chip;
Figure 56 shows second step of the film wiring layer individuation of sening as an envoy to, and wherein this film wiring layer is formed on the silicon chip;
Figure 57 shows the third step of the film wiring layer individuation of sening as an envoy to, and wherein this film wiring layer is formed on the silicon chip;
Figure 58 shows the 4th step of the film wiring layer individuation of sening as an envoy to, and wherein this film wiring layer is formed on the silicon chip;
Figure 59 shows the 5th step of the film wiring layer individuation of sening as an envoy to, and wherein this film wiring layer is formed on the silicon chip;
Figure 60 demonstrates the method for testing film MULTILAYER SUBSTRATE during the manufacture process of semiconductor device;
Figure 61 demonstrates the method for testing film MULTILAYER SUBSTRATE during the manufacture process of semiconductor device;
Figure 62 demonstrates the method for testing film MULTILAYER SUBSTRATE during the manufacture process of semiconductor device;
Figure 63 demonstrates the method for testing film MULTILAYER SUBSTRATE during the manufacture process of semiconductor device.
Detailed description of preferred embodiments
Below with reference to accompanying drawings principle of the present invention and embodiment are described.
According to the present invention, can obtain the insert structure that designs simplification and thickness reduce by a kind of insert structure manufacture method, in this method, the stepped construction of wiring layer and insulating barrier is formed on the substrate that is used to keep intensity, removes this substrate by from stepped construction, peeling off then.
At first, will the manufacturing process according to the insert structure of first embodiment of the invention be described.Figure 1A-2C demonstrates the several manufacturing steps according to the manufacturing process of the insert structure of first embodiment of the invention.By will realize a kind of complete insert structure manufacturing process together in the combination of process steps shown in Figure 1A-1C.
At first, prepare silicon chip 1, and shown in Figure 1A, will be used for the surperficial 1a that bonding resin bed 2 is formed on silicon chip 1 as substrate.Resin bed 2 does not cover the whole surperficial 1a of silicon chip 1, but forms grille-like as shown in Figure 3.By adopting spin coating proceeding that resin-coating is formed grid-like resin bed 2 on the whole surperficial 1a of silicon chip 1.The structure of the grid of resin bed 2 is corresponding with the segmentation lines that is used for cutting step subsequently.
The thickness of silicon chip is 500 μ m-700 μ m, as the parts that keep the intensity of insert structure during manufacture process.For making the ordinary semiconductor device, before forming through hole, silicon chip is ground to the thickness that is approximately 100 μ m-200 μ m.This resin bed 2 can be formed by polyimide resin, and this resin is generally used for constructing semiconductor chip and has good adhesiveness with respect to silicon chip 1.
Then, shown in Figure 1B, form the peelable resin bed 3 have than low-adhesion to cover the whole surperficial 1a of silicon chip 1.The peelable resin bed 3 of low-adhesion can be formed by polyimide resin, and the adhesiveness that the polyimide resin of this resin and above-mentioned resin bed 2 compares silicon chip 1 is lower, can be easy to peel off from silicon chip.The thickness of low-adhesion resin bed 3 is greater than resin bed 2, and forms and be used for covering resin layer 2.
Then, shown in Fig. 1 C, form pad 4 by copper facing on resin bed 3.Then, shown in Fig. 1 D, cover these pads 4, and use adjacent pad 4 to form capacitor 8 with insulating barrier 5.In detail, be formed on in a pair of pad 4 one as first conductive layer pattern 6 of electrode, and second conductive layer pattern 7 is formed on the certain intervals place of first conductive layer, 6 tops.Second conductive pattern 7 is connected with in the described a pair of pad 4 another.To have high dielectric constant materials and be filled between first conductive layer pattern 6 and second conductive layer pattern 7, so that between first conductive layer pattern 6 and second conductive layer pattern 7, form capacitor 8.That is to the terminal of pad 4 as capacitor 8.
Then, shown in Fig. 1 E, capacitor is imbedded in the insulating barrier 9.Then, shown in Fig. 1 F, another layer insulating 10 is formed on the insulating barrier 9.Remove this another layer insulating 10 with predetermined pattern, and for example form pad 11 at the part place of removing by copper facing.
Then, shown in Fig. 2 A, stepped construction (insert structure) individuation that adopts cutting cutter (dicing blade) will have the capacitor 8 that forms in inside (is cut open, individualize).In detail, silicon chip back 1b is attached on the cutting band 13, cutting cutter 12 is moved to cut this stepped construction along segmentation lines.The penetraction depth of cutting cutter 12 is such, and promptly resin bed 2 is cut, and the top of cutting cutter 12 (perhaps periphery) cuts in the silicon chip 1 as substrate a little.Therefore, by cutting technology the major part of resin bed 2 is cut and removed.
Be noted that resin bed 2 has good adhesiveness with respect to silicon chip 1, and with respect to also being that resin bed 3 by the polyimide resin of same type is made also has good adhesiveness.Therefore, having resin bed 3 than low-adhesion even adopt with respect to silicon chip 1, can be the certain adhesiveness of silicon chip 1 acquisition by resin bed 2 also.Therefore, in the manufacturing step (in the step shown in Figure 1A-1F) of insert structure, can as the intensity holding member stepped construction be formed on the silicon chip 1 by using silicon chip 1.
With reference to Fig. 2 A, be removed carrying out the most of afterwards resin bed 2 of cutting step (individualizing step) by cutting cutter 12 as can be seen.Therefore, the adhesiveness between stepped construction and the silicon chip 1 is lowered, and shown in Fig. 2 B, can be easy to cutting be opened from the silicon chip 1 (individuation, individualized) stepped construction (corresponding with insert structure) is peeled off.
Shown in Fig. 2 C, each stepped construction of peeling off from silicon chip 1 is provided with hole 3a in the pad 4 corresponding positions with resin bed 3, thereby these pads are exposed among the 3a of these holes.These holes 3a can form by laser processing technology.
By above-mentioned steps, can obtain to have the insert structure of interior capacitor of being embedded in 8.As mentioned above, according to the present invention, can be positioned at the stepped construction that forms insert structure as the low-adhesion polyimide resin layer on the silicon chip 1 of substrate 3 by utilization and remove silicon chip by peeling off then, thereby form the insert structure that thickness reduces.Only in these manufacturing step processes, just use resin bed 2 that low-adhesion polyimide resin layer 3 firmly is fixed on the silicon chip 1.
According to above-mentioned embodiment, capacitor 8 is formed on insert structure inside, but not necessarily at the inner capacitor that forms of insert structure, this insert structure can only be used for reallocation and connect (redistribution connection).Also have, according to this embodiment, adopt silicon chip as substrate, and this low-adhesion resin bed 3 made by polyimide resin, still, the present invention is not limited to those materials and substrate, but also can use the resin of other material.
Now, will an embodiment of series of steps be described, wherein made up above-mentioned insert structure manufacturing step and semiconductor chip is installed to step on the insert structure.
Fig. 4 A-4E demonstrates some steps of above-mentioned series of steps.Come on silicon chip 1 after the cambium layer stack structure in the step by carrying out Figure 1A-1F, this technology advances to the step shown in Fig. 4 A.
In the step shown in Fig. 4 A, on insert structure, install and be provided with for example LSI chip 14 of solder bump (solder bump) of external connecting electrode.In detail, the solder bump 14a of LSI chip 14 is contacted with the pad 11 of exposure.Then, underfilling 15 is filled between LIS chip 14 and the insulating barrier 10.
Then, shown in Fig. 4 B, with sealing resin 16 these LSI chips 14 of sealing.Like this, on silicon chip 1, form a plurality of semiconductor device 17.Then, shown in Fig. 4 C, make these semiconductor device 17 separately by cutting technology.This cutting technology with carry out in the similar mode of cutting technology shown in Fig. 2 A, thereby removed most of resin bed 2, and in silicon chip 1, produce the shallow cut.
Then, shown in Fig. 4 D, (individuation) semiconductor device 17 that cutting is opened is peeled off from silicon chip 1.Then, shown in Fig. 4 E, form and run through the hole 3a of resin bed 3, thereby pad 4 is exposed.The pad 4 that exposes is as the external connection terminals of semiconductor device 17.
Top explanation relates to an embodiment of the semiconductor device with single LSI chip.But, also a plurality of dissimilar LSI chips can be installed on the insert structure.For example, as shown in Figure 5, a kind of possible application is to use the insert structure 23 that produces according to above-mentioned steps high-speed i/o interface chip 20, logic LSI21 and RAM chip 22 to be linked together and further they are arranged in a kind of semiconductor device is provided on the LSI assembly 24.
Now, will describe having adopted the method for making semiconductor device according to the insert structure of second embodiment of the invention.Fig. 6 A-6E demonstrates the method for making semiconductor device according to the insert structure of second embodiment of the invention that adopted.
The insert structure 30 of this embodiment is to constitute with the similar mode of above-mentioned first embodiment.That is to say, form the peelable resin bed 3 that has low-adhesion with respect to silicon chip 1, form the stepped construction of wiring layer and insulating barrier then thereon.In this embodiment, utilizing after resin bed 3 is formed on insert structure 30 on the silicon chip 1, as shown in Figure 6 semiconductor chip 31 is installed in (flip-over type is installed (flip-chip mounting)) on the insert structure 30.In this state, a plurality of insert structures 30 are attached on the silicon chip 1 in interconnective mode.Therefore, a plurality of insert structures 30 have certain adhesive strength on the whole, therefore can not peel off from silicon chip 1.In other words, resin bed 3 is made by being selected from the material with such adhesiveness characteristic.
After being installed in semiconductor chip 31 on the insert structure 30, shown in Fig. 6 B, these semiconductor chips 31 are sealed (wafer molding) with sealing resin 32.Thus, on silicon chip 1, form a plurality of semiconductor device 33.Afterwards, shown in Fig. 6 C, UV is attached on the back side of silicon chip 1 with 34, utilizes cutting cutter 12 to carry out the cutting step (individualizing step) (Si hemisect or cutting) of semiconductor device 33.The otch that is formed by cutting cutter 12 has so degree of depth, makes the cutting cutter enter silicon chip 1 a little but silicon chip 1 is not separated by these otch.
Then, shown in Fig. 6 D (Si hemisect or cutting), peel off from silicon chip 1 by they being picked up the semiconductor device 33 that (as by shown in the arrow among Fig. 6 D) open these cuttings with vacsorb equipment.Before the cutting step, a plurality of semiconductor device 33 are attached on the silicon chip 1 together by resin bed 3.But, because resin bed 3 is also by the cutting step separately, so these semiconductor device 33 can be easy to peel off from the silicon chip 1 that still keeps not having to separate (in aggregates).
At last, shown in Fig. 6 E, for example form and run through the hole 3a of resin bed 3, thereby expose the pad 4 that is embedded in the resin bed 3 by laser processing technology.These pads 4 are as the external connection terminals of semiconductor device 32.In the step shown in Fig. 6 E, by forming hole 3a these pads 4 are exposed, but also can be arbitrarily other technology for example remove resin bed 3 with dissolution with solvents resin bed 3, thereby these pads 4 are exposed.
As mentioned above, being formed on the semiconductor device that the employing insert structure 30 on the silicon chip 1 constitutes is bonded on the silicon chip 1 firmly up to their cuttings are opened.But after the cutting step, these semiconductor device can be easy to peel off from silicon chip 1.
In the above-described embodiment, replace having resin than low-adhesion with respect to silicon chip, described resin bed 3 can be by having than the resin of low-adhesion and make with respect to being formed on insert structure 30 (pad 4 and insulating barrier) on the resin bed 3.Thus, as shown in Figure 7, comprise that the semiconductor device 1 of insert structure 30 can separate with the resin bed 3 that keeps being bonded on the silicon chip 1.In this case, can pad 4 be exposed, therefore can cancel in Fig. 6 E, forming and run through the hole 3a of resin bed 3 so that expose the step of pad 4 by carrying out stripping technology.
In the above-described embodiment, adopt sealing resin that semiconductor device 31 is sealed on the insert structure 30.But, replace resin-sealedly, underfilling 35 can be filled between semiconductor chip 31 and the insert structure 30 to form semiconductor device 33.
To describe another kind of situation below, wherein shown in Fig. 6 B-6E, come sealing semiconductor chips 31 by sealing resin 32.Fig. 9 demonstrates the preferred size of sealing resin.As shown in Figure 9, be filled in the height H of the sealing resin between the adjacent semiconductor chip 31
RPreferably be lower than height (or horizontal plane) H at the back side of semiconductor chip 31
M(H
R＜H
M).Its reason is as follows.
Owing to the semiconductor chip that the insert structure of top embodiment is extremely thin and mounted thereto is also extremely thin, so these semiconductor device are also extremely thin, so rigidity is relatively poor and easy deformation.Therefore, the contraction that causes owing to the curing by sealing resin 32 can cause insert structure 30 distortion.That is to say, insert structure 30 meeting warpages, sealing resin 32 is positioned at the inboard during warpage.
The amount of the sealing resin 32 on can being located at around these semiconductor chips 31 by minimizing prevents above-mentioned distortion.In other words, can reduce the distortion of semiconductor device 33 by the height that reduces sealing resin 32.
Figure 10-13 demonstrates each step of moulding resin process, thereby the height of sealing resin 32 is reduced as shown in Figure 9.Usually, adopt the transfer molding method that sealing resin 32 is filled between the semiconductor chip 31.
At first, as shown in figure 10, make fexible film 41 along the bed die 40A arrangement that is used for carrying out transfer molding.The semiconductor chip 31 that is installed on the silicon chip 1 is arranged among the bed die 40A.Then fexible film 42 is applied on the mold 40B.The sheet 43 of sealing resin is placed between bed die 40A and the mold 40B.The fexible film 42 that is applied on the mold 40B is a kind of elastic films with relatively large thickness.
As shown in figure 11, when bed die 40A and mold 40B were moved toward each other under heating condition, resin sheet 43 was softening and be filled between these semiconductor device 31.Then, the back side of the fexible film 42 contact semiconductor chips 31 of mold 40B.
When bed die 40A and mold 40B further near the time, as shown in figure 12, the part that fexible film 42 contacts with semiconductor chip 31 is compressed and is out of shape, thus in the part of the fexible film between the semiconductor chip 31 42 as shown in the reference number A among this figure, equally becoming convex.Therefore, the height of the sealing resin between semiconductor chip 31 32 becomes and is lower than the height of semiconductor chip 31.
By reducing temperature and making mold 40A and the complete closure of bed die 40B is solidified sealing resin 32.Therefore, as shown in Figure 9, the height that this semiconductor device constitutes sealing resin 32 is lower than the height of semiconductor chip 31.
The semiconductor device that is formed in the above described manner on the silicon chip 1 can be according to peeling off from silicon chip 1 at the stripping technology shown in Fig. 6 A-6E or Fig. 7.Its thickness of sealing resin that is formed on by this way around the semiconductor chip 31 of the semiconductor device that constitutes reduces, and therefore can reduce the distortion (or warpage) that the contraction owing to sealing resin produces.
Now, will the production process of semiconductor device of the insert structure that adopts third embodiment of the invention be described.Figure 14 A-14G demonstrates each step of the method, semi-conductor device manufacturing method of the insert structure that adopts third embodiment of the invention.
Figure 14 A and 14B demonstrate with at the similar step of step shown in Fig. 6 A and the 6B (flip-over type install and wafer molding).In this embodiment, after being sealed in semiconductor chip 31 on the silicon chip 1 with sealing resin 32, shown in Figure 14 C, the back side of grinding silicon chip 1, thus be that the silicon chip of 200 μ m is reduced to the thickness (silicon grinding) that is approximately 25 μ m-50 μ m with thickness.
Then, shown in Figure 14 D, the silicon chip 1 of thinning is peeled off (silicon is peeled off) from semiconductor device.By grinding process, silicon chip 1 becomes a kind of flexible foil, therefore can be easy to silicon chip 1 is peeled off.Then, shown in Figure 14 E, the hole 3a (hole formation) that runs through resin bed 3 by formation exposes pad 4.
Then, shown in Figure 14 F, utilize the UV that is attached on semiconductor chip 34 sides to be with 34, with semiconductor chip 33 individuations.Then, these semiconductor chips 33 are peeled off to obtain complete semiconductor device 33 (individuation or cutting) with 34 from UV.
In this embodiment, resin bed 3 by its with respect to the adhesiveness of insert structure 30 greater than situation about making with respect to the adhering material of silicon chip in, can also be shown in as Figure 15 A and peel off silicon chip 1 when peeling off resin bed 3.Therefore, only need the cutting step to finish, can save the step that the hole of running through resin bed 3 by formation exposes pad at the semiconductor device 33 shown in Figure 15 B.
Now, will the production process of semiconductor device of the insert structure that adopts four embodiment of the invention be described.Figure 16 A-16D demonstrates each step of the method, semi-conductor device manufacturing method of the insert structure that adopts four embodiment of the invention.
At first, shown in Figure 16 A, semiconductor chip 31 upside-down mountings are installed on the insert structure 30, and underfilling 35 is filled in (flip-over type is installed and bottom filling (underfilling)) between semiconductor chip 31 and the insert structure 30.Then, shown in Figure 16 B, will be provided with and be fixed on the insert structure 30 by the framework 36 that material or resin are made by bonding agent, thereby each framework 36 surrounds semiconductor chip 31 (framework shaping).Like this, semiconductor chip 31 and their coupling part have been protected.
Then, shown in Figure 16 C, carry out the cutting process so that the UV that is attached on the silicon chip 1 is arranged with 34 semiconductor device 33 individuations (Si hemisect or cutting).Then, on resin bed 3 and silicon chip 1, semiconductor device 33 is peeled off, thereby finished at the semiconductor device 33 shown in Figure 16 D.
In this embodiment, owing to preformed rigid frame 36 is attached on the insert structure 3, can prevent owing to sealing resin shrinks the problem that causes semiconductor device (insert structure) distortion with bonding agent.
Be noted that after the framework 36 that forms as shown in Figure 16 B, resin 37 can be filled between framework 36 and the semiconductor chip 31 as shown in figure 17.
Figure 18 demonstrates by a plurality of semiconductor chips and passive component are installed in the semiconductor device that forms on the insert structure of the present invention. Dissimilar semiconductor chip 50 and 51 is installed on the insert structure 30, and will be installed on the insert structure 30 as the capacitor of passive component.As among Figure 19 as can be seen, soldered ball 53 is formed on the pad 4 of the semiconductor device shown in Figure 18.As among Figure 19 as can be seen, semiconductor device is installed in by on organic substrate or the inorganic substrate package substrate that for example ceramic substrate is made.In fact widened the external connection terminals of the minute interval of insert structure 30 by package substrate 54.Also have, as shown in figure 20, can utilize bonding agent with thermal conductive resin with radiator 56 for example metallic plate form on the back side that exposes semiconductor chip 50 of this semiconductor device.
Now, consider a kind of like this semiconductor device, wherein a plurality of semiconductor chips for example LSI chip are installed on the insert structure.Figure 21 is for by being installed in a plurality of LSI chips the cutaway view of the semiconductor device that forms on the wiring substrate that adopts silicon substrate to form.On comprising by the silicon substrate (Si substrate) 101 that is about 50-200 μ m at thickness, the semiconductor device shown in Figure 21 forms the insert structure (wiring substrate) 103 that multiple wiring layer 102 forms.
In the embodiment shown in Figure 21, will as two LSI chips 104 of chip part and 105 and capacitor 106 (having shown one of them capacitor among the figure) be installed on the wiring layer 102 of insert structure 103.To be formed on the back side of insert structure 103 by the insulating barrier 107 that polyimide resin is made, and electrode pad 108 will be formed on the front of insulating barrier 107.The pattern of electrode pad 108 for being connected with wiring layer 102 by the path 109 of filling copper.Like this, LSI chip 104,105 and electrode pad 108 are electrically connected.By forming the path 109 of filling copper in the through hole that electro-coppering is filled in through-silicon substrate 101 and insulating barrier 107.
The electrode pad 108 of insert structure 103 is connected with the electrode 111 that is located at as on the glass-ceramic substrate 110 of package substrate with solder bump by soldered ball.Be formed on the back side of glass ceramic substrate 110 as the soldered ball 112 of external connection terminals.So just formed this semiconductor device.
For for the semiconductor device shown in Figure 21, electro-coppering must be filled in the through hole of the Si substrate 101 that passes insert structure 102 and insulating barrier 107.The thickness of Si substrate 101 is approximately 50-200 μ m, and needs special technology to form the small through hole that runs through the substrate with such thickness.For example, must form through hole and utilize CVD that the inner surface of through hole is carried out insulation processing by inductive couple plasma reactive ion etching (ICP-RIE).These relatively costly technologies cause the manufacturing cost of this semiconductor device to increase.In addition, in the process that electro-coppering is filled in these through holes, be difficult to prevent to cause conductivity to descend technically and the appearance in the space that reliability reduces.
Also have,, be approximately 50-200 μ m, so be difficult in manufacture process, insert structure be handled as a monomer because the thickness of silicon substrate 101 is very little.
As shown in this figure, wiring layer 102 is formed on one of them side of silicon substrate 101, and insulating barrier 107 is formed on another side of this silicon substrate 101.Therefore, this insert structure 103 is easy to warpage.That is to say that because wiring layer 102 has a kind of sandwich construction and its thickness thickness greater than insulating barrier 107, so warpage can be owing to difference in thickness occurs.In the situation of insert structure 103 warpages, also there is a problem, the LSI chip that promptly is difficult to have small at interval electrode is installed on the insert structure 103.
It is also noted that the silicon substrate 101 of insert structure 103 is parts essential in manufacture process, but not necessarily will be included in the finished product semiconductor device.Therefore, have another problem, promptly the height of this semiconductor device (perhaps thickness) comprises the thickness of Si substrate 101 not necessarily essential for semiconductor device.
Figure 22 is the cutaway view of the semiconductor device of fifth embodiment of the invention.As shown in figure 22, use with label identical in Figure 21 with the parts that in Figure 21, are equal to and represent.
The semiconductor device 120 of fifth embodiment of the invention constitutes by being installed in LSI chip 104,105 on the thin-film multilayer substrate 121 and this thin-film multilayer substrate 121 being installed on the package substrate 110.Thin-film multilayer substrate 121 is with corresponding in the insert structure shown in Figure 21 102.Underfilling 122 is filled between thin-film multilayer substrate 121 and the package substrate 110, and thin-film multilayer substrate 12 is fixed on the encapsulated layer 110 with relative high stiffness.By stacked insulating barrier for example polyimides and BCB (benzocyclobutene, Bezo-Cyelo-Butene) and wiring layer for example copper (Cu) constitute thin-film multilayer substrate 121.Package substrate 110 is the substrate glass-ceramic substrates (GC substrate) or strengthen substrate (build-up substrate) for example with relative good stiffness.Also have, because this wiring MULTILAYER SUBSTRATE 121 is for example by being welded to connect on package substrate 110, so needn't fill underfilling 122.
From between Figure 21 and 22 more as can be seen, thin-film multilayer substrate 121 be in the semiconductor device shown in Figure 22 120, be used as the wiring substrate unique part.That is to say that this semiconductor device 120 is not provided with Si substrate 101 shown in Figure 21 and insulating barrier 107.Therefore, the copper path 109 that passes Si substrate 101 can be save, and the through hole of copper path 109 needn't be formed for providing.
As mentioned above, because semiconductor device 120 does not comprise the Si substrate as the wiring substrate,, therefore can reduce manufacturing cost so can save the step that forms the copper path that passes the Si substrate.Also have, can make the height (thickness) of semiconductor device reduce a corresponding amount of thickness with insulating barrier and Si substrate.
At the semiconductor device shown in Figure 22 120 is so to constitute, thereby the connection between thin-film multilayer substrate 121 and the package substrate 110 is ball grid array (BGA, Ball-grid-array) connection of structure.But, be noted that these connectors can be in the pad grid matrix shown in Figure 23 (LGA, land grid array) structure.
Now, describe with reference to Figure 24-34 pair of manufacturing process at the semiconductor device shown in Figure 22 120.Figure 24,26 and 28-34 demonstrate each step of the manufacture method of semiconductor device 120.
At first, as shown in figure 24, metal film layer 124 is formed on the silicon chip 123 of thick about 500-700 μ m, and film wiring layer 125 is formed on the metal film layer 124.Film wiring layer 125 is with corresponding at the thin-film multilayer substrate 12 shown in Figure 22.Above-mentioned steps can adopt the equipment of the film wiring layer 125 that is used for common wafer process and can forms meticulous sandwich construction to carry out.
Figure 25 is the enlarged drawing that is designated as the circular portion of " A " in Figure 24.As can be seen from Figure 25, metal film layer 124 comprises the Ti sputtering layer 124A that is formed on the silicon chip 123 and is formed on Cu sputtering layer 124B on this Ti sputtering layer 124A.Therefore, this film wiring layer 125 is formed on the Cu sputtering layer 124B.Ti sputtering layer 124A can replace with Cu sputtering layer or Ni sputtering layer.Metal film layer 124 forms the wiring sputtering layer simultaneously as protective layer on silicon chip 123.
Top electrode 127 has and bottom electrode 128 similar structures, therefore, nickel (Ni) electrodeposited coating 132 is formed on copper (Cu) electrodeposited coating 131, then gold (Au) layer 133 is formed thereon.
Electrode can also be formed in the film wiring layer 115 so that make bottom electrode relative with top electrode, thereby by between them, providing the material with higher relative dielectric constant to form internal capacitor.
Then, as shown in figure 26, utilize film of adhesiveness 125 with support component 136 for example glass plate be attached on the top of film wiring layer 125.Support component 136 so is provided with, thereby it is remained on flat condition so that handle easily with the film wiring layer in the manufacturing step process.Figure 27 is the cutaway view of the structure of film of adhesiveness 135.Film of adhesiveness 135 comprises polyethylene (PET) film 135A, be applied to the common adhesive 135B on the side of this PET film 135A and be positioned at heat foamable jointing material or UV curing binder material 135C on the another side of PET film 135A.
As for film of adhesiveness 135, adhesive 135B is used for bonding glass plate as support component 136, and heat foamable foam jointing material or UV curing binder material 135C are used for adhering film wiring layer 125.Heat foamable adhesion material 135C is a kind of jointing material with performance like this: it is heated to temperature above predetermined temperature, produces foam in heat foamable jointing material 135C, therefore reduced adhesiveness.UV curing binder material 135C is a kind of material with such performance, and promptly it solidifies under ultraviolet radiation irradiation situation thereon and has reduced adhesiveness.Heat foamable jointing material or UV curing binder material 135C as adhesion layer can also be formed directly on the support component 136.
Then as shown in figure 28, be with 137 to be attached on the support component 136 back side grinding (BG), and when making support component 136 rotation grinding silicon chip 123 (back side grinding).These silicon chip 123 grindings are reduced to about 50 μ m up to its thickness.Then, as shown in figure 29, the silicon chip 123 of this thinning is arranged to upwards, and when making these silicon chip 123 rotations, is rotated etch process so that remove the remainder and the metal film layer 124 of silicon chip 123.Thus, make as the undermost insulating barrier of film wiring layer 25 and the Au electrodeposited coating 128 of bottom electrode 126 and expose.
In this embodiment, the etchant that is used for spin etch technology is hydrofluoric acid-nitric acid (5%HF+55%HNO
3+ H
2O).Hydrofluoric acid-nitric acid makes silicon and Ti and Cu dissolving, but it can not dissolve Au electrodeposited coating or polyimide insulative layer.Therefore, have only the remainder of the silicon chip 123 that does not grind away to be dissolved in hydrofluoric acid-nitric acid and be removed.Therefore, the Au electrodeposited coating 128 of the bottom insulating barrier of film wiring layer 125 and bottom electrode 126 exposes.
After spin etch technology, hydrofluoric acid-nitric acid is neutralized, clean dry then.When dropping in sodium phosphate on the exposed surface, carry out the N-process of hydrofluoric acid-nitric acid by rotating technics.That is to say, will be retained in hydrofluoric acid on the exposed surface-nitric acid neutralization by dripping sodium phosphate (tertiary sodium phosphate) down.Afterwards, carry out drying with this exposed surface of washed with de-ionized water and by drying up dry air or nitrogen.
The chemical formula that is used as the tertiary sodium phosphate of nertralizer is Na
3PO
46H
2O.The concentration of tertiary sodium phosphate is preferably 5wt% (approximately 0.1-10% be feasible scope), and temperature be preferably 50 ℃ (degree centigrade) (20-70 ℃ is usable range).Also have, the needed time of this N-process is approximately 10-20 second.
Then, as shown in figure 30, in the state that film wiring layer 125 is fixed on the support component 136, solder bump 138 is formed on the Au electrodeposited coating 128 of bottom electrode 126 of exposure.In general, form solder bump 138 by electroplating process.If film of adhesiveness 135 has used heat foamable jointing material 135C, then processing temperature must be remained below the temperature that described heat foamable jointing material 135C begins to form foam.Also have, in the situation of as shown in Figure 23 LGA structure, needn't form solder bump 138.Here, owing to thin-film multilayer layer 125 is fixed on the support component 136, so can on film wiring layer 125, be used for forming the light etching process of electroplating projection.
Then, as shown in figure 31, cutting band 139 is attached on the support component 131, and film wiring layer 125 is cut and individuation by cutting cutter 140.Simultaneously, also cut film of adhesiveness 135 and support component 136.Like this, the film wiring layer 125 (corresponding with the thin-film multilayer substrate 121 among Figure 22) with individuation remains on the state that is fixed on the support component 136.
Then, shown in figure 32, the thin-film multilayer substrate 121 of individuation is connected on the package substrate 110 by the bonding solder bump 138 that utilizes of flip-over type.This thin-film multilayer substrate 121 keeps good flatness, so and since thin-film multilayer substrate 121 to be fixed on the coplanarity of solder bump on the support component of being made by glass plate 136 good.Therefore, this thin-film multilayer substrate 121 with fine structure can be easily installed on the package substrate.For this reason, bonding temp should be lower than the foaming initial temperature of film of adhesiveness.Afterwards, underfilling 122 is filled between thin-film multilayer substrate 121 and the package substrate 110, and underfilling 122 is solidified.
As shown in figure 33, after making underfilling 122 curing, from thin-film multilayer substrate 121, film of adhesiveness 135 is peeled off.Adopting UV to solidify in the situation of fopam gluing material 135C as film of adhesiveness 135, by the support component of making by glass plate ultraviolet radiation is being radiated at adhesion material 135C and goes up so that reduce adhesiveness.Then, adhesion material 135C is separated to remove film of adhesiveness 135 with thin-film multilayer substrate 121.
Then, as shown in figure 34, by the flip-over type connection LSI chip 104,105 is installed on the thin-film multilayer substrate 121, and also chip part 106 (not shown) is installed on the thin-film multilayer substrate 121.Then, underfilling 139 is filled between LSI chip 104,105 and the thin-film multilayer substrate 121.To be formed on as the soldered ball 112 of external connection terminals then on the back side of package substrate 110 to finish at the semiconductor device shown in Figure 22 120.
Equally, as shown in figure 35, can radiator or fin 141 be installed on the top of LSI chip 104,105 of this semiconductor device 120 so that accelerated heat dissipates by solder flux (Ag) cream 140.
According to the manufacturing process of this semiconductor device 120, film wiring layer 125 is fixed in the flat condition by support component 136.Therefore, there is no need to form the copper path of through-silicon substrate.Also have, film wiring layer 125 individualities are turned to a plurality of thin-film multilayer substrates 121 and it is installed on the package substrate 110 and remove by peeling off then from support component 136.Therefore, thin-film multilayer substrate 121 always is fixed in the flat condition, therefore handles easily.
Now, will the semiconductor device of sixth embodiment of the invention be described.Figure 36 is the cutaway view of the semiconductor device 150 of sixth embodiment of the invention.In Figure 36, represent with corresponding reference number with the parts that those parts at the semiconductor device shown in Figure 32 120 are equal to, and omitted its detailed description.
Similar in 130 its basic structures of the semiconductor device shown in Figure 36 and semiconductor device 120, except the LSI chip 104,105 of the semiconductor device 120 that seals above-mentioned the 5th embodiment with sealing resin.
Figure 37-43 order demonstrates each step in the manufacture method of the semiconductor device shown in Figure 36.Therefore the something in common of the manufacturing step of the manufacturing step of this semiconductor device 150 and semiconductor 120 has save its detailed description up to LSI chip 104,105 is installed on the film wiring layer 125.
As shown in figure 37, these chips 104,105 are installed on the film wiring layer 125.Then, be used in the sealing resin 151 (molding type or fluid resin type) that forms by for example epoxide resin material shown in Figure 38 and seal these LSI chips 104,105.Sealing resin 151 is filled between LSI chip 104 and 105, thereby the upper surface of sealing resin 151 is flushed with the back side of LSI chip 104,105.Therefore, the back side of the upper surface of sealing resin 151 and LSI chip 104 and 105 forms flat surfaces.
The linear expansion coefficient α of sealing resin 151 is that (α=8-20ppm), it is greater than the linear expansion coefficient of silicon for 8-20ppm.Therefore, may be owing to silicon chip 123 warpages appear in the linear expansion coefficient difference between them.But in this embodiment, sealing resin 151 just is filled in around LSI chip 104 and 105, so the volume of sealing resin 151 becomes littler, also can be very not big even the situation warpage degree of warpage therefore occurs.
Then, as shown in figure 39, back side grinding band 137 is attached to the back side of the upper surface and the LSI chip 104,105 of sealing resin 151.Then, silicon chip 123 is carried out grinding up to thickness being reduced to about 50 μ m.In this embodiment, sealing resin 151 is used for film wiring layer 125 is remained on support component in the flat condition.Therefore, needn't be as in the 5th embodiment of the present invention, support component 136 being installed.Then, as shown in figure 40, adopt hydrofluoric acid-nitric acid to remove remaining silicon chip 123 and metal film layer 124 by spin etch technology.Then, with hydrofluoric acid-nitric acid neutralization, cleaning and dry.
Then, as shown in figure 41, solder bump 138 is formed on the Au electrodeposited coating 128 of bottom electrode 126 of exposure.Then, as shown in figure 42, cutting band 139 is attached to the back side of the upper surface and the LSI chip 104,105 of sealing resin 151.Then, by cutting cutter 140 film wiring layer 125 and sealing resin 151 are cut and individuation.
Then, as shown in figure 43, the thin-film multilayer substrate 121 that separates is connected on the package substrate 110 by the bonding solder bump 138 that utilizes of flip-over type.Because thin-film multilayer substrate 121 bent sealing resins 151 are fixed, so this thin-film multilayer substrate 121 keeps good flatness, and the coplanarity of these solder bumps 138 is good.Therefore, the thin-film multilayer substrate 121 that can be easy to have fine structure is installed on the package substrate.Afterwards, underfilling 122 is filled between thin-film multilayer substrate 121 and the package substrate 110, and this underfilling 122 is solidified.Like this, just finished at the semiconductor device shown in Figure 36 150.
Equally, as shown in figure 44, can utilize solder flux (Ag) cream 140 radiator or fin 141 to be installed on the top of LSI chip 104,105 of semiconductor device 120 so that quicken heat radiation.
Equally, in above-mentioned manufacture process, before the back side grinding step shown in Figure 39, the back side and sealing resin 151 that as shown in figure 45 can grinding LSI chip 104,105.In other words, after the back side and sealing resin 151 of grinding LSI chip 104,105 as shown in figure 45, the grinding silicon chip 23 as shown in figure 46.Like this, can further make the upper surface planarization of LSI chip 104,105 and sealing resin 151.Also have, can reduce the thickness of semiconductor device 150.In addition, owing to reduced the volume of sealing resin 151, so can prevent warpage.
Now, will the modification that can be applied on the 5th and the 6th embodiment be described.
Figure 47 is the amplification view of a modification of film wiring layer.Promptly corresponding in the part shown in Figure 47 corresponding to the part of Figure 25 with the part " A " of Figure 24.See the film wiring layer 125 of Figure 47, wherein insulating barrier # 1 to #4 is stacked together, and electrode and wiring pattern are formed between these insulating barriers.Here, suppose to form that to compare with the insulating material that forms remaining insulating barrier # 2 to #4 from the insulating material (for example polyimides) of the nearest insulating barrier # 1 of silicon chip 123 be low-stress material (that is to say to have the material of bigger flexibility).Its reason is as follows.
In general, well-knownly be, to leave residual stress in inside making after for example the insulation film of polyimides solidifies.As in the above-described embodiment, in the situation of removing silicon chip 123 and metal film layer 12 by etch process, the insulating layer exposing with residual stress is gone out and discharge stress.In this state, as shown in figure 48, because internal residual stress crackle occurs the insulating barrier that the surface from insulating barrier exposes.Therefore, as shown in figure 47, this insulating barrier # 1 should be made by the material with high flexibility, thereby eliminates or reduce residual stress, therefore can prevent from crackle to occur in the surface of insulating barrier # 1.
Also have, after removing silicon chip 123, can utilize laser beam to form the hole bottom electrode 126 of film wiring layer 125 is exposed by spin etch.That is to say that as shown in figure 49, the Cu electrodeposited coating 140 that becomes bottom electrode 126 is formed on the insulating barrier #1.Then, remove silicon chip 123 and metal film layer 124.Then, as shown in figure 50, in insulating barrier # 1, form the hole so that expose Cu electrodeposited coating 130 by laser beam.Then, shown in Figure 51, Ni coating 129 and Au coating 128 are formed on the Cu electrodeposited coating 130 by the electroless plating coating process.
Referring now to Figure 52-54, these figure demonstrate the method that formation is in the film wiring layer 125 of individuation state at first.Figure 52 demonstrates the separated individuation step in the step that forms the film wiring layer of film wiring layer wherein.Figure 53 is the plane graph of the silicon chip of the film wiring layer that is formed with individuation on it.Figure 54 demonstrates cutting and is fixed with step at the support component of the film wiring layer shown in Figure 52 on it.
In described embodiment, make film wiring layer 125 individuations form thin-film multilayer substrate 121 by utilizing cutting technology.But, can also in the step that film wiring layer 125 is formed on the silicon chip 123, this film wiring layer 125 be divided into final size.Shown in Figure 52, when being formed on metal film layer 124 and film wiring layer 125 on the silicon chip 123, each layer of these layers is stacked by required size by for example optical lithography.Figure 53 is the plane graph of the film wiring layer that forms in this manner.That is to say, finally will not form metal film layer 124 and film wiring layer 125 with the position that cutting technology is cut.
The film wiring layer 125 (corresponding with thin-film multilayer substrate 121) that is arranged on the silicon chip 123 shown in Figure 53 is attached on the support component 136 by film of adhesiveness 135, and removes silicon chip 123 and metal film layer 124 by etch process.Then, after being formed on solder bump 138 on the film wiring layer 125, shown in Figure 54, support component 136 is carried out cutting and individuation.Along the part that does not form film wiring layer 125 support component 136 is cut.
Therefore, by forming film wiring layer 125, can reduce to connect the area of as a whole film wiring layer 125 at initial individuation state.Therefore, can reduce when removing silicon chip 123, in film wiring layer 125, to occur the possibility of crackle by etch process.Also have,, therefore can prevent the damage that causes owing to cutting technology owing to can not cut film wiring layer 135 by cutting technology.
Can be not do not form the film wiring layer, and be formed on cutting film wiring layer 125 under the state on the silicon chip 123 at film wiring layer 125 in the mode of initial individuation.Figure 55-59 demonstrates the step of cutting film wiring layer 125 when being formed on film wiring layer 125 on the silicon chip 123.
Shown in Figure 55, come individuation to be formed on film wiring layer 125 on the silicon chip 123 by cutting technology.Silicon chip 123 is not cut fully, but carries out slight cutting (hemisect) in silicon chip 123.Then, shown in Figure 56, support component 136 is attached on the film wiring layer 125 by film of adhesiveness 135.Afterwards, shown in Figure 57, reduce the thickness of silicon chip by grinding process (back side grinding).This back side grinding process can stop or can lasting till always arriving described otch before arriving this otch.
Then, shown in Figure 58, remove remaining silicon chip 123 and metal film layer 124 by spin etch technology.Then, shown in Figure 59, cutting band 139 is attached on the support component 136, thereby adhesiveness band 135 and support component 136 is cut and individuation by the cutting step.This cutting cutter 140 is thinner than the cutting cutter that is used to cut film wiring layer 125, and carries out cutting along the straight line that film wiring layer 125 has been cut.
Like this, by making film wiring layer 125 individuations in the state on being formed on silicon chip, can reduce to connect the area of as a whole film wiring layer 125.Therefore, can be reduced in the possibility that in film wiring layer 125, occurs crackle when removing silicon chip 123 by etch process.
Now, will describe the method for test according to the thin-film multilayer substrate of said method formation.
At first, shown in Figure 60, film wiring layer 125 (corresponding with thin-film multilayer substrate 121) is formed on the silicon chip 123 during, can carry out conductivity test.The thickness of this silicon chip 123 is 500-700 μ m and has rigidity.Therefore, test probe 155 can contact with the top electrode of film wiring layer 125 so that detect aspect conductivity.Therefore, can on wafer, carry out owing to test, so can test a large amount of thin-film multilayer substrates 121 effectively.
Also have, shown in Figure 61, be formed with current-carrying part 125a, these parts are passed film wiring layer 125 and are extended on the facing surfaces from metal film layer 124.Can detect thin-film multilayer substrate 121 to determine that by measuring metal film layer 124 and the electric capacity between the lip-deep wiring layer of this film wiring layer 125 it is good or bad.In this case, metal wiring layer 124 finally is removed, and therefore the function to thin-film multilayer substrate 121 does not have any influence.Also have, film wiring layer 125 can be located at and go up so that by being used to make the cutting step of film wiring layer 125 individuations remove current-carrying part 125a by the current-carrying part 125a that cutting technology is removed.
Also have, shown in Figure 62, after being formed on film wiring layer 125 (corresponding) on the silicon chip 121, test wire layer 156 can be formed on the test to be scheduled on the film wiring layer 125 with thin-film multilayer substrate 121.This test wire layer 156 can form and remove by etch process after finishing test by sputtering technology.
Then, shown in Figure 63, after removing silicon chip 123 and metal film layer 124, can under being attached to situation on the support component 136, test film wiring layer 125 by spin etch technology.Equally, in this case, because support component 136 has rigidity, so test probe 155 can contact with the top electrode of film wiring layer 125 so that test aspect conductivity.Therefore, with the similar mode of above-mentioned situation at wafer, can test a large amount of thin-film multilayer substrates 121 effectively.
In addition, the present invention is not limited to these embodiments, can make various variations and change without departing from the scope of the invention.
At first to file 2002-151050 (in application on May 24th, 2002) and 2002-235524 (in application on August 13rd, 2002), these applications here are cited as a reference the application based on Japan.
Claims (12)
1. method of making semiconductor device, this method may further comprise the steps:
A. on silicon substrate, form metal film layer;
B. form the thin-film multilayer substrate by formation conductive layer and insulating barrier in a plurality of horizontal planes on described metal film layer;
C. by bonding part support component is attached on the described thin-film multilayer substrate;
D. make described silicon substrate attenuation by back side grinding;
E. after the grinding of the described back side, remove described silicon substrate and described metal film layer;
F. with described thin-film multilayer substrate together with described support component individuation;
G. described thin-film multilayer substrate is installed on the package substrate and with described thin-film multilayer substrate and is fixed on the described package substrate;
H. reduce the adhesiveness of described bonding part, peel off described support component and described bonding part from described thin-film multilayer substrate; And
I. at least one semiconductor chip is installed on the described thin-film multilayer substrate.
2. the method for manufacturing semiconductor device as claimed in claim 1, wherein said bonding part with surface that described thin-film multilayer substrate contacts on be provided with the heat foamable jointing material, and the described step of peeling off described bonding part comprises described bonding part is heated to step more than or equal to the temperature of the blowing temperature of described heat foamable jointing material.
3. the method for manufacturing semiconductor device as claimed in claim 1, wherein said bonding part with surface that described thin-film multilayer substrate contacts on be provided with UV curing type jointing material, the described step of peeling off described bonding part comprises ultraviolet radiation is radiated at step on the described bonding part.
4. the method for manufacturing semiconductor device as claimed in claim 1, wherein in described step f, described thin-film multilayer substrate, described bonding part and described support component are cut simultaneously.
5. the method for manufacturing semiconductor device as claimed in claim 1, wherein said step e comprises that employing hydrofluoric acid-nitric acid is rotated etching.
6. the method for manufacturing semiconductor device as claimed in claim 5, wherein said step f is included in hydrofluoric acid-nitric acid and is rotated the step that etching neutralizes to hydrofluoric acid-nitric acid with neutralization reagent afterwards.
7. the method for manufacturing semiconductor device as claimed in claim 1, the material of the one deck that contacts with described metal film layer in the wherein said insulating barrier are compared with remaining insulating barrier bigger flexibility.
8. the method for manufacturing semiconductor device as claimed in claim 1 wherein after described step e, runs through the hole of described insulating barrier with formation with laser beam irradiation, thereby described conductive layer is come out in described hole on the described insulating barrier that exposes.
9. the method for manufacturing semiconductor device as claimed in claim 1 wherein before removing described silicon substrate from described thin-film multilayer substrate, is tested on described thin-film multilayer substrate.
10. the method for manufacturing semiconductor device as claimed in claim 1 is wherein tested on described thin-film multilayer substrate when described thin-film multilayer substrate is fixed on the described support component.
11. a method of making semiconductor device, this method may further comprise the steps:
A. on silicon substrate, form metal film layer;
B. form the thin-film multilayer substrate by formation conductive layer and insulating barrier in a plurality of horizontal planes on described metal film layer;
C. when described thin-film multilayer substrate is fixed on the described silicon substrate, with described thin-film multilayer substrate cutting and individuation;
D. by bonding part support component is attached on the described thin-film multilayer substrate;
E. make described silicon substrate attenuation by back side grinding;
F. after the grinding of the described back side, remove described silicon substrate and described metal film layer;
G. with described thin-film multilayer substrate together with described support component individuation;
H. described thin-film multilayer substrate is installed on the package substrate and with described thin-film multilayer substrate and is fixed on the described package substrate;
I. reduce the adhesiveness of described bonding part, peel off described support component and described bonding part from described thin-film multilayer substrate; And
J. at least one semiconductor chip is installed on the described thin-film multilayer substrate.
12. a method of making semiconductor device, this method may further comprise the steps:
A. on silicon substrate, form metal film layer, and form the thin-film multilayer substrate, make described metal film layer and described thin-film multilayer substrate by individuation by formation conductive layer and insulating barrier in a plurality of horizontal planes on described metal film layer;
B. by bonding part support component is attached on the described thin-film multilayer substrate;
C. make described silicon substrate attenuation by back side grinding;
D. after the grinding of the described back side, remove described silicon substrate and described metal film layer;
E. with described thin-film multilayer substrate together with described support component individuation;
F. described thin-film multilayer substrate is installed on the package substrate and with described thin-film multilayer substrate and is fixed on the described package substrate;
G. reduce the adhesiveness of described bonding part, peel off described support component and described bonding part from described thin-film multilayer substrate; And
H. at least one semiconductor chip is installed on the described thin-film multilayer substrate.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002151050A JP3825370B2 (en) | 2002-05-24 | 2002-05-24 | Manufacturing method of semiconductor device |
| JP151050/2002 | 2002-05-24 | ||
| JP235524/2002 | 2002-08-13 |
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|---|---|---|---|
| CNB031204309A Division CN1264207C (en) | 2002-05-24 | 2003-03-14 | Semiconductor device and its mfg. method |
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| CN100524669C true CN100524669C (en) | 2009-08-05 |
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| JP5232185B2 (en) * | 2010-03-05 | 2013-07-10 | 株式会社東芝 | Manufacturing method of semiconductor device |
| KR101383002B1 (en) * | 2012-05-25 | 2014-04-08 | 엘지이노텍 주식회사 | Semiconductor package substrate, Package system using the same and method for manufacturing thereof |
| US10474600B2 (en) | 2017-09-14 | 2019-11-12 | Samsung Electronics Co., Ltd. | Heterogeneous accelerator for highly efficient learning systems |
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| US4825284A (en) * | 1985-12-11 | 1989-04-25 | Hitachi, Ltd. | Semiconductor resin package structure |
| CN1260590A (en) * | 1998-10-28 | 2000-07-19 | 株式会社日立制作所 | Semiconductor device, semiconductor crystal wafer, semiconductor assembly and mfg. method for semiconductor device |
| CN1264923A (en) * | 1999-02-23 | 2000-08-30 | 富士通株式会社 | Semiconductor device and its mfg. method |
| CN1312347A (en) * | 2000-02-16 | 2001-09-12 | 日东电工株式会社 | Radiation-solidified therrno-stripping pressure-sensitive binder sheet material and method for making cutting cube made thereby |
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- 2002-05-24 JP JP2002151050A patent/JP3825370B2/en not_active Expired - Fee Related
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2003
- 2003-03-14 CN CNB200610089954XA patent/CN100524669C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4825284A (en) * | 1985-12-11 | 1989-04-25 | Hitachi, Ltd. | Semiconductor resin package structure |
| CN1260590A (en) * | 1998-10-28 | 2000-07-19 | 株式会社日立制作所 | Semiconductor device, semiconductor crystal wafer, semiconductor assembly and mfg. method for semiconductor device |
| CN1264923A (en) * | 1999-02-23 | 2000-08-30 | 富士通株式会社 | Semiconductor device and its mfg. method |
| CN1312347A (en) * | 2000-02-16 | 2001-09-12 | 日东电工株式会社 | Radiation-solidified therrno-stripping pressure-sensitive binder sheet material and method for making cutting cube made thereby |
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| Title |
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| JP特开2001-203237A 2001.07.27 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1855401A (en) | 2006-11-01 |
| JP3825370B2 (en) | 2006-09-27 |
| JP2003347470A (en) | 2003-12-05 |
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