CN100521517C - Preamplifier gain switching circuit and method - Google Patents
Preamplifier gain switching circuit and method Download PDFInfo
- Publication number
- CN100521517C CN100521517C CNB031540732A CN03154073A CN100521517C CN 100521517 C CN100521517 C CN 100521517C CN B031540732 A CNB031540732 A CN B031540732A CN 03154073 A CN03154073 A CN 03154073A CN 100521517 C CN100521517 C CN 100521517C
- Authority
- CN
- China
- Prior art keywords
- signal
- preamplifier
- circuit
- reference voltage
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Amplifiers (AREA)
- Optical Communication System (AREA)
Abstract
Cascaded circuit of resistor element and SW (9) is parallel connected to feedback resistance element of preamplifier, which magnifies signals of current and voltage outputted from photo detector of converting optical signal in pulse sequence into electric signal. Gain switching circuit for changing gains in preamplifier 2 is switched in order to receive output from preamplifier (2). Thus, in specific position, SW (9) is turned to on. Then, when state for making SW (10) be turned to on is occurred, if SW (9) is in on state, then at another specific position, SW (10) is turned to on.
Description
Technical field
The present invention relates to the gain commutation circuit and the method for preamplifier used in the light receiver of analyzer, monitor etc. of the optical pickup apparatus of optical communication system and light signal.
Background technology
At this,, be that example describes with the gain commutation circuit of the preamplifier of the optical pickup apparatus that is used for optical communication system for easy understanding.As optical communication system, known have for example ATM-PON (Asynchronous Transfer Mode-Passive Optical Network).This ATM-PON be as ITU-T suggestion G.983 and the optical communication system of International standardization, owing to pass through time division multiplexing mode, can realize that the point-to-multipoint that communicates with 1 office's side device and a plurality of user's set transmits, and can reduce the mode that transmits cost significantly so be expected for.
As the gain commutation circuit of the preamplifier of this optical communication system, known for example open the disclosed circuit of 2000-315923 communique (pulse train optical receiving circuit) before having the spy.Below with reference to Fig. 4～Fig. 6 summary is described.In addition, Fig. 4 is the circuit diagram of structure example of the gain commutation circuit of the existing preamplifier of expression.Fig. 5 is the sequential chart of explanation action.Fig. 6 is the figure of control flow of the gain commutation circuit of expression preamplifier shown in Figure 4.
Among Fig. 4, reception is that the preamplifier 2 of output (current signal) a of the photo detector 1 of the signal of telecommunication is made of operational amplifier 2a and feedback resistance element 2b with converting optical signals, is the transimpedance amplifier (Transimpedance Amplifier: hereinafter referred to as " TIA ") that amplifies the current signal of input and export the signal of telecommunication.
On the feedback resistance element 2b of TIA2, be connected in parallel to the series circuit, resistive element 6 of resistive element 5 and diode 8 respectively and as the series circuit of the MOS transistor 9 of switch element, resistive element 7 with as the series circuit of the MOS transistor 10 of switch element.
That is, the output of TIA2 (voltage signal) b is input to the normal phase input end (+) of identification circuit 11,12.At inverting input (-) the input reference voltage V1 of identification circuit 11, at inverting input (-) the input reference voltage V2 of identification circuit 12.At this, V1＜V2.
The output of identification circuit 11 is connected to the input end of clock C of flip-flop circuit 13, and the data input pin D of flip-flop circuit 13 is connected to power supply VH.The signal d of the data output end Q output of slave flipflop circuit 13 offers the grid of MOS transistor 9, makes MOS transistor 9 be ON.Its result, resistive element 6 is connected in parallel with feedback resistance element 2b.
In addition, the output of identification circuit 12 is connected to the input end of clock C of flip-flop circuit 14, and the data input pin D of flip-flop circuit 14 is connected to power supply VH.The signal e of the data output end Q output of slave flipflop circuit 14 offers the grid of MOS transistor 10, makes MOS transistor 10 be ON.Its result, resistive element 7 is connected in parallel with feedback resistance element 2b.
Import reset signal (RESET) c respectively from the outside to 0 reset terminal R of flip-flop circuit 13,14.Because reset signal (RESET) c imported before the input of optical pulse train signal, so flip- flop circuit 13,14 was initialised in the initial of each burst signal.Thereby MOS transistor 9,10 is at initial OFF (ending) operate condition that becomes of each burst signal.
Below, the action of the gain commutation circuit of existing preamplifier shown in Figure 4 is described with reference to figure 5.In addition, for convenience of description, be prerequisite with diode 8 idle states.
The output current wave of resistive element Fig. 5 (a) expression photo detector 1, the i.e. input current waveform of TIA2.At this, the occasion that the optical pulse train signal is input to photo detector 1 with the order of #1, #2, #3 is shown.In addition, pulse train # 1, #2, #3 are respectively the data-signals with the bit pattern of " 1010 ", and amplitude increases in proper order with this.
The waveform of output voltage (Vout) b of Fig. 5 (b) expression TIA2 and the relation of reference voltage (V1, V2).Output voltage (Vout) b of the TIA2 of paired pulses string # 1 is the level less than reference voltage.Output voltage (Vout) b of the TIA2 of paired pulses string # 2 is greater than reference voltage V 1, is not more than the level of reference voltage V 2.To output voltage (Vout) b of the TIA2 of #3 is level greater than reference voltage V 2.
Fig. 5 (c) is the waveform of reset signal (RESET) c.Shown in Fig. 5 (c), at initial input reset signal (RESET) c of each pulse train # 1, #2, #3.Like this, flip- flop circuit 13,14 becomes initialized state in each burst signal initial.MOS transistor 9,10 is in initial OFF (ending) operating state that becomes of each burst signal.That is, TIA2 becomes the original conversion gain of being determined by feedback resistance element 2b of TIA2 in each burst signal initial.
Fig. 5 (d) is the oscillogram of the action of explanation identification circuit 11,12 and flip-flop circuit 13,14 (e).Among Fig. 5 (d), because the amplitude of the pulse train # 1 of TIA2 output is less than reference voltage V 1, so identification circuit 11 is not worked, TIA2 amplifies pulse train # 1 with original conversion gain.
In the identification circuit 11,,, remain to till input reset signal (RESET) c so output level rises to level"1" from level "0" because the 1st the amplitude of pulse train # 2 surpasses reference voltage V 1.The signal d of the data output end Q output level"1" of slave flipflop circuit 13, MOS transistor 9 conductings, resistive element 6 is connected in parallel with feedback resistance element 2b.Its result, in pulse train # 2, the conversion gain of TIA2 switches to the less conversion gain of being determined by the feedback resistance value that is connected in parallel of feedback resistance element 2b and resistive element 6 from original conversion gain.
Then, in the identification circuit 11, because the 1st the amplitude of pulse train #3 has surpassed reference voltage V 1, so output level rises to level"1" from level "0".The signal d of the data output end Q output level"1" of slave flipflop circuit 13, MOS transistor 9 conductings, resistive element 7 is connected in parallel with feedback resistance element 2b.
Simultaneously, among Fig. 5 (e), in the identification circuit 12, because the 1st the amplitude of pulse train #3 has surpassed reference voltage V 2, so output level rises to level"1" from level "0".The signal e of the data output end Q output level"1" of slave flipflop circuit 14, MOS transistor 10 conductings, resistive element 7 is connected in parallel with feedback resistance element 2b.Its result, among the pulse train #3, the conversion gain of TIA2 switches to the littler conversion gain of being determined by the feedback resistance value that is connected in parallel of resistive element 2b and resistive element 6,7 from original conversion gain.
Flow chart shown in Figure 6 gathers above action is shown.Among Fig. 6, among the step S81, in the initial reception reset signal (RESET) of burst signal.That is, an input reset signal (RESET), flip- flop circuit 13,14 just is reset, and MOS transistor 9,10 is ended, and TIA2 turns back to original conversion gain.
Under this state, optical pulse train signal one is input to photo detector 1, and just whether the output level that detects TIA2 with identification circuit 11,12 has surpassed each threshold value (V1, V2) (step S82).
The output level of TIA2 (step S83 during less than reference voltage V 1; No), gain commutation circuit 31 does not make MOS transistor 9 conductings.The output level of TIA2 (step S83 during greater than reference voltage V 1; Yes), gain commutation circuit 31 makes MOS transistor 9 conductings, keeps this ON operating state (step S84).
In addition, at the output level of TIA2 (step S85 during less than reference voltage V 2; No), gain commutation circuit 31 does not make MOS transistor 10 conductings.At the output level of TIA2 (step S85 during greater than reference voltage V 2; Yes), gain commutation circuit 31 makes MOS transistor 10 conductings, keeps this ON operating state (step S86).
Like this, in the gain commutation circuit of existing preamplifier, the output level of TIA2 is set at the original conversion gain of TIA2, greater than reference voltage V 1, less than reference voltage V 2 time during less than reference voltage V 1, only make MOS transistor 9 conductings, resistive element 6 is connected in parallel with feedback resistance element 2b, when surpassing reference voltage V 2, makes MOS transistor 9,10 conductings simultaneously, resistive element 6,7 and feedback resistance element 2b are connected in parallel, switch the conversion gain of TIA2.
But, in the gain commutation circuit of existing preamplifier, as as can be known from control flow shown in Figure 6, must make MOS transistor when surpassing reference voltage owing to the output amplitude that is TIA is the structure of ON, when so various wave distortions such as transition, amplitude fluctuation, signal drop are arranged at the burst signal waveform, might not necessarily switch, and the switching that gains of the position, any position in burst signal is difficult to follow the tracks of threshold value in the initial of burst signal.In addition, also might be set at the conversion gain different because of wave distortion etc. with purpose.
Below, be specifically described with reference to figure 4, Fig. 6～Fig. 8.In addition, Fig. 7 is the sequential chart of misoperation of the gain commutation circuit of explanation preamplifier shown in Figure 4.Fig. 8 is the figure of expression as the input-output characteristic of the TIA2 of preamplifier shown in Figure 4.
Among Fig. 7, the output current wave of Fig. 7 (a ') expression photo detector 1, the i.e. input current waveform of TIA2.At this, the optical pulse train signal is input to photo detector 1 with the order of the 1st pulse train, the 2nd pulse train situation is shown.In addition, the 1st pulse train, the 2nd pulse train are respectively the data-signals with the bit pattern of " 1010 ", and amplitude increases in proper order with this.In each pulse train, can see bigger wave distortions such as transition at the rising part of each " 1 " position.
The waveform of the output voltage (Vout) of Fig. 7 (b ') expression TIA2 and the relation of reference voltage (V1, V2).In the output waveform to the TIA2 of the 1st pulse train, the waveform shown in the dotted line 61 is the purpose signal waveform, and level and reference voltage V 1 are about equally.On the other hand, the waveform shown in the solid line 62 is the waveform that becomes the reason that causes misoperation, illustrates to have because of transition and amplitude fluctuation etc., surpasses and be no more than the occasion of reference voltage V 1 at random.
In addition, in the output waveform to the TIA2 of the 2nd pulse train, the waveform shown in the dotted line 63 is the purpose signal waveform, level for greater than reference voltage V 1, be not more than reference voltage V 2.On the other hand, the waveform shown in the solid line 64 is the waveform that becomes the reason that causes misoperation, is illustrated in the 1st bigger signal depression Td that has above reference voltage V 2, and afterwards everybody falls to the state less than reference voltage V 1 significantly.
Fig. 7 (c ') be the waveform of reset signal (RESET).Shown in Fig. 7 (c '), reset signal (RESET) is transfused in that each of the 1st pulse train, the 2nd pulse train is initial.Thus, flip- flop circuit 13,14 becomes initialized state in each burst signal initial.MOS transistor 9,10 is in initial OFF (ending) operating state that becomes of each burst signal.That is, TIA2 becomes the original conversion gain of being determined by feedback resistance element 2b of TIA2 in each burst signal initial.
Fig. 7 (d ') (and e ') be the oscillogram of the action of explanation identification circuit 11,12 and flip-flop circuit 13,14.Fig. 7 (d ') in, if the signal waveform of the 1st pulse train of TIA2 output is the purpose signal waveform shown in the dotted line 61 among Fig. 7 (b '), because the 1st amplitude surpasses reference voltage V 1, so identification circuit 11 can be the 1st correct position identification, shown in dotted line 65, make MOS transistor 9 conductings since the 1st the moment.
But, if the signal waveform of the 1st pulse train of TIA2 output is the waveform shown in the solid line 62 among Fig. 7 (b '), may occur not only the 1st position, and after position, any position surpass the situation of reference voltage V 1, and the position, any position in burst signal makes MOS transistor 9 conductings.For example, shown in solid line 66, make the MOS transistor conducting, in the way of burst signal, carry out the switching of conversion gain since the 5th position.
In addition, among Fig. 7 (e '), if the signal waveform of the 2nd pulse train of TIA2 output be the purpose signal waveform shown in the dotted line 63 among Fig. 7 (b ') since the 1st amplitude only above reference voltage V 1, be no more than reference voltage V 2, so have only identification circuit 11 work, identification circuit 12 is not worked.At this moment, shown in dotted line 67, since the 1st the moment, MOS transistor 10 is kept and is ended, and shown in Fig. 7 (d '), has only MOS transistor 9 conductings.
But, if the signal waveform of the 1st pulse train of TIA2 output be shown in the solid line 64 among Fig. 7 (b ') have the waveform that bigger signal drops the time, owing to surpass reference voltage V 2 the 1st position, so identification circuit 12 is also discerned, shown in solid line 68, also make MOS transistor 10 conductings since the 1st the moment.That is, at this moment, be the purpose gain with the conversion gain that feedback resistance element 2b is connected in parallel only, but can be set at the conversion gain different that output amplitude is littler than purpose amplitude with the purpose that again output element 7 also is connected in parallel with resistive element 6.
Below, Fig. 8 is the figure that the utilization and the relation of the input-output characteristic of TIA2 illustrate above action.Among Fig. 8, the action shown in Figure 5 of characteristic 71,72,73 correspondences.That is, characteristic 71 is as pulse train # 1, the input-output characteristic when TIA2 moves with original conversion gain.Then, among the pulse train # 2, because at the gain switching point A as the moment that surpasses reference voltage V 1, MOS transistor 9 conductings are so the switching that gains becomes the input-output characteristic of characteristic 72.In addition, among the pulse train #3, because at the gain switching point B as the moment that surpasses reference voltage V 2, MOS transistor 9,10 conductings are so the switching that gains becomes the input-output characteristic of characteristic 73.
Different therewith, in the action shown in Figure 7, the level of the 1st pulse train is identical with reference voltage V 1, the level of promptly approaching gain switching point.Therefore, because of the transition of waveform and the fluctuation of amplitude etc. occur, not only the 1st position, after position, any position surpass the situation of reference voltage V 1, the position, any position in burst signal makes MOS transistor 9 conductings.
In addition, in the 2nd pulse train, when surpassing reference voltage V 2, make MOS transistor 9,10 conductings the 1st position because of the transition of the 1st digit wave form etc. is wrong.Thereby gain switching point B moves to the gain switching point B ' of little amplitude side, and characteristic 73 becomes from the characteristic 74 of the gain switching point B ' beginning of little amplitude side, so output amplitude becomes the amplitude also more much smaller than purpose amplitude.
Summary of the invention
Thereby, only the object of the present invention is to provide and to implement gain in the specific bit-position of burst signal and switch, can switch to the gain commutation circuit and the method for preamplifier of suitable conversion gain of the level of corresponding each burst signal.
The gain commutation circuit of preamplifier of the present invention is that the converting optical signals that amplifies pulse series shape is the output current of the photo detector of the signal of telecommunication, and in the preamplifier of output voltage signal, switch the gain commutation circuit of conversion gain of preamplifier that is connected in parallel to the series circuit of the series circuit of the 1st resistive element and the 1st switch element and the 2nd resistive element and the 2nd switch element with the feedback resistance element respectively, it is characterized in that, receive the output of above-mentioned preamplifier, make above-mentioned the 1st switch element conducting in specific bit-position, then, when having taken place to make the situation of above-mentioned the 2nd switch element conducting, with above-mentioned the 1st switch element conducting is condition, makes above-mentioned the 2nd switch element conducting in another specific bit-position.
According to this invention, the gain commutation circuit receives with the feedback resistance element and is connected in parallel to the series circuit of the 1st resistive element and the 1st switch element and the series circuit of the 2nd resistive element and the 2nd switch element respectively, amplification is the output of the preamplifier of the output current of photo detector of the signal of telecommunication and output voltage signal with the converting optical signals of pulse series shape, make above-mentioned the 1st switch element conducting in specific bit-position, then, when having taken place to make the situation of above-mentioned the 2nd switch element conducting, with above-mentioned the 1st switch element conducting is condition, makes above-mentioned the 2nd switch element conducting in another specific bit-position.
The gain commutation circuit of the preamplifier of next invention is characterised in that: in foregoing invention, be connected in parallel to the series circuit of the 3rd resistive element and diode with the above-mentioned feedback resistance element of above-mentioned preamplifier.
According to this invention, in foregoing invention, be connected in parallel to the series circuit of the 3rd resistive element and diode with the above-mentioned feedback resistance element of above-mentioned preamplifier.
The gain commutation circuit of the preamplifier of next invention is characterised in that: in foregoing invention, above-mentioned gain commutation circuit has: when the output level of above-mentioned preamplifier surpasses the 1st reference voltage, produce the 1st gate signal in above-mentioned specific bit-position, then, produce the gate signal production part of the 2nd gate signal in above-mentioned another certain bits; When the output level of above-mentioned preamplifier surpassed than big the 2nd reference voltage of above-mentioned the 1st reference voltage, the time when surpassing above-mentioned the 2nd reference voltage made the 1st functional unit of above-mentioned the 1st switch element conducting in the generation time section of above-mentioned the 1st gate signal the time; When the output level of above-mentioned preamplifier surpasses than big the 3rd reference voltage of above-mentioned the 2nd reference voltage, time when surpassing above-mentioned the 3rd reference voltage is in the generation time section of above-mentioned the 2nd gate signal, and, when making above-mentioned the 1st switch element conducting, make the 2nd functional unit of above-mentioned the 2nd switch element conducting.
According to this invention, in foregoing invention, when the gain commutation circuit surpasses the 1st reference voltage at the output level of above-mentioned preamplifier, at first produce the 1st gate signal in specific bit-position with the gate signal production part, then, produce the 2nd gate signal in above-mentioned another specific bit-position.Its result, when the output level of above-mentioned preamplifier surpasses than big the 2nd reference voltage of above-mentioned the 1st reference voltage, and the time when surpassing above-mentioned the 2nd reference voltage utilizes the 1st functional unit to make above-mentioned the 1st switch element conducting in the generation time section of above-mentioned the 1st gate signal the time.In addition, when the output level of above-mentioned preamplifier surpasses than big the 3rd reference voltage of above-mentioned the 2nd reference voltage, time when surpassing above-mentioned the 3rd reference voltage is in the generation time section of above-mentioned the 2nd gate signal, and during above-mentioned the 1st switch element conducting, utilize the 2nd functional unit to make above-mentioned the 2nd switch element conducting.
The gain commutation circuit of the preamplifier of next invention is characterised in that: in foregoing invention, above-mentioned gain commutation circuit has: the output level of above-mentioned preamplifier surpass the 1st reference voltage during in the 1st level sensitive circuit of output pulse signal; The output level of above-mentioned preamplifier surpass 2nd reference voltage bigger than above-mentioned the 1st reference voltage during in the 2nd level sensitive circuit of output pulse signal; The output level of above-mentioned preamplifier surpass 3rd reference voltage bigger than above-mentioned the 2nd reference voltage during in the 3rd level sensitive circuit of output pulse signal; Generate respectively will begin from the trailing edge of the reset signal of outside input till the trailing edge of the output pulse signal of above-mentioned the 1st level sensitive circuit of the above-mentioned specific bit-position of correspondence during as the 1st gate signal of pulse duration, will begin from the trailing edge of above-mentioned the 1st gate signal till the trailing edge of the output pulse signal of above-mentioned the 1st level sensitive circuit of above-mentioned another specific bit-position of correspondence during as the gate signal generative circuit of the 2nd gate signal of pulse duration; When in the pulse duration of above-mentioned the 1st gate signal, importing the output pulse signal of above-mentioned the 2nd level sensitive circuit, export the 1st decision circuitry of the 1st judgement signal; Keep the above-mentioned the 1st to judge signal in during before the above-mentioned reset signal of input, make the 1st holding circuit of above-mentioned the 1st switch element conducting; When in the pulse duration of above-mentioned the 2nd gate signal, importing the output pulse signal of above-mentioned the 3rd level sensitive circuit, export the 2nd decision circuitry of the 2nd judgement signal; The 2nd holding circuit that keeps above-mentioned the 2nd judgement signal in during before the above-mentioned reset signal of input; Keep and export the above-mentioned the 1st and judge under the situation of signal in above-mentioned the 1st holding circuit, when above-mentioned the 2nd holding circuit keeps and exported the above-mentioned the 2nd when judging signal, according to the output of above-mentioned the 2nd holding circuit, make the 3rd decision circuitry of above-mentioned the 2nd switch element conducting.
According to this invention, in foregoing invention, the output of preamplifier is input to the 1st～the 3rd level sensitive circuit respectively.In the 1st level sensitive circuit, the output level of preamplifier surpass the 1st reference level during in during output pulse signal, the trailing edge that the gate signal generative circuit generates the reset signal that will import from the outside respectively begin till the trailing edge of the output pulse signal of above-mentioned the 1st level sensitive circuit of the above-mentioned specific bit-position of correspondence during as the 1st gate signal of pulse duration, to begin from the trailing edge of above-mentioned the 1st gate signal till the trailing edge of the output pulse signal of the 1st level sensitive circuit of corresponding another specific bit-position during as the 2nd gate signal of pulse duration.In the 2nd level sensitive circuit, the output level of preamplifier surpass 2nd reference voltage bigger than above-mentioned the 1st reference voltage during in during output pulse signal, when the 1st decision circuitry is imported the output pulse signal of the 2nd level sensitive circuit in the pulse duration of above-mentioned the 1st gate signal, export the 1st and judge signal.Its result, the 1st holding circuit input before the above-mentioned reset signal during in keep the 1st to judge signal, the 1st switch element conducting is in the conversion gain switching of being implemented preamplifier by the specific bit-position of the 1st gate signal regulation.In addition, in the 3rd level sensitive circuit, the output level of preamplifier surpass 3rd reference voltage bigger than above-mentioned the 2nd reference voltage during in during output pulse signal, when the 2nd decision circuitry is imported the output pulse signal of the 3rd level sensitive circuit in the pulse duration of above-mentioned the 2nd gate signal, export the 2nd and judge signal, the 2nd holding circuit before the above-mentioned reset signal of input during in keep the 2nd judgement signal.When the 3rd decision circuitry keeps output the above-mentioned the 1st to judge signal in above-mentioned the 1st holding circuit, when above-mentioned the 2nd holding circuit keeps output the above-mentioned the 2nd to judge signal,, make the 2nd switch element conducting according to the output of above-mentioned the 2nd holding circuit.Its result switches to the new conversion gain of the 1st switch element and the 1st switch element conducting simultaneously work in the specific bit-position by the 2nd gate signal regulation.
The gain commutation circuit of the preamplifier of next invention is characterised in that: in foregoing invention, the degree of the wave distortion that occurs in the output signal of above-mentioned preamplifier is considered in the setting of above-mentioned the 1st reference voltage, makes between itself and above-mentioned the 2nd reference voltage to have bigger voltage difference.
According to this invention, in foregoing invention, the degree of the wave distortion that occurs in the output signal of preamplifier is considered in the setting of the 1st reference voltage, makes between itself and the 2nd reference voltage to have bigger voltage difference.
The gain commutation circuit of the preamplifier of next invention is characterised in that: in foregoing invention, the feedback resistance element of above-mentioned preamplifier also is connected in parallel to the series circuit of N (N 〉=3) resistive element and switch element respectively, above-mentioned gain commutation circuit receives the output of above-mentioned preamplifier, then, taking place to make i (during the situation of the switch element conducting of series circuit of 3≤i≤N), switch element conducting work with all series circuits before above-mentioned i the series circuit is condition, makes the switch element conducting of above-mentioned i series circuit in corresponding specific bit-position.
According to this invention, in foregoing invention, when the feedback resistance element of preamplifier also is connected with the series circuit of N (N 〉=3) resistive element and switch element respectively, the output of gain commutation circuit receiving preamplifier, then, taking place to make i (during the situation of the switch element conducting of the series circuit of 3≤i≤N), switch element conducting with all series circuits before above-mentioned i the series circuit is operating as condition, in the switch element conducting of corresponding above-mentioned i the series circuit of specific bit-position.
The gain changing method of the preamplifier of next invention be with the converting optical signals that amplifies pulse series shape be the output current of the photo detector of the signal of telecommunication, and the feedback resistance element of the preamplifier of output voltage signal is connected in parallel to the series circuit of the 1st resistive element and the 1st switch element, the series circuit of the 2nd resistive element and the 2nd switch element, make above-mentioned the 1st switch element and above-mentioned the 2nd switch element conducting or end, switch the gain changing method of the conversion gain of above-mentioned preamplifier, it is characterized in that, comprise the output that receives above-mentioned preamplifier, make above-mentioned the 1st switch element conducting in specific bit-position, then, when having taken place to make the situation of above-mentioned the 2nd switch element conducting, with above-mentioned the 1st switch element conducting work is condition, makes the operation of above-mentioned the 2nd switch element conducting in another specific bit-position.
According to this invention, be connected in parallel to the series circuit of the 1st resistive element and the 1st switch element with the feedback resistance element, the series circuit of the 2nd resistive element and the 2nd switch element, receiving the converting optical signals that amplifies pulse series shape is the output current of the photo detector of the signal of telecommunication, and the output of the preamplifier of output voltage signal, above-mentioned the 1st switch element is operated in the specific bit-position conducting, then, when having taken place to make the situation of above-mentioned the 2nd switch element conducting, with above-mentioned the 1st switch element conducting work is condition, makes above-mentioned the 2nd switch element conducting in another specific bit-position.
The gain changing method of the preamplifier of next invention is characterised in that: in foregoing invention, when the feedback resistance element that is included in above-mentioned preamplifier also is connected in parallel to the series circuit of N (N 〉=3) resistive element and switch element respectively, receive the output of above-mentioned preamplifier, then, taking place to make i (during the situation of the switch element conducting of the series circuit of 3≤i≤N), switch element conducting work with all series circuits before above-mentioned i the series circuit is condition, makes the operation of the switch element conducting of above-mentioned i series circuit in corresponding specific bit-position.
According to this invention, in foregoing invention, when the feedback resistance element of preamplifier also is connected in parallel to the series circuit of N (N 〉=3) resistive element and switch element respectively, the output of receiving preamplifier, then, taking place to make i (during the situation of the switch element conducting of the series circuit of 3≤i≤N), switch element conducting work with all series circuits before above-mentioned i the series circuit is condition, makes the switch element conducting of above-mentioned i series circuit in corresponding specific bit-position.
Description of drawings
Fig. 1 is the circuit diagram of structure of gain commutation circuit of the preamplifier of expression one embodiment of the invention.
Fig. 2 is the sequential chart of action example of the gain commutation circuit of explanation preamplifier shown in Figure 1.
Fig. 3 is the figure of control flow of the gain commutation circuit of expression preamplifier shown in Figure 1.
Fig. 4 is the circuit diagram of structure example of the gain commutation circuit of the existing preamplifier of expression.
Fig. 5 is the sequential chart of action of the gain commutation circuit of explanation preamplifier shown in Figure 4.
Fig. 6 is the figure of control flow of the gain commutation circuit of expression preamplifier shown in Figure 4.
Fig. 7 is the sequential chart of misoperation of the gain commutation circuit of explanation preamplifier shown in Figure 4.
Fig. 8 is the figure of the input-output characteristic of expression preamplifier shown in Figure 4.
Embodiment
Below, describe the gain commutation circuit of preamplifier of the present invention and the most preferred embodiment of method with reference to the accompanying drawings in detail.
Fig. 1 is the circuit diagram of structure of gain commutation circuit of the preamplifier of expression one embodiment of the invention.Among Fig. 1, reception is that the preamplifier 2 of output (current signal) A of the photo detector 1 of the signal of telecommunication is to be made of operational amplifier 2a and feedback resistance element 2b with converting optical signals, be the current signal that amplifies input, and the transimpedance amplifier (TIA) of output voltage signal.The feedback resistance element 2b of TIA2 be connected in parallel to respectively resistive element 5 and diode 8 series circuit, resistive element 6 and as the MOS transistor 9 of switch element (below, be called " SW9 ") series circuit, resistive element 7 and as the series circuit of the MOS transistor 10 of switch element (below, be called " SW10 ").More than structure with shown in Figure 4 identical.
The series circuit of resistive element 5 and diode 8 is not set in addition, sometimes.If consider the series circuit of resistive element 5 and diode 8, the conversion gain of the TIA2 of SW9,10 when the OFF operate condition becomes gain of being determined by the value of feedback resistance element 2b or the gain of being determined by the parallel resistance value of feedback resistance element 2b and resistive element 5.At this, for easy explanation, ignore the series circuit of resistive element 5 and diode 8, suppose that the gain of being determined by the value of feedback resistance element 2b is the original conversion gain of TIA2.
The gain commutation circuit 3 of this embodiment has level sensitive circuit 15,16,17, the pupil becomes circuit 18, decision circuitry 19,20,21, level holding circuit 22,23, implementing gain in the position, position of burst signal switches, then, when different gain switch reasons has taken place, do not carry out change action separately, but be condition with the gain change action that must carry out 1 front, implement gain in another specific bit-position and switch, can switch to the suitable conversion gain of the level of corresponding each burst signal.
At this, as the one example, the bit pattern that is illustrated in each burst signal is during for " 1010 ", implementing gain the 1st position switches, afterwards, when the gain switch reasons having taken place, do not carry out change action separately the 3rd position, but be condition having carried out the gain change action the 1st position, the structure example when implementing gain the 3rd position and switching.
That is, the output of TIA2 (voltage signal) B is input to an input of level sensitive circuit 15,16,17.In another input input of level sensitive circuit 15 reference voltage V 0 as the 1st reference voltage.In another input input of level sensitive circuit 16 reference voltage V 1 as the 2nd reference voltage.In another input input of level sensitive circuit 17 reference voltage V 2 as the 3rd reference voltage.At this, V0＜V1＜V2.
The output D of level sensitive circuit 15 is input to the pupil and becomes circuit 18, and the pupil becomes the output E (the 1st gate signal) of circuit 18, the input that H (the 2nd gate signal) is input to decision circuitry 19,20 respectively.The output F of level sensitive circuit 16 is input to another input of decision circuitry 19, and the output I of level sensitive circuit 17 is input to another input of decision circuitry 20.
The output of decision circuitry 19 is input to level holding circuit 22, and the output G of level holding circuit 22 becomes the control signal of SW9, is input to an input of decision circuitry 21 simultaneously.The output of decision circuitry 20 is input to level holding circuit 23, and the output of level holding circuit 23 is input to another input of decision circuitry 21.The output J of decision circuitry 21 becomes the control signal of SW10.
In addition, become circuit 18 and level holding circuit 22,23 to import reset signal (RESET) C respectively from the outside the pupil.Owing to before the input optical pulse string signal, import reset signal (RESET) C, so the pupil becomes circuit 18 and level holding circuit 22,23 to be initialised in the initial of each burst signal.Thereby, SW9,10 initial OFF (ending) operate conditions that become at each burst signal.
Below, the action of gain commutation circuit of the preamplifier of this embodiment is described with reference to figure 1～Fig. 3.In addition, Fig. 2 is the sequential chart of action example of the gain commutation circuit of explanation preamplifier shown in Figure 1.Fig. 3 is the figure of control flow of the gain commutation circuit of expression preamplifier shown in Figure 1.
The action of one example gain commutation circuit at first, is described with reference to figure 1, Fig. 2.Among Fig. 2,, the action example with identic burst signal shown in Figure 5 is shown for easy understanding.
That is, the output current wave of Fig. 2 (A) expression photo detector 1, promptly the input current waveform of TIA2 illustrates the optical pulse train signal is input to photo detector 1 with the order of pulse train # 1, #2, #3 situation.In addition, pulse train # 1, #2, #3 are respectively the data-signals with " 1010 " bit pattern, and amplitude increases in proper order with this.
Fig. 2 (B) illustrates the waveform of output voltage (Vout) B of TIA2 and the relation of reference voltage (V0, V1, V2).Output voltage (Vout) B of the TIA2 of paired pulses string # 1 is the level less than reference voltage V 0.Output voltage (Vout) B of the TIA2 of paired pulses string # 2 is the level that surpasses reference voltage V 1, is no more than reference voltage V 2.Output voltage (Vout) B of the TIA2 of paired pulses string #3 is the level that surpasses reference voltage V 2.
Fig. 2 (C) is the waveform of reset signal (RESET) C.Shown in Fig. 2 (C), reset signal (RESET) C is in each initial input of pulse train # 1, #2, #3.Like this, the pupil becomes circuit 18 and level holding circuit 22, the 23 initial state that is initialised that becomes at each burst signal.In addition, SW9,10 initial OFF (ending) operate conditions that become at each burst signal.That is, TIA2 becomes the original conversion gain of being determined by feedback resistance element 2b of TIA2 in each burst signal initial.
Fig. 2 (D) is the oscillogram of the action of expression level sensitive circuit 15.Because pulse train # 1 is less than reference voltage V 0, so the output D of level sensitive circuit 15 is a level "0".Because pulse train # 2, #3 surpass reference voltage V 0, so the output D of level sensitive circuit 15 becomes the every mutual waveform that repeats level"1" and level "0" of respective pulses string signal.
Fig. 2 (E) is that the expression pupil becomes circuit 18 to produce the oscillogram of the action of the 1st gate signal E.Among the pulse train # 1, before pulse train # 1, the rising edge of response reset signal (RESET) C and being initialised responds the trailing edge of its reset signal (RESET) C and makes output become level"1".Because the output D of level sensitive circuit 15 is a level "0", so the pupil becomes circuit 18 that the output of this level"1" is maintained until till importing reset signal (RESET) C before next pulse train # 2, in case input just is initialised, make output become level "0".
In addition, before pulse train # 2, the trailing edge of response reset signal (RESET) C makes output E become level"1".Specifically, because the output of level sensitive circuit 15 becomes level"1" and the mutual waveform that repeats of level "0", so the output of level sensitive circuit 15 becomes level"1" at first, drop to the level "0" position during in, the pupil becomes circuit 18 will export E to maintain level"1".Also carry out identical action for pulse train #3.
At this, the position that the output of level sensitive circuit 15 becomes level"1" at first is the 1st position.That is, the pupil becomes circuit 18 under level sensitive circuit 15 detects situation above the burst signal of reference voltage V 0, and like this, generation will begin till the 1st the terminal the 1st gate signal E as pulse duration from the trailing edge of reset signal (RESET) C.The 1st gate signal E offers decision circuitry 19.
Fig. 2 (H) is that the expression pupil becomes circuit 18 to generate the oscillogram that the back produces the action of the 2nd gate signal H at the 1st gate signal E.Shown in Fig. 2 (H), the pupil becomes in the circuit 18, and since the trailing edge of the 1st gate signal E, the output of level sensitive circuit 15 becomes level"1" the 2nd time, till dropping to level "0" during in, will export H and maintain level"1".The position that the output of level sensitive circuit 15 becomes level"1" for the 2nd time is the 3rd position.That is, the pupil become circuit 18 produce will be till the terminal of 3 of the trailing edges to the of the 1st gate signal E as the 2nd gate signal H of pulse duration.The 2nd gate signal H offers decision circuitry 20.
Fig. 2 (F) is the oscillogram of the action of expression level sensitive circuit 16.Because pulse train # 1 is less than reference voltage V 0, so the output of level sensitive circuit 16 becomes level "0".Among the pulse train # 2 because the 1st surpass reference voltage V 1, so the time period that will surpass reference voltage V 1 the 1st time output to decision circuitry 19 as the detection pulse signal F of pulse duration.
In addition, among the pulse train #3, because the 1st and the 3rd surpass reference voltage V 1, so will output to decision circuitry 19 above time period of reference voltage V 1 as the detection pulse signal F of pulse duration in time of the 1st and the 3rd.
Fig. 2 (G) is the oscillogram of the action of expression decision circuitry 19 and level holding circuit 22.Because pulse train # 1 is less than reference voltage V 0, so not input of decision circuitry 19.For pulse train # 1, TIA2 amplifies action with original conversion gain.
Different therewith, among the pulse train # 2, at decision circuitry 19 input the 1st gate signal E and detection pulse signal F.In the decision circuitry 19, only in the time period of the 1st gate signal E, imported the occasion that detects pulse signal F, the SW control signal has been outputed to level holding circuit 22.Level holding circuit 22 offers the grid of SW9 with the SW control signal of input as SW operation signal G, also outputs to decision circuitry 21 simultaneously, remains to till input reset signal (RESET) C, makes SW9 continue conducting.Among the TIA2,, switch to by the definite less conversion gain of the parallel resistance value of feedback resistance element 2b and resistive element 6 from original conversion gain at the 1st for pulse train # 2.
Too, 22 work of decision circuitry 19 and level holding circuit make SW9 continue conducting among the pulse train #3, but because the 3rd of pulse train #3 surpasses reference voltage V 2, so parallelly carry out the action of Fig. 2 (I) shown in (J).
Fig. 2 (I) is the oscillogram of the action of expression level sensitive circuit 17.Because pulse train # 1 and pulse train # 2 are less than reference voltage V 2, so the output of level sensitive circuit 17 becomes level "0".
Different therewith, among the pulse train #3, because the 1st and the 3rd surpass reference voltage V 2, so will output to decision circuitry 20 above time period of reference voltage V 2 as the detection pulse signal I of pulse duration in time of the 1st and the 3rd.
Fig. 2 (J) is the oscillogram of the action of expression decision circuitry 20, level holding circuit 23 and decision circuitry 21.In the decision circuitry 20, only the occasion of input detection pulse signal I in the time period of the 2nd gate signal H outputs to level holding circuit 23 with the SW control signal.That is, the detection pulse signal I that produces the 1st position is because in the time period of the 2nd gate signal H, so be considered as invalidly, the detection pulse signal I that produces the 3rd position is because in the time period of the 2nd gate signal H, so effectively.
Level holding circuit 23 outputs to decision circuitry 21 with the SW control signal of input, is retained to till input reset signal (RESET) C.Decision circuitry 21 when SW operation signal G remains on level"1", will offer the grid of SW10 from the SW control signal of level holding circuit 23 inputs as SW operation signal J from level holding circuit 23 input SW control signals the time.
Its result, among the TIA2, for pulse train #3, switch to the less conversion gain of determining by the parallel resistance value of feedback resistance element 2b and resistive element 6 the 1st position from original conversion gain, afterwards, switch to the littler conversion gain of the resistive element 7 that further is connected in parallel the 3rd position.
At this,, consider action to this example of the 1st pulse train shown in Figure 7 or the 2nd pulse train according to above action specification.For the 1st pulse train,, then, switch so carry out the gain of TIA2 since the 1st position owing to utilize the 1st gate signal E reliably to catch if surpass reference voltage V 1 at the 1st.On the other hand, even surpass reference voltage V 1 later on, also, switch so in the way of the 1st pulse train, do not carry out the gain of TIA2 owing to do not produce the 1st gate signal E at the 1st.
In addition, for the 2nd pulse train, when being the signal of the waveform shown in the solid line 64, owing to surpass reference voltage V 1 and reference voltage V 2 the 1st position, detect pulse signal F and detect pulse signal I so produce, but, do not produce the 2nd gate signal owing to only produce the 1st gate signal E, switch so only carry out the gain of the TIA2 of SW9 since the 1st position, can mistake not make also conducting of SW10.
Among this embodiment, the burst signal waveform is considered various distortions such as transition, amplitude fluctuation, signal drop as shown in Figure 7, makes the interval of reference voltage V 0 and reference voltage V 1 bigger.Like this, even lose genuine occasion in signal waveform, the level that arrives does not to a certain degree use before SW9 to implement the gain switching.That is, can frequently not carry out the unnecessary gain in ground switches.
Below, along Fig. 3, with reference to the general action of figure 1 explanation.In addition, among Fig. 3, SW1 represents SW9, and SW2 represents SW10.Among the S1, in the initial reception reset signal (RESET) of burst signal.That is, an input reset signal (RESET), the pupil becomes circuit 18 and level holding circuit 22,23 just to be reset, and SW1, SW2 become the OFF state, and TIA2 turns back to original conversion gain.
Under this state, when the optical pulse train signal was input to photo detector 1, whether the output level that detects TIA2 with level sensitive circuit 15,16,17 had surpassed each threshold value (V0, V1, V2) (step S2).Do not surpassing reference voltage V 0 (step S3:No) or surpassing reference voltage V 1 (step S4:No), when not surpassing reference voltage V 2 when (step S5:No), SW1, SW2 are not controlled.
When surpassing reference voltage V 0 (step S3:Yes), generation will begin till the terminal of the 1st position the 1st gate signal (step S31) as pulse duration from the trailing edge of reset signal (RESET), and generate will be till the terminal of 3 positions of trailing edge to the of the 1st gate signal as the 2nd gate signal (step S32) of pulse duration.
When surpassing reference voltage V 1 when (step S4:Yes), judge this time that surpasses whether with time consistent (step S41) of the 1st gate signal that generates at step S31.(step S41 when unanimity; Yes), make the SW conducting, keep this state (step S42).On the other hand, (step S41 when inconsistent; No), do not make the SW1 conducting, the finishing control action.Thus, only in specific bit-position (the 1st the position) switching that gains, prevent the switching that gains of position, any position in burst signal.
When surpassing reference voltage V 2 (step S5:Yes), judge this time that surpasses whether with time consistent (step S51) of the 2nd gate signal that generates at step S32.(step S51 when inconsistent; No), do not make the SW2 conducting, finishing control action, but (step S51 when consistent; Yes), judge whether SW1 becomes ON operate condition (step S52), (step S52 when SW1 becomes the ON operate condition in step S42; Yes) time, make the SW2 conducting, keep this state (step S53) in another specific bit-position (the 3rd position).On the other hand, (step S52 when SW1 does not become the ON operate condition; No), do not make the SW2 conducting, the finishing control action.
Like this, carried out the SW1 operation, but in the time also should operating SW2 originally, the both sides at another specific bit-position (the 3rd position) reliable operation SW1 and SW2 can be set at suitable conversion gain in the specific bit-position that should operate SW1 of going ahead of the rest (the 1st position).In addition, when the specific bit-position that should operate SW1 of going ahead of the rest (the 1st position) is not carried out the SW1 operation, even do not carry out the operation of SW2, so prevent to be set at wrong conversion gain owing to having produced the reason that to operate SW2 yet.
Among the TIA, when SW1 that utilization and feedback resistance element are arranged in parallel and SW2 had switched feedback resistance value by each received pulse string, if because of switching reduces feedback resistance value, then because the high-frequency cut-off frequency becomes greatly, so phase margin diminishes, circuit vibrated easily.Known can employing and the parallel method that reduces the open-loop gain of TIA of operation of SW1 and SW2 avoid this problem.The control signal of operating above-mentioned SW1 and SW2 certainly becomes the control signal of the open-loop gain that reduces TIA simultaneously.
In addition, under the situation of the series circuit that is provided with resistive element 5 and diode 8, certainly smooth and easyly carry out above-mentioned action.In addition, the form of the bit pattern of burst signal for " 1010 " has been described, but, can be suitable for the present invention so long as " 1 " follows the pattern of " 0 " afterwards.For example, can be " 110110 ", " 11001100 " or bit patterns such as " 11101110 ".In addition, for convenience of description, show the occasion that the amplitude of each burst signal of input increases successively, even but amplitude is constant certainly, also can move equally.
In addition, among this embodiment,, enumerated the example of the 1st position and the 3rd position, but also can determine according to the above-mentioned bit pattern that adopts or the characteristic of burst signal etc. as specific bit-position.In addition, the preamplifier of the optical pickup apparatus that is applicable to optical communication system has been described, but can certainly be equally applicable to the used preamplifier of light receiver such as analyzer, monitor of light signal.
In addition, among this embodiment, the occasion that 2 switch elements are arranged has been described, but has the invention is not restricted to this that series circuit of switch element and resistive element also can be 1, any number more than 3 also can be set.Promptly, gain commutation circuit 3 when any number more than 3 is set is for the switch element of the 3rd later series circuit, produced and to have made i (during the situation of the switch element conducting of the series circuit of 3≤i≤N), switch element conducting with all series circuits before above-mentioned i the series circuit is a condition, in corresponding specific bit-position the switch element conducting of above-mentioned i series circuit is got final product.
As mentioned above, according to this invention, in the gain commutation circuit, receive the series circuit that the feedback resistance element is connected in parallel to the 1st resistive element and the 1st switch element respectively, the series circuit of the 2nd resistive element and the 2nd switch element, amplification is the output current of the photo detector of the signal of telecommunication with the converting optical signals of pulse series shape, and the output of the preamplifier of output voltage signal, make above-mentioned the 1st switch element conducting in specific bit-position, then, when having taken place to make the situation of above-mentioned the 2nd switch element conducting, with above-mentioned the 1st switch element conducting is condition, makes above-mentioned the 2nd switch element conducting in another specific bit-position.Thereby, can reliably implement the switching of conversion gain in the specific bit-position of burst signal, can prevent reliably that the position, any position in burst signal from carrying out the conversion gain switching.In addition, when having taken place to make the situation of the 2nd switch element conducting, owing to, make the 2nd switch element conducting so that the 1st switch element work of prerequisite activity is condition, so not only can be set at suitable conversion gain, but also can prevent to be set at wrong conversion gain.
According to next invention, in the foregoing invention, in the above-mentioned preamplifier, above-mentioned feedback resistance element and then be connected in parallel to the series circuit of the 3rd resistive element and diode.Thereby, implement the switching of conversion gain automatically according to the size of the input amplitude of preamplifier.
According to next invention, in the foregoing invention, in the gain commutation circuit, when the output level of above-mentioned preamplifier surpasses the 1st reference voltage, at first produce the 1st gate signal in specific bit-position, then, produce the 2nd gate signal in above-mentioned another specific bit-position with the gate signal production part.Its result, when the output level of above-mentioned preamplifier surpasses than big the 2nd reference voltage of above-mentioned the 1st reference voltage, time when surpassing above-mentioned the 2nd reference voltage, the 1st functional unit made above-mentioned the 1st switch element conducting in the generation time section of above-mentioned the 1st gate signal the time.In addition, when the output level of above-mentioned preamplifier surpasses than big the 3rd reference voltage of above-mentioned the 2nd reference voltage, time when surpassing above-mentioned the 3rd reference voltage is in the generation time section of above-mentioned the 2nd gate signal, and when making above-mentioned the 1st switch element conducting, the 2nd functional unit makes above-mentioned the 2nd switch element conducting.Thereby, can be in the switching that reliably implement conversion gain by the specific bit-position of the 1st gate signal regulation, can prevent reliably that the position, any position in burst signal from carrying out the switching of conversion gain.In addition, when having taken place to make the situation of the 2nd switch element conducting, because so that the 1st switch element work of prerequisite activity is condition, make the 2nd switch element conducting by the 2nd gate signal regulation specific bit-position, so not only can be set at suitable conversion gain, but also can prevent to be set at wrong conversion gain.
According to next invention, in the foregoing invention, the output of preamplifier is input to the 1st～the 3rd level sensitive circuit respectively.In the 1st level sensitive circuit, the output level of preamplifier surpass the 1st reference level during in during output pulse signal, the gate signal generative circuit generate respectively will begin from the trailing edge of the reset signal of outside input till the trailing edge of the output pulse signal of above-mentioned the 1st level sensitive circuit of the above-mentioned specific bit-position of correspondence during as the 1st gate signal of pulse duration and will begin from the trailing edge of above-mentioned the 1st gate signal till the trailing edge of the output pulse signal of the 1st level sensitive circuit of another specific bit-position of correspondence during as the 2nd gate signal of pulse duration.At the 2nd level sensitive circuit, the output level of preamplifier surpass 2nd reference voltage bigger than above-mentioned the 1st reference voltage during in during output pulse signal, when the 1st decision circuitry 1 is imported the output pulse signal of the 2nd level sensitive circuit in the pulse duration of above-mentioned the 1st gate signal, export the 1st and judge signal.Its result, the 1st holding circuit input before the above-mentioned reset signal during in keep the 1st to judge signal, the 1st switch element conducting work is in the conversion gain switching of being implemented preamplifier by the specific bit-position of the 1st gate signal regulation.In addition, in the 3rd level sensitive circuit, the output level of preamplifier surpass 3rd reference voltage bigger than above-mentioned the 2nd reference voltage during in during output pulse signal, when the 2nd decision circuitry is imported the output pulse signal of the 3rd level sensitive circuit in the pulse duration of above-mentioned the 2nd gate signal, export the 2nd and judge signal, the 2nd holding circuit before the above-mentioned reset signal of input during in keep the 2nd judgement signal.The 3rd decision circuitry keeps having exported the above-mentioned the 1st when judging signal in above-mentioned the 1st holding circuit, and above-mentioned the 2nd holding circuit keeps having exported the above-mentioned the 2nd when judging signal, according to the output of above-mentioned the 2nd holding circuit, makes the 2nd switch element conducting work.Its result switches to the new conversion gain of the 1st switch element and the 2nd switch element conducting simultaneously work in the specific bit-position by the 2nd gate signal regulation.
According to next invention, in the foregoing invention, the degree of the wave distortion that occurs in the output signal of preamplifier is considered in the setting of the 1st reference voltage, makes between itself and above-mentioned the 2nd reference voltage to have bigger voltage difference.Its result can prevent from frequently to carry out unnecessary conversion gain and switch.
According to next invention, in the foregoing invention, when the feedback resistance element of preamplifier also is connected in parallel to the series circuit of N (N 〉=3) resistive element and switch element respectively, the output of gain commutation circuit receiving preamplifier, then, taking place to make i (during the situation of the switch element conducting of series circuit of 3≤i≤N), switch element conducting work with all series circuits before above-mentioned i the series circuit is condition, makes the switch element conducting of above-mentioned i series circuit in corresponding specific bit-position.Its result, the further reliably switching of control change gain.
According to next invention, receive the series circuit that the feedback resistance element is connected in parallel to the 1st resistive element and the 1st switch element respectively, the series circuit of the 2nd resistive element and the 2nd switch element, amplification is the output current of the photo detector of the signal of telecommunication with the converting optical signals of pulse series shape, and the output of the preamplifier of output voltage signal, make above-mentioned the 1st switch element conducting in specific bit-position, then, when having taken place to make the situation conducting of above-mentioned the 2nd switch element, with above-mentioned the 1st switch element conducting work is condition, makes above-mentioned the 2nd switch element conducting in another specific bit-position.Thereby, can reliably implement the switching of conversion gain in the specific bit-position of burst signal, can prevent reliably that the position, any position in burst signal from carrying out the conversion gain switching.In addition, when having taken place to make the situation conducting of the 2nd switch element, because so that the 1st switch element work of prerequisite activity is condition, make the 2nd switch element conducting in specific bit-position by the 2nd gate signal regulation, so not only can be set at suitable conversion gain, but also can prevent to be set at wrong conversion gain.
According to next invention, in the foregoing invention, when the feedback resistance element of preamplifier also is connected with the series circuit of N (N 〉=3) resistive element and switch element respectively, the output of receiving preamplifier, then, taking place to make i (during the situation of the switch element conducting of series circuit of 3≤i≤N), switch element conducting work with all series circuits before above-mentioned i the series circuit is condition, makes the switch element conducting of above-mentioned i series circuit in corresponding specific bit-position.Thereby, the further reliably switching of control change gain.
As mentioned above, the used preamplifier of light receiver of the analyzer of the gain commutation circuit of preamplifier of the present invention and the method optical pickup apparatus that is applicable to optical communication system or light signal, monitor etc.
Claims (8)
1. the gain commutation circuit of a preamplifier, the converting optical signals that the conversion gain of switching preamplifier amplifier, described preamplifier amplify pulse series shape is the output current of the photo detector of the signal of telecommunication, and output voltage signal, its feedback resistance element is connected in parallel to the series circuit of the 1st resistive element and the generation of the 1st switch element and the series circuit of the 2nd resistive element and the generation of the 2nd switch element respectively, it is characterized in that: possess
When the output level of described preamplifier surpasses the 1st reference voltage, produce the 1st gate signal in described specific bit-position, then, produce the gate signal production part of the 2nd gate signal in described another specific bit-position;
When the output level of described preamplifier surpassed than big the 2nd reference voltage of described the 1st reference voltage, the timing when surpassing described the 2nd reference voltage made the 1st functional unit of described the 1st switch element conducting when the generation of described the 1st gate signal is regularly in the section;
When the output level of described preamplifier surpasses than big the 3rd reference voltage of described the 2nd reference voltage, timing when surpassing described the 3rd reference voltage is in the generation of described the 2nd gate signal regularly in the section, and, when making described the 1st switch element conducting, make the 2nd functional unit of described the 2nd switch element conducting.
2. the gain commutation circuit of preamplifier as claimed in claim 1 is characterized in that:
In the described preamplifier, be connected in parallel to the series circuit that the 3rd resistive element and diode produce with described feedback resistance element.
3. the gain commutation circuit of preamplifier as claimed in claim 1 is characterized in that:
The degree of the wave distortion that occurs in the output signal of described preamplifier is considered in the setting of described the 1st reference voltage, makes between itself and described the 2nd reference voltage to have bigger voltage difference.
4. the gain commutation circuit of preamplifier as claimed in claim 1 is characterized in that having:
The output level of described preamplifier surpass the 1st reference voltage during in the 1st level sensitive circuit of output pulse signal;
The output level of described preamplifier surpass 2nd reference voltage bigger than described the 1st reference voltage during in the 2nd level sensitive circuit of output pulse signal;
The output level of described preamplifier surpass 3rd reference voltage bigger than described the 2nd reference voltage during in the 3rd level sensitive circuit of output pulse signal;
Generate respectively will begin from the trailing edge of the reset signal of outside input till the trailing edge of the output pulse signal of described the 1st level sensitive circuit of the described specific bit-position of correspondence during as the 1st gate signal of pulse duration and will begin from the trailing edge of described the 1st gate signal till the trailing edge of the output pulse signal of described the 1st level sensitive circuit of described another specific bit-position of correspondence during as the gate signal generative circuit of the 2nd gate signal of pulse duration;
When in the pulse duration of described the 1st gate signal, importing the output pulse signal of described the 2nd level sensitive circuit, export the 1st decision circuitry of the 1st judgement signal;
Keep the described the 1st to judge signal in during before the described reset signal of input, make the 1st holding circuit of described the 1st switch element conducting work;
When in the pulse duration of described the 2nd gate signal, importing the output pulse signal of described the 3rd level sensitive circuit, export the 2nd decision circuitry of the 2nd judgement signal;
The 2nd holding circuit that keeps described the 2nd judgement signal in during before the described reset signal of input;
Described the 1st holding circuit keeps and exports the described the 1st when judging signal, and described the 2nd holding circuit keeps and exported the described the 2nd when judging signal, according to the output of described the 2nd holding circuit, makes the 3rd decision circuitry of described the 2nd switch element conducting work.
5. the gain commutation circuit of preamplifier as claimed in claim 4 is characterized in that:
The degree of the wave distortion that occurs in the output signal of described preamplifier is considered in the setting of described the 1st reference voltage, makes between itself and described the 2nd reference voltage to have bigger voltage difference.
The gain commutation circuit of 6 preamplifiers as claimed in claim 1 is characterized in that:
The feedback resistance element of described preamplifier also is connected in parallel to the series circuit of N (N 〉=3) resistive element and switch element generation respectively,
Described gain commutation circuit receives the output of described preamplifier, then, taking place to make i (during the situation of the switch element conducting of the series circuit of 3≤i≤N), switch element conducting work with all series circuits before described i the series circuit is condition, makes the switch element conducting of described i series circuit in corresponding specific bit-position.
7. the gain changing method of a preamplifier, be connected in parallel to the series circuit that series circuit that the 1st resistive element and the 1st switch element produce and the 2nd resistive element and the 2nd switch element produce with the feedback resistance element of the preamplifier that amplifies the output current of photo detector that converting optical signals with pulse series shape is the signal of telecommunication and output voltage signal, described the 1st switch element and described the 2nd switch element are ended or conducting, switch the conversion gain of described preamplifier, it is characterized in that having:
When the output level of described preamplifier surpasses the 1st reference voltage, produce the 1st gate signal in described specific bit-position, then, produce the operation of the 2nd gate signal in described another specific bit-position;
When the output level of described preamplifier surpassed than big the 2nd reference voltage of described the 1st reference voltage, the timing when surpassing described the 2nd reference voltage made the 1st operational sequence of described the 1st switch element conducting when the generation of described the 1st gate signal is regularly in the section;
When the output level of described preamplifier surpasses than big the 3rd reference voltage of described the 2nd reference voltage, timing when surpassing described the 3rd reference voltage is in the generation of described the 2nd gate signal regularly in the section, and, when making described the 1st switch element conducting, make the 2nd operational sequence of described the 2nd switch element conducting.
8. the gain changing method of preamplifier as claimed in claim 7 is characterized in that having:
When on the feedback resistance element of described preamplifier, also being connected in parallel to the series circuit of N (N 〉=3) resistive element and switch element generation respectively, receive the output of described preamplifier, then, taking place to make i (during the situation of the switch element conducting of the series circuit of 3≤i≤N), switch element conducting work with all series circuits before described i the series circuit is condition, makes the operation of the switch element conducting of described i series circuit in corresponding specific bit-position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031540732A CN100521517C (en) | 2003-08-15 | 2003-08-15 | Preamplifier gain switching circuit and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031540732A CN100521517C (en) | 2003-08-15 | 2003-08-15 | Preamplifier gain switching circuit and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1581680A CN1581680A (en) | 2005-02-16 |
| CN100521517C true CN100521517C (en) | 2009-07-29 |
Family
ID=34580131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031540732A Expired - Fee Related CN100521517C (en) | 2003-08-15 | 2003-08-15 | Preamplifier gain switching circuit and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100521517C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007028372A (en) * | 2005-07-20 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Light reception amplifier circuit and optical pickup device using the same |
| JP5272021B2 (en) * | 2009-01-19 | 2013-08-28 | 株式会社日立製作所 | Transimpedance amplifier and PON system |
| US10778170B2 (en) * | 2018-11-10 | 2020-09-15 | Semtech Corporation | Automatic gain control for passive optical network |
-
2003
- 2003-08-15 CN CNB031540732A patent/CN100521517C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1581680A (en) | 2005-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110492856B (en) | Transimpedance amplification unit circuit feedback circuit, photoelectric detection circuit and laser radar system | |
| US6246282B1 (en) | First stage amplifier circuit | |
| CN100546175C (en) | Receiving circuit and optical receiving circuit | |
| CN102771065B (en) | Optical signal turn-off detection circuit and optical receiver | |
| CN101563843B (en) | Optical receiver | |
| CN101243663B (en) | Light receiver and its identification threshold value generation method | |
| CN103460624A (en) | Optical signal detection circuit and optical receiver | |
| US10819425B2 (en) | Transimpedance amplifier for receiving burst optical signal | |
| US20070286611A1 (en) | Transimpedance (TIA) circuit usable for burst mode communications | |
| CN103477575A (en) | Detection device, light receiving device, detection method, and light receiving method | |
| US5589683A (en) | Optical receiver apparatus for quickly detecting loss of a composite optical signal input employing a loss-of-clock detector | |
| CN102820863A (en) | Dual-threshold automatic gain control circuit applied to class D audio frequency amplifiers | |
| EP1394938B1 (en) | System including a gain switching circuit and method of switching gain of pre-amplifier | |
| CN103262444A (en) | Optical line terminal | |
| GB1573695A (en) | Clock driven voltage comparator employing master-slave configuration | |
| EP0838914A2 (en) | Circuit arrangement for amplifying an electrical signal converted from an optical signal | |
| CN100521517C (en) | Preamplifier gain switching circuit and method | |
| JP5101131B2 (en) | Electronic circuit | |
| CN1820413B (en) | Circuit for varying gain of preamplifier | |
| US20100014607A1 (en) | Ad converter, data receiver and data reception method | |
| JP4597718B2 (en) | Burst optical receiver circuit | |
| US7626456B2 (en) | Overdrive control system | |
| US7349471B2 (en) | PPM receiving system and method using time-interleaved integrators | |
| WO2020225893A1 (en) | Transimpedance amplifier | |
| SU1532931A1 (en) | Device for checking information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090729 Termination date: 20170815 |