CN100521150C - Method for reducing sub-micron integrate circuit contact hole resistor - Google Patents

Method for reducing sub-micron integrate circuit contact hole resistor Download PDF

Info

Publication number
CN100521150C
CN100521150C CN 200710135506 CN200710135506A CN100521150C CN 100521150 C CN100521150 C CN 100521150C CN 200710135506 CN200710135506 CN 200710135506 CN 200710135506 A CN200710135506 A CN 200710135506A CN 100521150 C CN100521150 C CN 100521150C
Authority
CN
Grant status
Grant
Patent type
Prior art keywords
step
deposition
metal
method
power
Prior art date
Application number
CN 200710135506
Other languages
Chinese (zh)
Other versions
CN101159248A (en )
Inventor
允 刘
肖志强
赵文彬
陈海峰
Original Assignee
无锡中微晶园电子有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Abstract

本发明涉及集成电路的制造方法,具体地说是一种降低亚微米集成电路接触孔电阻的方法。 The present invention relates to a method of manufacturing integrated circuits, in particular to a method of sub-micron integrated circuit contact hole resistance is reduced. 按照本发明提供的技术方案,第一步,清洗,用二氧化硅腐蚀液(BOE)漂30-40秒,快速冲水8-10次,甩干,BOE腐蚀速率对热氧生长的二氧化硅约为85nm/min,35秒漂掉约为43-57nm;第二步,进行金属淀积;第三步,出片检查,送金属光刻工序。 According to the aspect of the present invention provides a first step, washed, with silica etching solution (BOE) bleaching 30-40 seconds, 8-10 fast flushing, drying dioxide, the BOE etching rate of thermally grown oxide silicon is about 85nm / min, 35 seconds rinsed off about 43-57nm; second step, metal deposition; a third step, a check sheet, a metal feeding photolithography process. 防止Al-Si直接接触造成的Al穿刺问题和硅析出问题,从而开发一种适合于大生产、低成本且成品率和可靠性达到规范要求的金属化工艺。 To prevent direct contact with Al-Si puncture problems caused by Al and Si deposition problems which developed which is suitable for mass production, at low cost and to achieve the yield and reliability of the metallization process specifications.

Description

降低亚微米集成电路接触孔电阻的方法 The method of reducing submicron IC contact hole resistance

技术领域 FIELD

本发明涉及集成电路的制造方法,具体地说是一种降低亚微米集成电路接触孔电阻的方法。 The present invention relates to a method of manufacturing integrated circuits, in particular to a method of sub-micron integrated circuit contact hole resistance is reduced. 背景技术 Background technique

随着微电子工业迅速发展,工艺制造技术快速进步,已经达到超大规模集 With the rapid development of the microelectronics industry, rapid technological advances in manufacturing technology, has reached a very large scale set

成电路(ULSI)阶段。 Circuits (ULSI) phase. 芯片尺寸增大,工作频率提高,这就要求提供更低的金属互连电阻,金属化(Metallization)成为一个极为重要的关键步骤。 Increasing the chip size, increase the operating frequency, which requires providing a lower metal interconnect resistance, metallization (Metallization) has become an extremely important key step. 在工艺制造中,金属用以连接(Interconnect)器件的源极(Source),漏极(Drain)和栅极(Gate)的接触孔(Contact)孔径縮小了许多,然而用以分开金属导线的介质层(Dielectric)厚度无法相对的减小,从而导致孔径和介质层的纵宽比(Aspect Ratio)增大,孔填充的工艺难度加大。 In the manufacturing process, the metal for connection (Interconnect) source device (the Source), a drain (Drain) and a gate (Gate) a contact hole (Business Card) many narrow aperture, but separate media for metal wire layer (the dielectric) the thickness can not be reduced relatively, resulting in vertical width than the aperture and the dielectric layer (Aspect ratio) is increased, the hole filling process more difficult. 表1为0.6~1.5um不同工艺的金属接触孔纵宽比。 Table 1 is 0.6 ~ 1.5um metal different process than the vertical width of the contact hole.

表l不同工艺种类的孔纵宽比 Table l different types of processes aperture aspect ratios

工艺类别 1.5um 1.2 um l.Oum 0,8 um 0.6 um Process Category 1.5um 1.2 um l.Oum 0,8 um 0.6 um

孔径 1.5 1.2 1.0 0.8 0.6 1.5 1.2 1.0 0.8 0.6 aperture

介质厚度 0.8 0.8 0.8 0.8 0.8 Medium thickness 0.8 0.8 0.8 0.8 0.8

孔纵宽比 0.53 0,67 0.8 1 1.33 Hole aspect ratios 1 1.33 0.53 0.67 0.8

目前,在0.6〜1.5um工艺中,金属填充孔的工艺总体有以下两种: Currently, in 0.6~1.5um process, the overall process of metal-filled pores in the following two:

1) Al-Si-Cu合金。 1) Al-Si-Cu alloy. 常规金属淀积工艺使用的是Al合金靶材(1。/。 Si、0.5% Cu), 孔接触电阻在50-100欧姆间。 Conventional metal deposition process using an Al alloy target (1. /. Si, 0.5% Cu), the contact resistance between the apertures 50-100 ohms. 由于Si与Cu在Al薄膜中的溶解度随温度而改变, 在热处理时,Si与Cu因冷却而析出。 Since the solubility of Si in Al and Cu in the film with temperature changes during the heat treatment, Si and Cu precipitated by cooling. 对接触窗口Al-Si-Cu金属膜,Si析出后可能在金属膜/硅衬底界面形成一层硅薄膜,其中掺有Al原子而呈p-type特性。 Contact window Al-Si-Cu metal film may be formed after the Si deposition layer of silicon thin metal film / silicon substrate interface, wherein the Al atoms were doped p-type characteristics. 如果硅衬底是n-type的形式就会形成一个pn接面。 If the silicon substrate is in the form of n-type will form a pn junction. 此现象在接触窗口愈小时愈明显。 This phenomenon is more evident in the contact window more hours. 同时Si晶粒(Nodule)(见图1)的存在也会导致Al薄膜电阻率增加以及抗反射层TiN (Anti-reflection Coating-TiN)的蚀刻问题,因此在使用TiN扩散阻挡层(Diffiision Barrier)后,Al合金薄膜中不再须要含Si。 Si grains exist (Nodule) (see FIG. 1) also results in increased resistivity of the Al film and the antireflection layer TiN (Anti-reflection Coating-TiN) etching problem, so TiN is used in the diffusion barrier layer (Diffiision Barrier) after, Al alloy thin film containing no longer necessary in Si. 至于Cu则可能与Al作用生成电阻率较高之Al2Cu (见图2)。 As for the Cu may be generated high resistivity Al2Cu (see FIG. 2) and the Al effect.

2) 孔Silicide工艺一金属硅化物 2) a pore Silicide metal silicide process

用于集成电路中的金属硅化物,要求与硅衬底附着力好,高电导率且具有很低的欧姆接触电阻,加温时稳定,表面平整,抗腐蚀性良好,抗氧化力强, 与二氧化硅附着性好但不发生反应,界面应力不大,工艺匹配,电迁移(Electromigmtion)不严重,可在较低温以固态反应形式生成。 A metal silicide in the integrated circuit, the silicon substrate requires good adhesion, high electrical conductivity and having a low ohmic contact resistance, stable heating, smooth surface, good corrosion resistance, strong oxidation, and good adhesion, but the silica does not react, little interfacial stress, the matching process, electromigration (Electromigmtion) is not serious, can be generated in a solid state reaction in the form of a relatively low temperature.

在金属接触应用上, 一般先在圆片上淀积一层金属薄膜,再经热处理生成具有一定能级、均匀而附着力好的金属硅化物。 The metal contact applications, generally by depositing a metal film on a wafer, and then heat-treated to generate a certain level, good adhesion and uniform metal silicide. 因为上层低阻A1或W等金属常与金属硅化物起作用,因此通常在低阻金属与金属硅化物之间,镀一层扩散 Because the upper layer such as a low-resistance metal, or W A1 functioning normally and a metal silicide, it is often low resistance between the metal and the metal silicide, a diffusion plate

3阻挡层(diffusion barrier)如Ti-W、 TiN等薄膜。 3 barrier layer (diffusion barrier), such as Ti-W, TiN film and the like. 其简要工艺流程如下表2。 2 which is a schematic process flow in the following table.

表2孔Silicide工艺流程 Table 2 hole Silicide Process

<table>table see original document page 4</column></row> <table>从上看出,采用第一种方法,需要增加一步N+孔光刻,接触孔电阻在50〜100 欧姆之间,随着孔径的縮小,极易发生硅析出和A1穿刺的情况,造成孔电阻增大或结漏电。 <Table> table see original document page 4 </ column> </ row> <table> from seen, the first method needs to be increased step N + bore photolithography, the contact hole between 50~100 ohmic resistance, with narrow pore size, and the case of silicon deposition A1 prone to puncture, resulting in an increase in resistance or junction leakage hole. 第二种方法工艺复杂。 The second method complex process. 去背面的目的是确保RTP时圆片有较好的热导性能,接触电阻受RTP工艺影响波动很大,产能较低,经历的工序太多, 不是一个很好的大生产工艺。 Purpose is to ensure that the back of the wafer RTP has good thermal conductivity properties, the contact resistance by the RTP process volatile impact, low production capacity, many experienced step, not a good large-scale production processes. 发明目的 Object of the invention

本发明的目的在于寻求一种降低亚微米集成电路接触孔电阻的方法,防止Al-Si直接接触造成的Al穿刺问题和硅析出问题,从而开发一种适合于大生产、 低成本且成品率和可靠性达到规范要求的金属化工艺。 Object of the present invention is to find a method of reducing the submicron IC contact hole resistance, to prevent direct contact with Al-Si puncture problems caused by Al and Si deposition problems which developed which is suitable for mass production, at low cost, and yield reliability to the metallization process specifications.

所述降低亚微米集成电路接触孔电阻的方法如下: The method of reducing submicron IC contact hole resistance is as follows:

第一步,清洗,用二氧化硅腐蚀液(BOE)漂30-40秒,快速冲水8-10次, 甩干,BOE腐蚀速率对热氧生长的二氧化硅约为85nm/min, 35秒漂掉约为43-57nm; The first step, clean, with silica etching solution (BOE) bleaching 30-40 seconds, 8-10 fast flushing, drying, the BOE etching rate of thermally grown silicon dioxide oxygen about 85nm / min, 35 second rinsed off about 43-57nm;

第二步,进行金属淀积 Second step, the metal deposited

a、 除气,温度:300±15°C,时间:55-65秒,目的:去除圆片中吸附的水 a, degassing, temperature: 300 ± 15 ° C, time: 55-65 seconds, Objective: to remove the water adsorbed wafer

汽; steam;

b、 Ti淀积,功率:2000W±5%,淀积膜层厚度为40±10%nm; b, Ti deposition, power: 2000W ± 5%, is deposited a film thickness of 40 ± 10% nm;

c、 101TiN淀积,功率:6500W±10%,淀积膜层厚度为60± 10%nm;d、 AL淀积,功率9000W土5X,温度:175±15°C;或者另外一种淀积方式:功率:2000W±5%,温度:400±15°C;淀积膜层厚度全为1000±5%nm; 第三步,出片检査,送金属光刻工序。 c, 101TiN deposition, power: 6500W ± 10%, a thickness of the deposition film layer 60 ± 10% nm; d, AL deposition, soil 9000W power 5X, temperature: 175 ± 15 ° C; deposition or another mode: power: 2000W ± 5%, temperature: 400 ± 15 ° C; depositing a film thickness of the whole of 1000 ± 5% nm; a third step, a check sheet, a metal feeding photolithography process.

本发明的优点是:1、能够获得高质量的阻挡层和低的欧姆接触电阻。 Advantage of the present invention are: 1, to obtain a high quality barrier layer and a low ohmic contact resistance. 随着孔尺寸的縮小和纵宽比的增大而特别有效。 Reduced with increasing pore size and aspect ratios of particularly effective. 2、能够避免由于孔接触电阻大而造 2, the hole can be avoided due to the large contact resistance made

成的成品率下降,提高电路的性能和成品率。 Yield decreased to improve the performance and yield of the circuits. 3、工艺简单,采用ENDURA— PVD三腔设备, 一次完成叠层金属淀积,适合于大生产,成本低且成品率和可靠性达到工艺规范要求。 3, simple process, using three-chamber ENDURA- PVD equipment, a complete stack of metal deposition, is suitable for large-scale production, low cost and yield and reliability of the process to achieve the specifications. 附图说明 BRIEF DESCRIPTION

图1是铝中硅析出的示意图。 1 is a schematic precipitated aluminum silicon.

图2是铝中铜析出的示意图。 FIG 2 is a schematic view of an aluminum deposited copper.

图3是金属叠层示意图。 FIG 3 is a schematic view of a metal laminate. 具体实施方式 detailed description

本发明所提供的工艺方案见图3所示。 The process embodiment of the present invention is provided as shown in Figure 3.

金属淀积工艺,第二步的各个工艺在ENDURA的3个腔体中一次完成,工艺完成后的纵向截面如图3所示。 Metal deposition process, a second step of the process is completed in each of the cavities 3 ENDURA, the longitudinal cross section of the process is completed as shown in FIG.

工艺设备:物理气相淀积台一ENDURA 膜层:Ti40-TiN60-AL1000(450nm) Process equipment: a physical vapor deposition station ENDURA layer: Ti40-TiN60-AL1000 (450nm)

所述降低亚微米集成电路接触孔电阻的方法如下: The method of reducing submicron IC contact hole resistance is as follows:

第一步,清洗,用二氧化硅腐蚀液(BOE)漂30-40秒,快速冲水8-10次, 甩干,BOE腐蚀速率对热氧生长的二氧化硅约为85nm/min, 35秒漂掉约为43-57nm; The first step, clean, with silica etching solution (BOE) bleaching 30-40 seconds, 8-10 fast flushing, drying, the BOE etching rate of thermally grown silicon dioxide oxygen about 85nm / min, 35 second rinsed off about 43-57nm;

第二步,进行金属淀积 Second step, the metal deposited

a、 除气,温度:300士15。 a, degassing, temperature: 300 ± 15. C,时间:55-65秒,目的:去除圆片中吸附的水 C, Time: 55-65 seconds, Objective: to remove the water adsorbed wafer

汽; steam;

b、 Ti淀积,功率:2000W±5%,淀积膜层厚度为40土100/^nm; b, Ti deposition, power: 2000W ± 5%, is deposited a film thickness of 40 Soil 100 / ^ nm;

c、 101TiN淀积,功率:6500W±10%,淀积膜层厚度为60± 10%nm; c, 101TiN deposition, power: 6500W ± 10%, a thickness of the deposition film layer 60 ± 10 nm%;

d、 AL淀积,功率9000W土5X,温度:175士15。 d, AL deposition, soil 9000W power 5X, temperature: 175 ± 15. C;或者另外一种淀积方式:功率:2000W士5X,温度:400土15。 C; deposition, or another way: POWER: 2000W disabilities 5X, temperature: 400 Soil 15. C;淀积膜层厚度全为1000±5%nm; C; depositing a film thickness of the whole of 1000 ± 5% nm;

第三步,出片检查,送金属光刻工序。 The third step, a check sheet, a metal feeding photolithography process.

本发明的工艺方案设计理由是:Ti/TiN的作用是获得高质量的阻挡层和低的欧姆接触电阻。 Process scheme of the present invention is designed on the grounds that: the role of Ti / TiN is to obtain a high quality barrier layer and a low ohmic contact resistance. 首先淀积40nm的Ti层, 一方面Ti与源漏直接接触,Ti较易穿透硅表面的自然氧化层,保证在合金时能形成良好的欧姆接触,且Ti与Si 只有在高温下(60(TC以上)会形成C49或C54相位的TiSi2,而对于我们现有工艺,后端工艺(Back End Of Line)没有高温出现,因此Ti不会消耗源漏结中的Si,不会造成漏电。另一方面Ti和Al不能直接接触,因为Ti与Al在40(TC 左右时会形成金属合金,而Si在Ti、 Al金属合金中的固溶度会大大提高(资料表明合金中Ah Ti: Si比例是5: 7: 12), Al靶中的Si根本无法满足金属合金的需求,导致源漏结中大量的Si被消耗,从而造成漏电。 40nm of Ti layer is first deposited, on the one hand in direct contact with the source and drain Ti, Ti easily penetrate the surface of the natural oxide layer of silicon, to ensure that when the alloy can form a good ohmic contact with Ti and Si only at a high temperature (60 (TC above) formation of the TiSi2 phase C49 or C54, and for our existing processes, back-end processing (Back End of Line) temperature does not occur, and therefore is not consumed Ti source drain junctions of Si, not cause leakage. on the other hand can not directly contact with Ti and Al, Ti and Al as in 40 (formed when the metal alloy is about TC, while in the Si Ti, Al solid solution of the metal alloy would be greatly enhanced (data indicate that the alloy Ah Ti: Si ratio is 5: 7: 12), Al in the Si target can not meet the needs of the metal alloy, the source and drain junctions resulting in large amount of Si is consumed, resulting in leakage.

5其次淀积101 TiN 60nrn作为Ti和Al的阻挡层,可避免Ti和Al在后端工艺的热过程时形成合金,源漏结中的Si就不会向金属扩散,金属也不能扩散到源漏结中形成穿剌(Spiking)。 Then 5 101 TiN 60nrn deposited as a barrier layer of Ti and Al, Ti and Al can be avoided during the thermal process of forming an alloy of the back-end process, source and drain junctions Si does not diffuse into the metal, the metal can not be diffused into the source drain junction formed puncture (Spiking).

最后淀积lOOOnm厚的Al膜,若是多层金属工艺,此膜厚可以根据需要随时调节。 Finally lOOOnm deposited Al film thickness, if the multi-layer metal process, the film thickness can be adjusted as needed at any time.

本发明适用于0.6~1.5um双极和CMOS工艺的接触孔金属淀积工艺模块, 使常规工艺的孔接触电阻由50~100欧姆降低到1~5欧姆,并且减少了一次N+ 孔光刻。 The present invention is applicable to bipolar and CMOS 0.6 ~ 1.5um process module the contact hole metal deposition process, the conventional process so that apertures 50 to reduce the contact resistance of 100 ohms to 1 to 5 ohms and a reduced aperture N + photolithography. 本发明可以有效地降低了孔接触电阻,同时有效解决A1-Si直接接触造成的A1钉(Spiking)问题和硅析出问题。 The present invention can effectively reduce the contact resistance of the hole, while effectively solving A1-Si caused by direct contact with A1 staples (on Spiking) silicon deposition problem and problems.

本发明从2005年起开始应用于中电科技集团第五十八研究所工艺线(无锡中微晶园电子有限公司)中。 The present invention since 2005 began to be used in Electronics Technology Group Institute for the fifty-eighth process line (microcrystalline Park in Wuxi Electronics Co., Ltd.) in. 使用在0.6um-1.5um约16种工艺流程中,到目前约流片近10万片,N+孔/P+孔/Poly孔的接触电阻由原先的5(M00欧姆降低到1-5欧姆,没有出现因为孔接触电阻大而造成的圆片报废,彻底解决了长期困扰工艺线多年的孔接触电阻大的问题,提高了电路的品质并为公司创造了较大的收益。 Used about 16 kinds of 0.6um-1.5um process flow sheet to the current flow nearly about 100,000, the contact hole resistance N + / P + hole / Poly well from the original 5 (M00 ohms ohms down to 1-5, no because the discs appear large hole caused by the contact resistance scrapped completely solve the big problems of long-term process line for many years via contact resistance problems and improve the quality of the circuit and for the company to create a larger income.

6 6

Claims (1)

  1. 1、降低亚微米集成电路接触孔电阻的方法,其特征在于,第一步,清洗,用二氧化硅腐蚀液BOE漂30-40秒,快速冲水8-10次,甩干,二氧化硅腐蚀液BOE腐蚀速率对热氧生长的二氧化硅约为85nm/min,漂掉约为43-57nm;第二步,进行金属淀积;a、除气,温度:300±15℃,时间:55-65秒,目的:去除圆片中吸附的水汽;b、Ti淀积,功率:2000W±5%,淀积膜层厚度为40±10%nm;c、101TiN淀积,功率:6500W±10%,淀积膜层厚度为60±10%nm;d、AL淀积,功率9000W±5%,温度:175±15℃;或者另外一种淀积方式:功率:2000W±5%,温度:400±15℃;淀积膜层厚度全为1000±5%nm;第三步,出片检查,送金属光刻工序。 1, a method to reduce the contact hole submicron IC resistance, wherein the first step, washing, rinsing the silica with an etching solution BOE 30-40 seconds, 8-10 fast flushing, drying, silica BOE etching solution etching rate of silicon dioxide thermally grown oxide is about 85nm / min, rinsed off about 43-57nm; second step, the metal deposition; a, degassing, temperature: 300 ± 15 ℃, time: 55-65 seconds, Objective: to remove moisture adsorbed wafer; b, Ti deposition, power: 2000W ± 5%, is deposited a film thickness of 40 ± 10% nm; c, 101TiN deposition, power: 6500W ± 10%, is deposited a film thickness of 60 ± 10% nm; d, AL deposition power 9000W ± 5%, temperature: 175 ± 15 ℃; or depositing another way: power: 2000W ± 5%, temperature : 400 ± 15 ℃; 1000 ± 5% nm is deposited full film thickness; the third step, a check sheet, a metal feeding photolithography process.
CN 200710135506 2007-11-16 2007-11-16 Method for reducing sub-micron integrate circuit contact hole resistor CN100521150C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 200710135506 CN100521150C (en) 2007-11-16 2007-11-16 Method for reducing sub-micron integrate circuit contact hole resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 200710135506 CN100521150C (en) 2007-11-16 2007-11-16 Method for reducing sub-micron integrate circuit contact hole resistor

Publications (2)

Publication Number Publication Date
CN101159248A true CN101159248A (en) 2008-04-09
CN100521150C true CN100521150C (en) 2009-07-29

Family

ID=39307266

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 200710135506 CN100521150C (en) 2007-11-16 2007-11-16 Method for reducing sub-micron integrate circuit contact hole resistor

Country Status (1)

Country Link
CN (1) CN100521150C (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102085522B (en) 2009-12-04 2014-05-14 中芯国际集成电路制造(上海)有限公司 Method for cleaning pipeline sprayed with silicon-containing bottom anti-reflection coating
CN102479744B (en) * 2010-11-25 2014-02-26 上海华虹宏力半导体制造有限公司 Aluminum pore-filling connection process
CN104465442B (en) * 2014-11-28 2017-05-24 厦门讯扬电子科技有限公司 Semiconductor processing method for real-time monitoring of the Al-Si surface

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604155A (en) 1995-07-17 1997-02-18 Winbond Electronics Corp. Al-based contact formation process using Ti glue layer to prevent nodule-induced bridging
CN1304552A (en) 1999-03-15 2001-07-18 皇家菲利浦电子有限公司 Methods for reducing semiconductor contact resistance
CN1426092A (en) 2003-01-02 2003-06-25 上海华虹(集团)有限公司 Damascene process for chemically vapor depositing titanium nitride and copper metal layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5604155A (en) 1995-07-17 1997-02-18 Winbond Electronics Corp. Al-based contact formation process using Ti glue layer to prevent nodule-induced bridging
CN1304552A (en) 1999-03-15 2001-07-18 皇家菲利浦电子有限公司 Methods for reducing semiconductor contact resistance
CN1426092A (en) 2003-01-02 2003-06-25 上海华虹(集团)有限公司 Damascene process for chemically vapor depositing titanium nitride and copper metal layer

Also Published As

Publication number Publication date Type
CN101159248A (en) 2008-04-09 application

Similar Documents

Publication Publication Date Title
Murarka et al. Copper metallization for ULSL and beyond
Crowder et al. 1 µm MOSFET VLSI technology: Part VII—Metal silicide interconnection technology—A future perspective
US6221763B1 (en) Method of forming a metal seed layer for subsequent plating
US5939788A (en) Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper
US5760475A (en) Refractory metal-titanium nitride conductive structures
US5217923A (en) Method of fabricating a semiconductor device having silicided source/drain regions
Kim et al. Cu wettability and diffusion barrier property of Ru thin film for Cu metallization
US6291082B1 (en) Method of electroless ag layer formation for cu interconnects
US6180469B1 (en) Low resistance salicide technology with reduced silicon consumption
US6426289B1 (en) Method of fabricating a barrier layer associated with a conductor layer in damascene structures
US5721175A (en) Method of manufacturing a semiconductor device
US6521515B1 (en) Deeply doped source/drains for reduction of silicide/silicon interface roughness
US5801444A (en) Multilevel electronic structures containing copper layer and copper-semiconductor layers
US6583052B2 (en) Method of fabricating a semiconductor device having reduced contact resistance
US6506668B1 (en) Utilization of annealing enhanced or repaired seed layer to improve copper interconnect reliability
US6147000A (en) Method for forming low dielectric passivation of copper interconnects
US5882738A (en) Apparatus and method to improve electromigration performance by use of amorphous barrier layer
US6274923B1 (en) Semiconductor device and method for making the same
US20050272235A1 (en) Method of forming silicided gate structure
US5858873A (en) Integrated circuit having amorphous silicide layer in contacts and vias and method of manufacture thereof
US6369429B1 (en) Low resistance composite contact structure utilizing a reaction barrier layer under a metal layer
US6218302B1 (en) Method for forming a semiconductor device
US20050170642A1 (en) Methods for improving metal-to-metal contact in a via, devices made according to the methods, and systems including the same
US6060387A (en) Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions
US20140287577A1 (en) Methods for producing interconnects in semiconductor devices

Legal Events

Date Code Title Description
C06 Publication
C10 Entry into substantive examination
C14 Grant of patent or utility model
C41 Transfer of patent application or patent right or utility model