CN101159248A - Method for reducing sub-micron integrate circuit contact hole resistor - Google Patents

Abstract

The invention relates to a manufacturing method of an integrated circuit, specifically to a method for reducing contact-hole resistance of a sub-micron integrated circuit. According to the technical proposal provided in the invention, the method comprises: (1) bleaching with silicon dioxide buffered oxide etch (BOE) solution for 30-40 sec, rapidly flushing with water for 8-10 times, and drying, wherein the BOE corrosion rate in terms of hot-oxygen grown silicon dioxide is 85 nm/min, and around 43-57 nm silicon dioxide is bleached out in 35 sec; (2) performing metal deposition; and (3) outputting a chip, detecting, and transporting to metal photoetching process. The inventive method prevents aluminum penetration problem and silicon precipitation problem due to direct contact of aluminum and silicon, so as to develop a metallization technique with suitability to large-scale production, low cost, and fulfillment of finished product rate and reliability to standard requirements.

Description

Reduce the method for sub-micron integrate circuit contact hole resistor

Technical field

The present invention relates to the manufacture method of integrated circuit, specifically a kind of method that reduces sub-micron integrate circuit contact hole resistor.

Background technology

Along with microelectronics industry develops rapidly, process manufacturing technology is progressive fast, has reached very lagre scale integrated circuit (VLSIC) (ULSI) stage.Chip size increases, and operating frequency improves, and this just requires the metal interconnected resistance that provides lower, and metallization (Metallization) becomes a very important committed step.In technology is made, metal is in order to connect the source electrode (Source) of (Interconnect) device, contact hole (Contact) aperture of drain electrode (Drain) and grid (Gate) has dwindled many, yet in order to reducing that separately dielectric layer (Dielectric) thickness of plain conductor can't be relative, thereby cause the vertical wide of aperture and dielectric layer to increase than (AspectRatio), the technology difficulty that fill in the hole strengthens.Table 1 is the vertical wide ratio of the metal contact hole of 0.6～1.5um different process.

Wide ratio is indulged in the hole of table 1 different process kind

Technology category	1.5um	1.2um	1.0um	0.8um	0.6um
						The aperture	1.5	1.2	1.0	0.8	0.6
Dielectric thickness	0.8	0.8	0.8	0.8	0.8
						Wide ratio is indulged in the hole	0.53	0.67	0.8	1	1.33

At present, in 0.6～1.5um technology, the technology in metal filled hole totally has following two kinds:

1) Al-Si-Cu alloy.That the common metal depositing technics uses is Al alloy target material (1%Si, 0.5%Cu), and the hole contact resistance is between 50-100 ohm.Solubility with temperature in the Al film changes owing to Si and Cu, and when heat treatment, Si and Cu separate out because of cooling.To contact window Al-Si-Cu metal film, after separating out, Si may form one deck silicon thin film at metal film/silicon substrate interface, and wherein be mixed with the Al atom and be the p-type characteristic.Will form a p-n and connect face if silicon substrate is the form of n-type.This phenomenon at contact window more hour more obviously.The existence of Si crystal grain (Nodule) (see figure 1) simultaneously also can cause the etch issues of increase of Al film resiativity and anti-reflecting layer TiN (Anti-reflection Coating-TiN), therefore after using TiN diffusion impervious layer (Diffusion Barrier), no longer need contain Si in the Al alloy firm.Then may generate the higher Al of resistivity as for Cu with the Al effect ₂The Cu (see figure 2).

2) hole Silicide technology-metal silicide

The metal silicide that is used for integrated circuit, it is good to require with silicon substrate adhesive force, and high conductivity and have very low ohmic contact resistance is stable when heating, surfacing, corrosion resistance is good, and resistance to oxidation is strong, and is good but do not react with the silicon dioxide tack, interfacial stress is little, the technology coupling, (Electromigration) is not serious in electromigration, can generate with the solid-state reaction form at lower temperature.

On Metal Contact was used, general deposit layer of metal film on disk earlier generated through heat treatment and has certain energy level, evenly and the good metal silicide of adhesive force.Work with metal silicide because metals such as upper strata low-resistance Al or W are normal, therefore usually between low resistance metal and metal silicide, plate one deck diffusion impervious layer (diffusion barrier) as films such as Ti-W, TiN.Its concise and to the point technological process such as following table 2.

The Silicide technological process of table 2 hole

1.	Operation
			2.	Remove backsizing	Gluing
Check
	3.	Go to the back side			Hot post bake
Float SiO2
			4.	Wet method is removed photoresist	Wet method is removed photoresist
Check
	5.	The metal Ti deposit			2%HF floats 120sec
Ti sputter 70nm
			6.	RTP1	740C N2 30sec
7.	Selective corrosion APM 5min, 50C+DI+S.D
			8.	RTP2	850C N2 30sec
9.	Metal laminated deposit Ti/TiN/AlSiCu/Ti/TiN	Ti sputter 40nm
			TiN sputter 60nm
		Temperature aluminium deposit 450nm
			TI deposit 20nm
		TiN deposit 60nm

From finding out, adopt first method, need to increase step N+ hole photoetching, silicon along with dwindling of aperture, very easily takes place and separates out situation about puncturing with Al between 50～100 ohm in contact hole resistance, causes hole resistance to increase or junction leakage.The second method complex process.The purpose of going to the back side is that disk has thermal conductivity preferably when guaranteeing RTP, and contact resistance is subjected to the fluctuation of RTP technogenic influence very big, and production capacity is lower, and the operation of experience is too many, is not a well big production technology.

Goal of the invention

The objective of the invention is to seek a kind of method that reduces sub-micron integrate circuit contact hole resistor, prevent Al-Si directly the Al puncture problem and the silicon that cause of contact separate out problem, thereby develop a kind of metallization process that big production, low cost and rate of finished products and reliability reach code requirement that is suitable for.

The method of described reduction sub-micron integrate circuit contact hole resistor is as follows:

The first step is cleaned, and (BOE) floats 30-40 second with silicon dioxide etching liquid, wash by water 8-10 time fast, and drying, the BOE corrosion rate is about 85nm/min to the silicon dioxide of hot oxide growth, floats in 35 seconds to fall to be about 43-57nm;

In second step, carry out the metal deposit

A, degasification, temperature: 300 ± 15 ℃, the time: 55-65 second, purpose: remove the steam that adsorbs in the disk;

B, Ti deposit, power: 2000W ± 5%, deposition membrane thickness are 40 ± 10%nm;

C, 101TiN deposit, power: 6500W ± 10%, deposition membrane thickness are 60 ± 10%nm;

D, AL deposit, power 9000W ± 5%, temperature: 175 ± 15 ℃; Perhaps another deposit mode: power: 2000W ± 5%, temperature: 400 ± 15 ℃; Deposition membrane thickness is 1000 ± 5%nm entirely;

In the 3rd step, the metal lithographic operation is sent in the slice inspection.

Advantage of the present invention is: 1, can obtain high-quality barrier layer and low ohmic contact resistance.Along with dwindling and the increase of vertical wide ratio and effective especially of hole dimension.2, can avoid the decrease in yield that causes greatly owing to the hole contact resistance, improve the performance and the rate of finished products of circuit.3, technology is simple, adopts ENDURA-PVD three chamber equipment, once finishes the lamination metal deposit, is suitable for big production, and low and rate of finished products of cost and reliability reach process specification requirements.

Description of drawings

Fig. 1 is the schematic diagram that silicon is separated out in the aluminium.

Fig. 2 is the schematic diagram that copper is separated out in the aluminium.

Fig. 3 is metal laminated schematic diagram.

Embodiment

Process program provided by the present invention is seen shown in Figure 3.

The metal depositing technics, each technology in second step is once finished in 3 cavitys of ENDURA, and the longitudinal cross-section after technology is finished is as shown in Figure 3.

Process equipment: physical vapor deposition platform-ENDURA

Rete: Ti40-TiN60-AL1000 (450nm)

The method of described reduction sub-micron integrate circuit contact hole resistor is as follows:

The first step is cleaned, and (BOE) floats 30-40 second with silicon dioxide etching liquid, wash by water 8-10 time fast, and drying, the BOE corrosion rate is about 85nm/min to the silicon dioxide of hot oxide growth, floats in 35 seconds to fall to be about 43-57nm;

In second step, carry out the metal deposit

A, degasification, temperature: 300 ± 15 ℃, the time: 55-65 second, purpose: remove the steam that adsorbs in the disk;

B, Ti deposit, power: 2000W ± 5%, deposition membrane thickness are 40 ± 10%nm;

C, 101TiN deposit, power: 6500W ± 10%, deposition membrane thickness are 60 ± 10%nm;

D, AL deposit, power 9000W ± 5%, temperature: 175 ± 15 ℃; Perhaps another deposit mode: power: 2000W ± 5%, temperature: 400 ± 15 ℃; Deposition membrane thickness is 1000 ± 5%nm entirely;

In the 3rd step, the metal lithographic operation is sent in the slice inspection.

Process program design reason of the present invention is: the effect of Ti/TiN is to obtain high-quality barrier layer and low ohmic contact resistance.The Ti layer of deposit 40nm at first, Ti leaks with the source and directly contacts on the one hand, Ti more easily penetrates the natural oxidizing layer of silicon face, guarantee can form good Ohmic contact when alloy, and Ti and Si has only at high temperature (more than 600 ℃) can form the TiSi of C49 or C54 phase place ₂, and for our existing technology, backend process (Back End Of Line) does not have high temperature to occur, so Ti can not consume the Si in the source-and-drain junction, can not cause electric leakage.Ti can not directly contact with Al on the other hand, because Ti and Al can form metal alloy when 400 ℃ of left and right sides, and the solid solubility of Si in Ti, Al metal alloy can improve (data shows Al in the alloy: Ti: the Si ratio is 5: 7: 12) greatly, Si in the Al target can't satisfy the demand of metal alloy at all, cause Si a large amount of in the source-and-drain junction to be consumed, thereby cause electric leakage.

Secondly deposit 101 TiN 60nm can avoid Ti and Al to form alloy when the thermal process of backend process as the barrier layer of Ti and Al, and the Si in the source-and-drain junction just can not be to metal diffusing, and metal can not be diffused into and form puncture (Spiking) in the source-and-drain junction.

The last thick Al film of deposit 1000nm, if multiple layer metal technology, this thickness can be regulated as required at any time.

The present invention is applicable to the contact hole metal depositing technics module of the bipolar and CMOS technology of 0.6～1.5um, makes the hole contact resistance of common process be reduced to 1～5 ohm by 50～100 ohm, and has reduced by a N+ hole photoetching.The present invention can reduce the hole contact resistance effectively, effectively solves direct Al nail (Spiking) problem and the silicon that cause of contacting of Al-Si simultaneously and separates out problem.

The present invention was applied in group of ZhongDian Science ﹠ Technology the 58 research institute's processing line (Wuxi Zhongwei Microchips Co., Ltd.) since 2005.Use is in the about 16 kinds of technological processes of 0.6um-1.5um, nearly 100,000 of about up till now flow, the contact resistance in N+ hole/P+ hole/Poly hole is reduced to 1-5 ohm by original 50～100 ohm, the disk that does not have to occur causing because the hole contact resistance is big is scrapped, thoroughly solved the long-term puzzlement processing line big problem of hole contact resistance for many years, improved the quality of circuit and also created bigger income for company.

Claims (1)

1. reduce the method for sub-micron integrate circuit contact hole resistor, it is characterized in that,

The first step is cleaned, and (BOE) floats 30-40 second with silicon dioxide etching liquid, wash by water 8-10 time fast, and drying, the BOE corrosion rate is about 85nm/min to the silicon dioxide of hot oxide growth, floats in 35 seconds to fall to be about 43-57nm;

In second step, carry out the metal deposit

A, degasification, temperature: 300 ± 15 ℃, the time: 55-65 second, purpose: remove the steam that adsorbs in the disk;

B, Ti deposit, power: 2000W ± 5%, deposition membrane thickness are 40 ± 10%nm;

C, 101TiN deposit, power: 6500W ± 10%, deposition membrane thickness are 60 ± 10%nm;

D, AL deposit, power 9000W ± 5%, temperature: 175 ± 15 ℃; Perhaps another deposit mode: power: 2000W ± 5%, temperature: 400 ± 15 ℃; Deposition membrane thickness is 1000 ± 5%nm entirely;

In the 3rd step, the metal lithographic operation is sent in the slice inspection.