CN100517643C - Method for manufacturing inlaid structure - Google Patents
Method for manufacturing inlaid structure Download PDFInfo
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- CN100517643C CN100517643C CNB2006101478035A CN200610147803A CN100517643C CN 100517643 C CN100517643 C CN 100517643C CN B2006101478035 A CNB2006101478035 A CN B2006101478035A CN 200610147803 A CN200610147803 A CN 200610147803A CN 100517643 C CN100517643 C CN 100517643C
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Abstract
The invention relates to a manufacturing method of a mosaic structure. The method comprises the following steps: a semiconductor substrate with a metal conducting wire layer is provided; a dielectric layer is formed on the semiconductor substrate, an opening is formed in the dielectric layer, and the bottom part of the openingis exposed outside the surface of the metal conducting wire layer; first metal layers are deposited at the bottom part and on the side wall of the opening; the first metal layer at the bottom part of the opening is removed, and the oxide on the surface of the metal conducting wire layer at the bottom part of the opening is removed; second metal layers are deposited at the bottom part and on the side wall of the opening; third metal layers are deposited on the second metal layers. The method can eliminate the coupling current which is generated by the plasma in the metal conducting wire layer, and reduce or eliminate the damage to the gate oxide.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of mosaic texture.
Background technology
Along with reducing day by day of semiconductor technology live width, industry selects for use copper to replace the interconnection material of aluminium as back segment, select for use advanced low-k materials as insulating material accordingly, because copper is difficult to etching and very easily diffusion, industry is introduced mosaic technology, overcome the shortcoming that is difficult to etching, and the introducing barrier layer stops the diffusion of copper in advanced low-k materials.Number of patent application is that 02106882.8 Chinese patent discloses a kind of mosaic technology, and Fig. 1 to Fig. 4 is the manufacture method generalized section of described disclosed mosaic technology.
As shown in Figure 1, provide a substrate 100 with metal carbonyl conducting layer, described metal carbonyl conducting layer material is a copper.Form first dielectric layer 102 in described substrate 100, the method for its formation is plasma enhanced chemical vapor deposition (PECVD), and thickness is 30 to 100nm.Form second dielectric layer 104 on described first dielectric layer 102, described second dielectric layer 104 is an advanced low-k materials.Form an anti-reflecting layer 106 on described second dielectric layer 104, described anti-reflecting layer 106 can be the organic or inorganic material.On described anti-reflecting layer 106, form a photoresist layer 108, form connecting hole patterns of openings 110 by exposure imaging.
As shown in Figure 2, serve as the cover curtain with described photoresist layer 108, by etching described connecting hole patterns of openings 110 is transferred to and formed connecting hole 110a in described second dielectric layer 104, described connecting hole 110a exposes described first dielectric layer 102 surfaces in the bottom.
As shown in Figure 3, remove described photoresist layer 108 and anti-reflecting layer 106 by ashing and wet-cleaned.
Spin coating photoresist and form channel patterns on described connecting hole 110a neutralizes second dielectric layer 104 is transferred to described channel patterns in described second dielectric layer 104 by etching then, forms groove 112 as shown in Figure 4.As shown in Figure 5, remove first dielectric layer 102 of described connecting hole 110a bottom by etching.And remove the described photoresist that is formed with channel patterns.
In described groove 112 and connecting hole 110a the filled conductive material for example copper promptly form copper enchasing structure.
In described groove 112 and connecting hole 110a, fill before the conductor material, generally need remove the oxide of the plain conductor laminar surface of described connecting hole 110a bottom with Ar or other inert gas plasma, to reduce contact resistance, for example TaN and Ta stop the diffusion of copper in second dielectric layer 104 of subsequent deposition to the deposited barrier layer material then, fill the copper metal at last on described barrier layer, and fill up whole connecting hole 110a and groove 112.Though the step of the oxide layer of the plain conductor laminar surface of above-mentioned removal connecting hole 110a bottom is carried out in being electroneutral plasma environment, yet the zone that plasma still has positive charge or negative electrical charge to assemble in local environment, the positive charge of described gathering or negative electrical charge can be coupling in the described metal carbonyl conducting layer in removing described oxide layer process and form electric current, described electric current to grid, can cause the grid oxygen of gate bottom breakdown along the plain conductor of lower floor.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of mosaic texture, in the lower metal conductor layer, to form the problem of couple current in the manufacture method that solves existing mosaic texture.
For achieving the above object, the manufacture method of a kind of mosaic texture provided by the invention comprises: the semiconductor-based end with metal carbonyl conducting layer is provided; Form dielectric layer on the described semiconductor-based end, and form opening in described dielectric layer, described open bottom is exposed described plain conductor laminar surface; At described open bottom and side wall deposition the first metal layer; Remove the oxide of the plain conductor laminar surface of the first metal layer of described open bottom and described open bottom; At described open bottom and side wall deposition second metal level; Deposition the 3rd metal level on described second metal level.
Described dielectric layer is a kind of or its combination in silica, silicon nitride, carborundum, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, the black diamond.
The step that forms opening in described dielectric layer is as follows: spin coating photoresist layer on described dielectric layer, and graphically form patterns of openings; By etching described patterns of openings is shifted down in the described dielectric layer, form opening; Remove described photoresist layer.
The described the first metal layer and second metal level are a kind of or combination in tantalum, the tantalum nitride.
The deposition process of the described the first metal layer and second metal level is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), ald, the electrochemical deposition.
The method of oxide of removing the plain conductor laminar surface of the first metal layer of described open bottom and described open bottom is a dry plasma.
On described second metal level method of deposition the 3rd metal level for electroplate, a kind of in the chemical vapour deposition (CVD).
Described the 3rd metal level is a copper.
The present invention also improves a kind of manufacture method of mosaic texture, comprise: the semiconductor-based end with metal carbonyl conducting layer is provided, on the described semiconductor-based end, the formation dielectric layer is arranged, and in described dielectric layer, be formed with the opening that described plain conductor laminar surface is exposed in the bottom; At described open bottom and side wall deposition the first metal layer; Remove the oxide of the plain conductor laminar surface of the first metal layer of described open bottom and described open bottom; At described open bottom and side wall deposition second metal level; Deposition the 3rd metal level on described second metal level.
Described plasma is an argon plasma.
Accordingly, the present invention also provides a kind of semiconductor device, comprising: the semiconductor-based end; The described semiconductor-based end, have metal carbonyl conducting layer; Be formed at the suprabasil dielectric layer of described semiconductor; Have opening in described dielectric layer, described plain conductor laminar surface is exposed in the bottom of described opening; It is characterized in that: described dielectric layer, described opening sidewalls and bottom are coated with metal level, and described metal level is used for spreading the gathering electric charge of described plasma etching gas when plasma etching.
Described metal level is a kind of or combination in tantalum, the tantalum nitride.
Compared with prior art, the present invention has the following advantages:
In the manufacturing process of mosaic texture of the present invention, at first be formed with dielectric layer surface and the described open bottom and the side wall deposition the first metal layer of opening, make whole semiconductor-based basal surface have conductivity, in remove the metal carbonyl conducting layer oxide on surface process of described open bottom with plasma bombardment, gathering electric charge local in the plasma environment can be discharged into other zone by the first metal layer of this conduction, and with the gathering charging neutrality of opposite polarity, thereby make whole plasma environment be in electric neutrality as far as possible, reduce or eliminated the coupling phenomenon of local gathering electric charge in described metal carbonyl conducting layer, thereby eliminated the destruction of couple current grid oxygen;
Because the first metal layer of metal material at first is deposited on described dielectric layer surface and described open bottom and sidewall, stopped of the bombardment of described argon plasma to described dielectric layer, reduced damage and failure to described dielectric layer, help improving or keeping the puncture voltage of described dielectric layer, improve the stability of the device that generates;
In the prior art, in dielectric layer, behind the formation opening, at first carry out the argon plasma bombardment, then bombard with hydrogen gas plasma, and then deposition of tantalum and tantalum nitride and metallic copper, the inventive method has been saved the hydrogen gas plasma implant steps, save processing step, reduced cost.
Description of drawings
Fig. 1 to Fig. 5 is the generalized section of each step corresponding structure of manufacture method of existing a kind of mosaic texture;
Fig. 6 is the flow chart of first embodiment of the manufacture method of mosaic texture of the present invention;
Fig. 7 to Figure 17 is the generalized section of each step corresponding structure of first embodiment of the manufacture method of mosaic texture of the present invention;
Figure 18 is the flow chart of second embodiment of the manufacture method of mosaic texture of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 6 is the flow chart of first embodiment of the manufacture method of mosaic texture of the present invention.
As shown in Figure 6, at first, provide the semiconductor substrate, in the described semiconductor-based end, be formed with metal line layer (S100).The described semiconductor-based end can be materials such as silicon on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier (SOI), arsenicization are sowed, silicon Germanium compound, described plain conductor layer material can be a kind of or its combination in copper, aluminium, titanium, titanium nitride, the tungsten, and metal carbonyl conducting layer described in the present embodiment is a copper.
Form etching stop layer on the described semiconductor-based end, form dielectric layer on described etching stop layer, form opening in described dielectric layer, the surface of described metal carbonyl conducting layer (S110) is exposed in the bottom of described opening.Described etching stop layer comprises a kind of in silicon nitride, carbon nitrogen silicon compound, the O-N-Si compound or its combination, and the formation method of described etching stop layer is a kind of in physical vapour deposition (PVD), plasma enhanced chemical vapor deposition, low-pressure chemical vapor deposition, high density plasma CVD, the ald; Described dielectric layer is a kind of in black diamond, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, silica, silicon nitride, the carborundum or its combination, and the method that forms described dielectric layer is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).
The step that forms opening in described dielectric layer is as follows: spin coating anti-reflecting layer on described dielectric layer, and spin coating photoresist on described anti-reflecting layer forms patterns of openings by exposure imaging; By etching described patterns of openings is transferred in the described dielectric layer and to be formed opening, expose on the etching stop layer of the described open bottom of etching to the surface of described metal carbonyl conducting layer; Remove described photoresist layer by oxygen gas plasma ashing and wet-cleaned.
Described opening is a connecting hole, can also form groove through again photoetching process.
Owing in subsequent technique, need in described opening, form copper interconnection structure by plated metal copper, and copper has very strong diffusivity, thereby be diffused in the described dielectric layer for avoiding copper directly to contact with the dielectric layer of described opening sidewalls, need form the first metal layer of barrier effect at the sidewall of described opening, described the first metal layer also is deposited on the bottom and the described dielectric layer surface (S120) of described opening simultaneously, this the first metal layer stops the diffusion of copper on the one hand, also play the adhesive effect of copper and described dielectric layer on the other hand, described the first metal layer is a tantalum, a kind of or combination in the tantalum nitride, the method for formation is a physical vapour deposition (PVD), chemical vapour deposition (CVD), ald, a kind of in the electrochemical deposition.The first metal layer described in the present embodiment is the combination of tantalum, tantalum nitride, by sidewall and bottom deposit the first metal layer at whole dielectric layer surface and described opening, make described semiconductor-based basal surface form a conductive layer, this conductive layer can play the electrical effect of the whole plasma environment of balance in follow-up plasma-treating technology, make whole plasma environment be in the electric neutrality state as much as possible, eliminate the part of plasma environment and assemble the coupling phenomenon of electric charge at described plain conductor laminar surface.
Remove the first metal layer of described open bottom by plasma bombardment, and remove the oxide (S130) of the plain conductor laminar surface of described open bottom.The copper metal carbonyl conducting layer is exposed to the cupric oxide that is easy to form on the surface high resistivity in the external environment condition, and follow-up metal interconnecting wires can increase contact resistance when contacting with described copper metal carbonyl conducting layer, thereby reduces the performance of device, increases power consumption.Thereby in manufacturing process, need this copper oxide is removed.Plasma described in the present embodiment is an argon plasma.The bombardment of the argon plasma by this step, at first remove the first metal layer of described open bottom, and make and the first metal layer attenuate on described dielectric layer surface further continue cupric oxide by the plain conductor laminar surface of the described open bottom of described argon plasma bombardment removal.Because oneself is through having formed the first metal layer of conduction at described semiconductor-based basal surface in preceding road technology, in the plasma bombardment technology of this step, gathering electric charge local in the plasma environment can be discharged into other zone by this first metal layer, and with the gathering charging neutrality of opposite polarity, make whole plasma environment be in electric neutrality as far as possible, reduce or eliminated the coupling phenomenon of local gathering electric charge in described metal carbonyl conducting layer, thereby eliminated the breakoff phenomenon of this couple current grid oxygen.
Then, at described open bottom and side wall deposition second metal level, described second metal level and the first metal layer are material of the same race (S140), owing in preceding road plasma bombardment technology, may cause the first metal layer of described opening sidewalls destroyed, and the dielectric layer of described opening sidewalls is exposed, this step is once more at described opening sidewalls deposition of tantalum and tantalum nitride, thereby effectively stops the diffusion of follow-up copper, and described second metal level can have different materials with described the first metal layer.
Deposition the 3rd metal level (S150) on described second metal level.The 3rd metal level described in the present embodiment is a copper, the method for its deposition for electroplate, a kind of in the chemical vapour deposition (CVD).Described copper fills up described opening at least.Further, carry out the cmp step, remove the copper and second metal layer material on described dielectric layer surface, promptly formed the mosaic texture of copper.
In the manufacturing process of mosaic texture of the present invention, at first be formed with dielectric layer surface and the described open bottom and the side wall deposition the first metal layer of opening, make whole semiconductor-based basal surface have conductivity, removing in the metal carbonyl conducting layer oxide on surface process of described open bottom with the argon plasma bombardment, gathering electric charge local in the plasma environment can be discharged into other zone by the first metal layer of this conduction.And with the gathering charging neutrality of opposite polarity, thereby make whole plasma environment be in electric neutrality as far as possible, reduce or eliminated the coupling phenomenon of local gathering electric charge in described metal carbonyl conducting layer, thereby eliminated the destruction of this couple current grid oxygen; Because the first metal layer of metal material at first is deposited on described dielectric layer surface and described open bottom and sidewall, stopped of the bombardment of described argon plasma to described dielectric layer, reduced damage and failure, thereby helped improving the puncture voltage of described dielectric layer described dielectric layer; In the prior art, in dielectric layer, behind the formation opening, at first carry out the argon plasma bombardment, then bombard with hydrogen gas plasma, and then deposition of tantalum and tantalum nitride and metallic copper, the inventive method has been saved the hydrogen gas plasma implant steps, save processing step, reduced cost.
First embodiment to the manufacture method of mosaic texture of the present invention is described in detail below in conjunction with profile.
Step 1 as shown in Figure 7, is formed with metal carbonyl conducting layer 200a and device layer in semiconductor substrate 200.The described semiconductor-based end 200 can be materials such as silicon on polysilicon, monocrystalline silicon, amorphous silicon, the insulating barrier (SOI), arsenicization are sowed, silicon Germanium compound, and described device layer is a metal oxide semiconductor transistor.Described metal carbonyl conducting layer 200a material is a kind of or its combination in copper, aluminium, titanium, titanium nitride, the tungsten, and the 200a of metal carbonyl conducting layer described in present embodiment material is a copper.
Step 2 is to carrying out the plasma surface preliminary treatment in the described semiconductor-based end 200 with device layer.To reduce or eliminate the pollutant on surface, the described semiconductor-based ends 200, improve the character of Facing material of the described semiconductor-based ends 200, strengthen the etching stop layer of subsequent technique formation and the adhesiveness on surface, the described semiconductor-based ends 200.Then, as shown in Figure 8, after the plasma preliminary treatment of finishing surface, the described semiconductor-based ends 200, deposition one etching stop layer 202 on surface, the described semiconductor-based ends 200.The method that deposits described etching stop layer 202 is a kind of in physical vapour deposition (PVD), low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, high density plasma CVD, the ald.Described etching stop layer 202 is a kind of or its combination in silicon nitride, nitrogen silicon oxide compound, the nitrogen-doped silicon carbide, and the reacting gas that deposits described etching stop layer 202 is a kind of or its combination in ammonia, silane, TEOS, dichloro-dihydro silicon, nitrous oxide, the nitrogen.Etching stop layer 202 thickness of deposition are 20 to 80nm.
As shown in Figure 9, on described etching stop layer 202, form dielectric layer 204.Described dielectric layer 204 is a kind of or its combination in black diamond, fluorine silex glass, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, silica, silicon nitride, the carborundum, and the method that forms described dielectric layer 204 is physical vapour deposition (PVD) or chemical vapour deposition (CVD).
The present embodiment split shed is connecting hole and groove, describes below in conjunction with the manufacture method of the technology that forms groove behind elder generation's formation connecting hole to mosaic texture of the present invention.
As shown in figure 10, spin coating anti-reflecting layer 206 on described dielectric layer 204, spin coating first photoresist layer 208 forms first patterns of openings 210 by technologies such as exposure imagings on described anti-reflecting layer 206.
As shown in figure 11, be barrier material with described first photoresist layer 208, described anti-reflecting layer 206 of etching and dielectric layer 204 form connecting hole 210a in described dielectric layer 204, and described connecting hole 210a exposes described etching stop layer 202 surfaces in the bottom.
Remove described first photoresist layer 208.Then, as shown in figure 12, spin coating sacrifice layer 212 on described connecting hole 210a neutralization medium layer 204, described sacrifice layer 212 can be photoresist, antireflection material etc.Spin coating second photoresist layer 214 on described sacrifice layer 212, and exposure imaging generates second patterns of openings 216.As shown in figure 13, described channel patterns 216 is transferred to formation groove 216a in the described dielectric layer 204, remove described second photoresist layer 214 and sacrifice layer 212 by etching.As shown in figure 14, expose on etching stop layer 202 to the described metal carbonyl conducting layer 200a surface of the described connecting hole 210a of etching bottom.
Step 3, owing in subsequent technique, need in described connecting hole 210a and groove 216a, form copper-connection by plated metal copper, and copper has very strong diffusivity, be diffused in the described dielectric layer 204 for avoiding copper directly to contact with the dielectric layer 204 of described connecting hole 210a and groove 216a sidewall, as shown in figure 15, formed the first metal layer 220 of barrier effect at the sidewall of described connecting hole 210a and groove 216a, described the first metal layer 220 also is deposited on bottom and described dielectric layer 204 surfaces of described connecting hole 210a simultaneously.This first metal layer 220 stops the diffusion of copper on the one hand, also plays the adhesive effect of copper and described dielectric layer 204 on the other hand.Described the first metal layer 220 is a kind of in tantalum, the tantalum nitride or combination, and the method for formation is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), ald, the electrochemical deposition.The first metal layer described in the present embodiment 220 is the combination of tantalum, tantalum nitride.By at the sidewall of whole dielectric layer 220 surfaces, described connecting hole 210a and the side wall deposition the first metal layer 220 of bottom and described groove 216a, make surface, the described semiconductor-based ends 200 form a conductive layer, this conductive layer can play the electrical effect of the whole plasma environment of balance in follow-up plasma-treating technology, make whole plasma environment be in the electric neutrality state as much as possible.
Step 4 as shown in figure 16, is removed the first metal layer 220 of described connecting hole 210a bottom by plasma bombardment, further removes the oxide on the metal carbonyl conducting layer 200a surface of described connecting hole 210a bottom.The metal carbonyl conducting layer 200a of copper material is exposed to the cupric oxide that is easy to form on the surface high resistivity in the external environment condition, follow-up metal interconnecting wires is when contacting with described copper metal carbonyl conducting layer 200a, can increase contact resistance, thereby reduction device performance, increase power consumption, thereby in manufacturing process, need this copper oxide is removed.Plasma described in the present embodiment is an argon plasma, the bombardment of the argon plasma by this step, at first remove the first metal layer 220 of described connecting hole 210a bottom, and make the first metal layer 220 attenuates on described dielectric layer 204 surfaces, further remove the cupric oxide on the metal carbonyl conducting layer 200a surface of described connecting hole 210a bottom by described argon plasma bombardment.Owing in preceding road technology, formed the first metal layer 220 of conduction on surface, the described semiconductor-based ends 200, in the plasma bombardment technology of this step, gathering electric charge local in the plasma environment can be discharged into other zone by this first metal layer 220, with opposite polarity gathering charging neutrality, make whole plasma environment be in electric neutrality as far as possible, reduce or eliminated local gathering electric charge in described metal carbonyl conducting layer 200a, to produce the couple current phenomenon, thereby eliminated the destruction of this couple current grid oxygen.
Step 5, at described connecting hole 210a bottom and sidewall, and trenched side-wall deposition of tantalum and tantalum nitride once more, owing in preceding road plasma bombardment technology, may cause the first metal layer 220 of described connecting hole 210a and groove 216a sidewall destroyed, and the dielectric layer 204 of described connecting hole 210a and groove 216a sidewall is exposed, this step is once more at described connecting hole 210a and groove 216a side wall deposition tantalum and tantalum nitride, thereby guarantees better to stop the diffusion of the copper of follow-up deposition.
Step 6, as shown in figure 17, deposition the 3rd metal level 230 on described second metal level.The 3rd metal level 230 is a copper described in the present embodiment, the method for its deposition for electroplate, a kind of in the chemical vapour deposition (CVD).Described copper fills up described connecting hole 210a and groove 216a at least.Further carry out the cmp step, remove described dielectric layer 204 surfaces copper and and second metal level, 220 materials, promptly formed the mosaic texture of copper.
The present invention also provides a kind of manufacture method of mosaic texture, and Figure 18 is the flow chart of second embodiment of mosaic texture of the present invention.
As shown in figure 18, at first, the one semiconductor-based end with metal carbonyl conducting layer, be provided, on the described semiconductor-based end, the formation dielectric layer is arranged, and in described dielectric layer, be formed with the bottom and expose the opening (S200) of described plain conductor laminar surface, the material of metal carbonyl conducting layer described in the present embodiment is a copper, described dielectric layer be black diamond (Black Diamond, BD);
At described open bottom and side wall deposition the first metal layer (S210); Described the first metal layer is tantalum nitride and tantalum, and the method for deposition is physical vapour deposition (PVD) or chemical vapour deposition (CVD);
Remove the first metal layer of described open bottom with the argon plasma bombardment, and remove the oxide (S220) of the plain conductor laminar surface of described open bottom;
Second metal level (S230) in described open bottom and side wall deposition and the first metal layer material of the same race;
Deposition the 3rd metal level (S240) on described second metal level.The 3rd metal level described in the present embodiment is a copper, and the method for deposition is chemical vapour deposition (CVD) or plating.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1, a kind of manufacture method of mosaic texture comprises:
The one semiconductor-based end with metal carbonyl conducting layer, be provided;
Form dielectric layer on the described semiconductor-based end, and form opening in described dielectric layer, described open bottom is exposed described plain conductor laminar surface;
At described open bottom and side wall deposition the first metal layer;
Remove the oxide of the plain conductor laminar surface of the first metal layer of described open bottom and described open bottom;
At described open bottom and side wall deposition second metal level;
Deposition the 3rd metal level on described second metal level.
2, the manufacture method of mosaic texture as claimed in claim 1 is characterized in that: described dielectric layer is a kind of or its combination in silica, silicon nitride, carborundum, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, fluorine silex glass, the black diamond.
3, the manufacture method of mosaic texture as claimed in claim 1 is characterized in that: the step that forms opening in described dielectric layer is as follows:
Spin coating photoresist layer on described dielectric layer, and graphically form patterns of openings;
By etching described patterns of openings is transferred in the described dielectric layer, formed opening;
Remove described photoresist layer.
4, the manufacture method of mosaic texture as claimed in claim 1 is characterized in that: the described the first metal layer and second metal level are a kind of or combination in tantalum, the tantalum nitride.
5, the manufacture method of mosaic texture as claimed in claim 4 is characterized in that: the deposition process of the described the first metal layer and second metal level is a kind of in physical vapour deposition (PVD), chemical vapour deposition (CVD), ald, the electrochemical deposition.
6, the manufacture method of mosaic texture as claimed in claim 1 is characterized in that: the method for oxide of removing the plain conductor laminar surface of the first metal layer of described open bottom and described open bottom is a dry plasma.
7, the manufacture method of mosaic texture as claimed in claim 6 is characterized in that: the plasma in the described dry plasma technology is an argon plasma.
8, the manufacture method of mosaic texture as claimed in claim 1 is characterized in that: on described second metal level method of deposition the 3rd metal level for electroplate, a kind of in the chemical vapour deposition (CVD).
9, the manufacture method of mosaic texture as claimed in claim 8 is characterized in that: described the 3rd metal level is a copper.
10, a kind of semiconductor device comprises:
The semiconductor-based end; The described semiconductor-based end, have metal carbonyl conducting layer;
Be formed at the suprabasil dielectric layer of described semiconductor;
Have opening in described dielectric layer, described plain conductor laminar surface is exposed in the bottom of described opening;
It is characterized in that: described dielectric layer surface and described opening sidewalls are coated with metal level, and described metal level is used for spreading the gathering electric charge of described plasma etching gas when plasma etching.
11, semiconductor device as claimed in claim 11 is characterized in that: described metal level is a kind of or combination in tantalum, the tantalum nitride.
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| CNB2006101478035A CN100517643C (en) | 2006-12-22 | 2006-12-22 | Method for manufacturing inlaid structure |
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| CN101661899B (en) * | 2008-08-29 | 2010-12-15 | 上海华虹Nec电子有限公司 | Method for producing contact holes in metal gates by adopting Damascus process |
| CN101661881B (en) * | 2008-08-29 | 2012-06-20 | 上海华虹Nec电子有限公司 | Method for producing metal gates and contact holes by adopting Damascus process |
| EP2360293A1 (en) | 2010-02-11 | 2011-08-24 | Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO | Method and apparatus for depositing atomic layers on a substrate |
| EP2362001A1 (en) * | 2010-02-25 | 2011-08-31 | Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO | Method and device for layer deposition |
| EP2362411A1 (en) | 2010-02-26 | 2011-08-31 | Nederlandse Organisatie voor toegepast -natuurwetenschappelijk onderzoek TNO | Apparatus and method for reactive ion etching |
| CN107703722B (en) * | 2016-08-08 | 2020-12-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming patterned photoresist |
| CN111063828A (en) * | 2019-12-31 | 2020-04-24 | 安徽熙泰智能科技有限公司 | Silicon-based Micro OLED Micro-display anode and preparation method thereof |
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