CN100517506C - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
CN100517506C
CN100517506C CNB2005800006399A CN200580000639A CN100517506C CN 100517506 C CN100517506 C CN 100517506C CN B2005800006399 A CNB2005800006399 A CN B2005800006399A CN 200580000639 A CN200580000639 A CN 200580000639A CN 100517506 C CN100517506 C CN 100517506C
Authority
CN
China
Prior art keywords
mentioned
circuit
import
export department
holding circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005800006399A
Other languages
Chinese (zh)
Other versions
CN1820324A (en
Inventor
炭田昌哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of CN1820324A publication Critical patent/CN1820324A/en
Application granted granted Critical
Publication of CN100517506C publication Critical patent/CN100517506C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

In a semiconductor integrated circuit having a multi-port register file, a first holding circuit (20A) is dedicated to a first function block having a first write port part (21AW) and two first read port parts (21AR1,21AR2). A second holding circuit (30B) is dedicated to a second function block having a second write port part (31AW) and a second read port part (31BR). When there occurs a need of reading the held data of the first holding circuit (20A) via, for example, the second read port part (31BR), the data of the second holding circuit (30B) is latched by a latch circuit (40), thereafter the data of the first holding circuit (20A) is transferred to the second holding circuit (30B), and then the data of the second holding circuit (30B) latched by the latch circuit (40) is transferred to the first holding circuit (20A), thereby exchanging the data. Accordingly, the area required for the register file can be significantly reduced.

Description

SIC (semiconductor integrated circuit)
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit), particularly have the structure of the register files of importing and exporting more.
Background technology
In the past, in SIC (semiconductor integrated circuit), when having the register file of many import and export, a plurality of functional blocks were connected this imports and exports on register files, so that can utilize these a plurality of functional blocks to carry out the processing arranged side by side of data more.
For example, in patent documentation 1, to import and export number be 2 in order to write to make the register file, and reading and importing and exporting number also is many turnover shape of the mouth as one speaks (2Write 2Read (2W2R) type) of 2, and 1W1R type functional block and other 1W1R type functional block are connected on the above-mentioned 2W2R turnover shape of the mouth as one speaks register file.That is to say, this 2W2R turnover shape of the mouth as one speaks register file, constitute: for memory cell prepare two read import and export and two write import and export, and with one read import and export and one write to import and export and be connected on the 1st functional block, another is read import and export and another writes import and export and is connected on the 2nd functional block simultaneously.
And, in containing the transistor circuit of above-mentioned memory cell, in the past, its form transistorized threshold voltage, to its form service voltage that transistor provides, its form transistorized activate rate, with and power consumption between, have under the regulation activate rate that is given and make minimum threshold voltage of power consumption and service voltage, for example, be documented in the non-patent literature 1.
[patent documentation 1] spy opens flat 11-175394 communique (Figure 13)
[non-patent literature 1] K.Nose et al. .Optimization of VDD and VTH forlow-power and high-speed applications .ASPDAC.00, pp.469-474, Jan.2000.
But, in SIC (semiconductor integrated circuit), have following shortcoming with above-mentioned many turnover shape of the mouth as one speaks register file in the past.
That is to say, in many turnover shape of the mouth as one speaks register file in the past, as mentioned above, each memory cell is prepared the import and export that write import and export and read the total number of import and export of a plurality of functional blocks of connection.Therefore, pass in and out shape of the mouth as one speaks register file more and have the shortcoming that area increases.
And, in above-mentioned many turnover shape of the mouth as one speaks register file in the past, for example, when the activate rate (visiting frequency) of a functional block that connects higher, when the activate rate of other functional block is low, though owing under an activate rate, exist in order to make little power consumption arrive the service voltage and the transistorized threshold voltage of optimum condition, but when another activate rate is used memory cell, its service voltage and threshold voltage can not become optimum value, therefore there is not make power consumption minimum the problem of waste power consumption.
So, for example, expected not adopting such in the past between a plurality of functional blocks the structure of shared storage unit, but adopt the structure of in each functional block, using special-purpose memory cell.Under this design, can be to the memory cell of special use, the corresponding service voltage of activate rate and the threshold voltage of setting and this special function piece can reduce power consumption effectively.And, as long as the memory cell to special use is provided with its special-purpose total import and export number of reading import and export and writing import and export that functional block had, can cut down the import and export number that other functional block has, will import and export number and be cut to needed import and export number, can save area.
But, in above-mentioned design, when the needed data of certain functional block, not to be accommodated in its special-purpose memory cell, but when being accommodated in the private memory unit of other functional block, be created in and carry out, carry out the necessity of reading of these data again from oneself private memory unit after the operation of this exchanges data in the private memory unit of oneself.At this moment, for example, expected adopting the data in the private memory unit that will be accommodated in oneself temporarily to be kept in the external register, then, to be sent to the structure in oneself the private memory unit from the data of the private memory unit of other functional block, in this design, produce following problem: need be arranged on outside save register and connected data bus etc., not only in the visit of data, need the time, and cause area to increase.And it is long for the grid about tens of millimicros to have a miniaturization process (process), because of the limit and the quantum effect of photoetching causes leakage current increase etc.
Summary of the invention
The present invention is conceived to above-mentioned problem, and its purpose is: a kind of import and export number that memory cell is required of both having cut down is provided, has the SIC (semiconductor integrated circuit) that can carry out many turnover shape of the mouth as one speaks register file of data access in the short time again.
In order to achieve the above object, adopted following structure in the present invention: when adopting the structure of in each functional block, using special-purpose memory cell basically, when the data of the memory cell that in another functional block, needs other functional block special use, in memory cell array, carry out the exchanges data between the memory cell.
Specifically, SIC (semiconductor integrated circuit) of the present invention is characterised in that, comprising: the 1st and the 2nd information holding circuit is formed on memory cell array, maintenance information; The 1st Import ﹠ Export Department only is connected on above-mentioned the 1st information holding circuit, is used for information and inputs or outputs; The 2nd Import ﹠ Export Department only is connected on above-mentioned the 2nd information holding circuit, is used for information and inputs or outputs; And switched circuit, accept the exchange control signal, in above-mentioned memory cell array, exchange information that remains in above-mentioned the 1st information holding circuit and the information that remains in above-mentioned the 2nd information holding circuit mutually.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department is made of transistor circuit respectively.The above-mentioned the 1st and the transistor circuit of the 2nd Import ﹠ Export Department, constitute by the different transistor of threshold voltage each other.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department, visiting frequency differs from one another.The visiting frequency of the Import ﹠ Export Department that is made of the higher transistor of threshold voltage is lower than the visiting frequency of the Import ﹠ Export Department that is made of the lower transistor of threshold voltage.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department, the supply voltage of accepting to supply with differs from one another.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the visiting frequency of the Import ﹠ Export Department that supply voltage is lower is lower than the visiting frequency of the higher Import ﹠ Export Department of supply voltage.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd information holding circuit is made of transistor circuit respectively.The above-mentioned the 1st and the transistor circuit of the 2nd information holding circuit, the transistor that is differed from one another by threshold voltage constitutes.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the visiting frequency of the information holding circuit that is made of the higher transistor of above-mentioned threshold voltage is lower than the visiting frequency of the information holding circuit that is made of the lower transistor of threshold voltage.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd information holding circuit, the supply voltage of accepting to supply with differs from one another.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the visiting frequency of the information holding circuit that supply voltage is lower is lower than the visiting frequency of the higher information holding circuit of supply voltage.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), above-mentioned switched circuit has the temporary transient temporary transient holding circuit of getting up that keeps of information.The information that keeps in the above-mentioned the 1st and the 2nd information holding circuit according to above-mentioned exchange control signal, exchanges mutually through above-mentioned temporary transient holding circuit.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), detect the end that mutual exchange remains on the switching motion of the information in the above-mentioned the 1st and the 2nd information holding circuit, detecting the output that stops above-mentioned exchange control signal when this exchange finishes.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), detect and allow the information in the above-mentioned the 1st and the 2nd information holding circuit of remaining on be maintained at state in these the 1st and the 2nd information holding circuits, after detecting, remain on the mutual exchange of the information in the above-mentioned the 1st and the 2nd information holding circuit.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department is made of transistor circuit respectively.The above-mentioned the 1st and the transistor circuit of the 2nd Import ﹠ Export Department, constitute by the transistor of the corresponding transistor width of access speed of Import ﹠ Export Department respectively with oneself.The transistor width of the transistor circuit of the Import ﹠ Export Department that access speed is slower is narrower than the access speed transistor width of the transistor circuit of Import ﹠ Export Department faster.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd information holding circuit is made of transistor circuit respectively.The above-mentioned the 1st and the transistor circuit of the 2nd information holding circuit, respectively by with the information holding circuit that is connected oneself on the transistor of the corresponding transistor width of access speed of Import ﹠ Export Department constitute.The transistor width of the transistor circuit of the information holding circuit that access speed is slower is narrower than the access speed transistor width of the transistor circuit of information holding circuit faster.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), above-mentioned temporary transient holding circuit is made of latch circuit.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), above-mentioned latch circuit is a differential circuit.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), above-mentioned switched circuit comprises: latch circuit, with temporary transient maintenance of information that remains in the lower information holding circuit of supply voltage, and the information that will keep outputs in the higher information holding circuit of supply voltage.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are made of transistor circuit respectively.Group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and the group that is made of above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit have the underlayer voltage control circuit respectively.Above-mentioned underlayer voltage control circuit, the transistorized threshold voltage that will constitute the Import ﹠ Export Department of oneself group and each transistor circuit of information holding circuit respectively is controlled to be the corresponding threshold voltage of visiting frequency with the own Import ﹠ Export Department that organizes.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and the group that is made of above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit have source voltage control circuit respectively.Above-mentioned source voltage control circuit respectively according to information readout time and write time in the oneself Import ﹠ Export Department, is controlled Import ﹠ Export Department and the supply voltage that provides of information holding circuit to oneself.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are made of transistor circuit respectively.Group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and the group that is made of above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit have underlayer voltage control circuit and source voltage control circuit respectively.Above-mentioned underlayer voltage control circuit, the transistorized threshold voltage that will constitute the Import ﹠ Export Department of oneself group and each transistor circuit of information holding circuit respectively is controlled to be the threshold voltage of regulation.Above-mentioned source voltage control circuit is provided respectively by Import ﹠ Export Department and the supply voltage that provides of information holding circuit to oneself, makes information readout time and write time in oneself the Import ﹠ Export Department be respectively setting-up time.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are formed on the transistor that a plurality of transistors are arranged in juxtaposition portion arranged side by side.Import ﹠ Export Department that responsiveness is slower and information holding circuit are positioned at the end of above-mentioned transistor portion arranged side by side.Responsiveness is Import ﹠ Export Department and information holding circuit faster, is positioned at the inboard of above-mentioned transistor portion arranged side by side.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), comprising: the 1st and the 2nd virtual information holding circuit, be formed on formed the above-mentioned the 1st and the cell array of the 2nd information holding circuit in.Above-mentioned exchange control signal reflects that reality exchanges the switching time that remains on the information in the above-mentioned the 1st and the 2nd virtual information holding circuit each other, is exporting through stopping after this switching time.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the substrate that has formed above-mentioned the 1st Import ﹠ Export Department separates with the substrate that has formed above-mentioned the 2nd Import ﹠ Export Department.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the substrate that has formed above-mentioned the 1st information holding circuit separates with the substrate that has formed above-mentioned the 2nd information holding circuit.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), above-mentioned temporary transient holding circuit is made of transistor circuit, and the transistorized threshold setting that will constitute is and the corresponding threshold value of the visiting frequency of above-mentioned switch-over control signal.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), above-mentioned temporary transient holding circuit is set at access speed correspondent voltage with above-mentioned switch-over control signal with the supply voltage of supplying with.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the access speed of the 2nd Import ﹠ Export Department be fixing speed.The visiting frequency of the Import ﹠ Export Department that supply voltage is lower is higher than the visiting frequency of the higher Import ﹠ Export Department of supply voltage.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the visiting frequency of the information holding circuit that supply voltage is lower is higher than the visiting frequency of the higher information holding circuit of supply voltage.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the supply voltage of above-mentioned switched circuit is higher than the supply voltage that the lower information of supply voltage is imported the Import ﹠ Export Department of usefulness.Above-mentioned switched circuit, comprise: latch circuit, the temporary transient maintenance of information that will in the information holding circuit of the Import ﹠ Export Department that is connected the higher information input usefulness of supply voltage, keep, and the information that will keep outputs in the information holding circuit of the Import ﹠ Export Department that is connected the lower information input usefulness of supply voltage.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), above-mentioned temporary transient holding circuit is made of the 1st phase inverter and the 2nd phase inverter.The output of above-mentioned the 1st phase inverter is connected in the input of above-mentioned the 2nd phase inverter.Above-mentioned the 2nd phase inverter has the 1st and 2NMOS transistor of series connection.The input of above-mentioned the 1st phase inverter is connected on the 1NMOS transistor drain of the output of the 1st or the 2nd Import ﹠ Export Department of information input usefulness and above-mentioned the 2nd phase inverter.The above-mentioned 1NMOS transistor of above-mentioned the 2nd phase inverter, its grid are connected in the output of above-mentioned the 1st phase inverter, and its source electrode is connected on the above-mentioned 2NMOS transistor drain.Import the output of the 1st or the 2nd Import ﹠ Export Department of above-mentioned information input usefulness to the transistorized grid of the above-mentioned 2NMOS of above-mentioned the 2nd phase inverter.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the number of the 1st or the 2nd Import ﹠ Export Department of information input usefulness is one.Import the energizing signal of signal of the 1st or the 2nd Import ﹠ Export Department of above-mentioned information input usefulness to the transistorized source electrode of the above-mentioned 2NMOS of above-mentioned the 2nd phase inverter.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the number of the 1st or the 2nd Import ﹠ Export Department of information input usefulness is a plurality of.The transistorized number of above-mentioned 2NMOS of above-mentioned the 2nd phase inverter is the number that equates with the above-mentioned the 1st and the number of the 2nd Import ﹠ Export Department.Above-mentioned a plurality of 2NMOS transistor series will wherein be positioned at apart from the transistorized source ground of 2NMOS of the 1NMOS transistor position farthest of above-mentioned the 2nd phase inverter together.Signal to transistorized each grid input the corresponding the above-mentioned the 1st of above-mentioned a plurality of 2NMOS or the 2nd Import ﹠ Export Department.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), the signal of the Import ﹠ Export Department that the activate rate in the 1st or the 2nd Import ﹠ Export Department of a plurality of information input usefulness is higher is input to the transistorized grid of 2NMOS that is positioned at apart from the 1NMOS transistor position farthest of above-mentioned the 2nd phase inverter.
The invention is characterized in, in above-mentioned SIC (semiconductor integrated circuit), comprising: the 1st virtual circuit, to above-mentioned the 1st information holding circuit carry out reading of data and subsequent data write and the 1st and the 2nd information holding circuit between exchanges data; And the 2nd virtual circuit, above-mentioned the 2nd information holding circuit is carried out exchanges data between writing of reading of data and subsequent data and the 1st and the 2nd information holding circuit.Constitute a plurality of MOS transistor of above-mentioned the 1st virtual circuit, the MOS characteristic of diffusion layer concentration, underlayer voltage or gate oxidation mould is all identical.Constitute a plurality of MOS transistor of above-mentioned the 2nd virtual circuit, its part has same MOS characteristic with above-mentioned MOS characteristic, and remaining part has the different MOS characteristic of MOS characteristic with the MOS transistor that constitutes above-mentioned the 1st virtual circuit; This SIC (semiconductor integrated circuit) have adjustment offer respectively the above-mentioned the 1st and the supply voltage of the supply voltage of the 2nd virtual circuit adjust circuit.Above-mentioned supply voltage is adjusted circuit, the supply voltage value that adjustment provides to above-mentioned the 1st virtual circuit, make the output delay of output signal value of above-mentioned the 1st virtual circuit become the predefined the 1st with reference to length of delay, the supply voltage value that will adjust offers the MOS transistor of the same MOS characteristic of the MOS transistor with above-mentioned the 1st virtual circuit in above-mentioned the 2nd virtual circuit simultaneously; And, the supply voltage value that the MOS transistor of the MOS characteristic that the MOS transistor with above-mentioned 1st virtual circuit of adjustment in above-mentioned the 2nd virtual circuit is different provides makes the output delay of output signal value of above-mentioned the 2nd virtual circuit become the predefined the 2nd with reference to length of delay.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are made of transistor circuit respectively.The group that group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit and above-mentioned switched circuit constitute has the power supply voltage supplying circuit of the supply voltage that different value is provided respectively.The summation that the above-mentioned supply voltage value of respectively organizing power supply voltage supplying circuit is set at information readout time, write time and swap time in oneself the Import ﹠ Export Department respectively is the supply voltage value of stipulated time.
The invention is characterized in that in above-mentioned SIC (semiconductor integrated circuit), SIC (semiconductor integrated circuit) is a multithreading type processor.
As mentioned above, in SIC (semiconductor integrated circuit) of the present invention, because the 1st information holding circuit is exclusively used in the 1st Import ﹠ Export Department basically, therefore the 2nd information holding circuit is exclusively used in the 2nd Import ﹠ Export Department basically, has cut down the import and export number of the part of Import ﹠ Export Department in addition of own special-purpose Import ﹠ Export Department in these information holding circuits.And, for example, will be with the information of the 1st information holding circuit during when producing from necessity that the 2nd Import ﹠ Export Department reads, since in memory cell array by in message exchange to the 2 information holding circuits of switched circuit with the 1st information holding circuit, therefore with being arranged on, save register etc. compares when the swap operation of information is carried out in the outside, the access speed of information accelerates, and can conduct interviews at short notice.
And, owing to always read/write the information of the 1st information holding circuit from the 1st Import ﹠ Export Department of special use, therefore can be to the 1st information holding circuit and the 1st Import ﹠ Export Department, with its supply voltage that provides and its form transistorized threshold voltage settings for the corresponding value of visiting frequency (activate rate) of the 1st Import ﹠ Export Department of its special use, the little power consumption that can make the 1st information holding circuit and the 1st Import ﹠ Export Department is to the best.This also is the same for the 2nd information holding circuit and the 2nd Import ﹠ Export Department.
And in the present invention, the message exchange of carrying out between two information holding circuits is undertaken by latch circuit.At this moment, owing to will be latched in the above-mentioned latch circuit with the information of the information holding circuit of low supply voltage action, then, output in the information holding circuit with high power supply voltage action, therefore the information of the information holding circuit of low supply voltage can be exchanged in the information holding circuit of high power supply voltage preferably.So, in the information holding circuit of low supply voltage,, also no problem even its supply voltage is a low-voltage.
In addition, in the present invention, because end in transistor portion arranged side by side, that probably cause the transistor performance deterioration too greatly because of the influence of STI (SharrowTrench Isolation element separation zone), arrange slower Import ﹠ Export Department and the information holding circuit of responsiveness, in the more weak zone of the inboard STI influence of transistor portion arranged side by side, arrange responsiveness Import ﹠ Export Department and information holding circuit faster, therefore guaranteed its responsiveness high speed and the stability of the action of Import ﹠ Export Department and information holding circuit faster preferably.
And, in addition, in the present invention, because when between two information holding circuits, carrying out the exchange of information, the actual exchange time that reflects the information between two virtual information holding circuits that are formed on memory cell array, therefore can under the situation of the influence of external environment conditions such as the deviation that is not subjected to manufacturing process so, temperature, voltage, between the information holding circuit, positively carry out the exchange of information, can realize the stabilization of moving.
And, in the present invention, because when writing the HI data in the temporary transient holding circuit, needn't set the transistorized grid length of the 1NMOS of the 2nd phase inverter longer in order to cut down saturation current, can be set shortlyer, therefore can cut down area, and owing to will not constitute the 1NMOS transistor by the long short transistor series of a plurality of grids, even thereby in the manufacturing process of miniaturization more, also can not produce the burden of area.In addition, because with the 1st and the 2NMOS transistor series, therefore can enough DIBL effects realize the reduction of subthreshold value (subthreshold) leakage current.
And, in the present invention, because be 3 sections cascaded structures that will be in series at the nmos pass transistor of the phase inverter of the signal of the Import ﹠ Export Department of two nmos pass transistors of the 2nd phase inverter and information input usefulness, therefore the leakage current with the 2nd phase inverter further reduces to 1/10.
And, in the present invention,, also increased the number of the nmos pass transistor that is had in the 2nd phase inverter owing to the number of importing the Import ﹠ Export Department of usefulness for information is a plural number, they are waited the structure that is cascaded, therefore cut down leakage current more.
In addition, in the present invention, because can be in the 2nd phase inverter, be that the source drain voltage of the higher nmos pass transistor of L is set lowlyer with grid potential, therefore can cut down grid leakage current.
And, in the present invention, because therefore the virtual circuit that can constitute a plurality of MOS transistor of MOS characteristic by regulation and provide appropriate supply voltage respectively by other virtual circuit that a plurality of MOS transistor of those MOS transistor and other MOS characteristic constitute can realize the low consumption electrification.
(effect of invention)
As mentioned above, according to SIC (semiconductor integrated circuit) of the present invention, because each Import ﹠ Export Department only is connected on the own special-purpose information holding circuit, therefore can cut down the import and export number of each information holding circuit significantly, and during the information of the out of Memory holding circuit beyond must reading own special-purpose information holding circuit from each Import ﹠ Export Department, because by being arranged on the switched circuit in the memory cell array, with the message exchange of above-mentioned out of Memory holding circuit in own special-purpose information holding circuit, therefore the access speed of information can be kept comparatively fast, can conduct interviews in the short time.And, can be with by Import ﹠ Export Department and to be exclusively used in the group that this information holding circuit constitutes be unit, set with the corresponding supply voltage of visiting frequency (activate rate) of the own Import ﹠ Export Department that organizes, form transistorized threshold voltage, have and to reduce the effect of respectively organizing power consumption.
And, use the present invention, the information of the information holding circuit of low supply voltage can be exchanged in the information holding circuit of high power supply voltage preferably, make its supply voltage lower voltage in the information holding circuit of low supply voltage simultaneously.
In addition, use the present invention and since with responsiveness faster Import ﹠ Export Department and information holding circuit be arranged in being difficult in the transistor portion arranged side by side and be subjected to the inboard of STI influence, therefore can keep its high speed motion and stability preferably.
Add, use the present invention, because when between two information holding circuits, carrying out the exchange of information, the actual exchange time that reflects the information between the virtual information holding circuit, therefore can be under the situation of the influence of external environment conditions such as the deviation that is not subjected to manufacturing process so, temperature, voltage, between the information holding circuit, positively carry out the exchange of information, can realize the stabilization of moving.
In addition, use the present invention, can cut down the area of temporary transient holding circuit,, also can suppress to produce the situation of area burden, and can enough DIBL effects cut down sub-threshold current leakage even simultaneously in the manufacturing process of miniaturization more.
And, use the present invention, can further cut down the leakage current of the 2nd phase inverter.
And, use the present invention, owing to can provide appropriate supply voltage, therefore can realize the low consumption electrification to a plurality of virtual circuits of a plurality of MOS transistor of MOS characteristic with regulation.
The simple declaration of accompanying drawing
Fig. 1 is the structural drawing that shows the related SIC (semiconductor integrated circuit) of embodiments of the invention.
Fig. 2 is that the portion that wants that shows the inner structure of the transistor file that has with SIC (semiconductor integrated circuit) schemes.
Fig. 3 is the sequential chart that shows carry out the switching motion of data with the register file.
Fig. 4 is the graph of a relation that shows activate rate with the writing Import ﹠ Export Department, read Import ﹠ Export Department of SIC (semiconductor integrated circuit), holding circuit and latch circuit, forms transistorized threshold voltage and supply voltage.
Fig. 5 is the cut-away view that shows the underlayer voltage control circuit that has in SIC (semiconductor integrated circuit).
Fig. 6 is the cut-away view that shows the DLL circuit that has in SIC (semiconductor integrated circuit).
Fig. 7 is the sequential chart that shows from the various signals of exporting with the DLL circuit.
Fig. 8 is the cut-away view that shows with the delay voltage translation circuit that has in the SIC (semiconductor integrated circuit).
Fig. 9 constitutes with the synoptic diagram of the position of the slower circuit part of circuit part and responsiveness faster of the responsiveness in the column of transistors of SIC (semiconductor integrated circuit) for explanation.
Figure 10 is the detailed circuit diagram that the various control signals that show the inner structure of the control circuit that has and will use the actual data exchange of two virtual circuits to reflect in SIC (semiconductor integrated circuit) generate.
Figure 11 is the detailed circuit diagram that shows the control circuit that has and used the exchanges data signal generating circuit of two virtual circuits in SIC (semiconductor integrated circuit).
Figure 12 shows by carry out the sequential chart of exchanges data action with the exchanges data signal generating circuit.
Figure 13 is for showing when with access speed fixedly the time, with the activate rate of the writing Import ﹠ Export Department, read Import ﹠ Export Department of SIC (semiconductor integrated circuit), holding circuit and latch circuit, form the graph of a relation of transistorized threshold voltage and supply voltage.
Figure 14 is that the portion that wants that shows the inner structure of the register file that satisfies relation shown in Figure 13 schemes.
Figure 15 shows all summary construction diagrams that satisfy same register file shown in Figure 13.
Figure 16 is the circuit diagram that shows the inner structure of delay voltage translation circuit.
Figure 17 is the action timing diagram that shows with the delay voltage translation circuit.
Figure 18 is the circuit structure diagram that shows the memory cell of the 1R/1W in the register file.
Figure 19 is the circuit structure diagram that shows the memory cell of the 1R/3W in the register file.
Figure 20 (a) is the cut-away view with the processor of the concrete application examples of SIC (semiconductor integrated circuit) for showing, with figure (b) for to show at switching sequence figure with the thread in the processor (thread).
Figure 21 is the cut-away view that shows to other processor of the concrete application examples of SIC (semiconductor integrated circuit).
(explanation of symbol)
1-register file; 2A-the 1st functional block; 2B-the 2nd functional block; The 5-memory cell array; 5a-normal memory one-element group; 5b～5f-virtual memory one-element group; 6-reads/write circuit; The 7-decoding scheme; The 8-control circuit; 9-delay voltage translation circuit; The 10-DLL circuit; 12a～12c-source voltage control circuit; 13a～13c-underlayer voltage control circuit; 20A-the 1st holding circuit (the 1st information holding circuit); 20AD1,20AD2-the 1st virtual holding circuit (the 1st virtual information holding circuit); 30BD1,30BD2-the 2nd virtual holding circuit (the 2nd virtual information holding circuit); 21AW-the 1st writes Import ﹠ Export Department; 21AR1,21AR2-the 1st read Import ﹠ Export Department; 30B-the 2nd holding circuit (the 2nd information holding circuit); 31AW-the 2nd writes Import ﹠ Export Department; 31AR-the 2nd reads Import ﹠ Export Department; 40-latch circuit (temporary transient holding circuit); 41,42-transfer circuit; The 43-switched circuit; The 61-column of transistors; The 70-testing circuit; 71-control signal generative circuit; 16B-MCA virtual circuit (the 2nd virtual circuit); 16C-MCB virtual circuit (the 1st virtual circuit); B1L, C1M-power control circuit (supply voltage is adjusted circuit and power supply voltage supplying circuit).
Embodiment
Be illustrated with reference to the SIC (semiconductor integrated circuit) of accompanying drawing embodiments of the invention.
(the 1st embodiment)
Fig. 1 shows the one-piece construction of the SIC (semiconductor integrated circuit) of the 1st embodiment of the present invention.
In with figure, 1 is the register file, and 2A and 2B are respectively functional block.To import and export number be 2 to above-mentioned register file 1 in order to write, and reading and importing and exporting number is 3 the 2W3R turnover shape of the mouth as one speaks.To import and export number be 1 in order to write for functional block 2A, and reading and importing and exporting number is 2 the 1W2R turnover shape of the mouth as one speaks, and another functional block 2B writes to import and export number and read that to import and export number all be 1 the 1W1R turnover shape of the mouth as one speaks.Therefore, register file 1 writes data line A-W1 with a functional block 2A with one and two sense data line A-R1, A-R2 are connected, and register file 1 writes data line B-W1 with one respectively with another functional block 2B and sense data line B-R1 is connected.
In above-mentioned register file 1, comprising: memory cell array 5, write/sensing circuit 6, decoding scheme 7, control circuit 8, delay voltage translation circuit 9 and DLL circuit 10.Above-mentioned memory cell array 5 also comprises: normal memory one-element group 5a and 5 virtual memory one-element group 5b～5f.These virtual memory one-element groups 5b～5f is identical with position (bit) wire shaped, word line shape and the memory cell shape of normal memory one-element group 5a.Above-mentioned writing/sensing circuit 6 writes data line A-W1, B-W1 with above-mentioned two functional block 2A, 2B with two and 3 sense data line A-R1, A-R2, B-R1 are connected.Will be in order to the address signal that writes/read that between above-mentioned two functional block 2A, 2B, carries out data, read the activate signal and write the activate signal and be input to above-mentioned control circuit 8, clock signal is input to above-mentioned DLL circuit 10.
And, in SIC (semiconductor integrated circuit) shown in Figure 1, comprise 3 source voltage control circuit 12a, 12b, 12c and 3 underlayer voltage control circuit 13a, 13b, 13c, again they are elaborated later on.
Fig. 2 shows the details that above-mentioned normal memory one-element group 5a is carried out the writing of data (information)/reading out structure.In with figure, 20A is the 1st holding circuit (the 1st information holding circuit) that is exclusively used in above-mentioned 1W2R type functional block 2A, 30B is the 2nd holding circuit (the 2nd information holding circuit) that is exclusively used in above-mentioned another 1W1R type functional block 2B, is made of two transducers (inverter) circuit I 1, I2 respectively.With the 1st of being exclusively used in above-mentioned 1W2R type functional block 2A write the 21AW of Import ﹠ Export Department (the 1st Import ﹠ Export Department of information input usefulness), and two the 1st read Import ﹠ Export Department (the 1st Import ﹠ Export Department of information output usefulness) 21AR1,21AR2 and be connected on above-mentioned the 1st holding circuit 20A.The above-mentioned the 1st writes the 21AW of Import ﹠ Export Department, constitute by the P type and N transistor npn npn Tr1, the Tr2 that respectively are 1, and be connected on the functional block 2A by writing data line A-W1, read the 21AR1 of Import ﹠ Export Department, 21AR2 and constitute by two N transistor npn npn Tr3, Tr4 respectively, and be connected on the functional block 2A for above-mentioned two by sense data line A-R1, A-R2.Data are write with word line WLWA be connected on the grid of the above-mentioned N transistor npn npn Tr2 that writes the 21AW of Import ﹠ Export Department, data are read with word line WLRA1, WLRA2 be connected on the grid of the N transistor npn npn Tr4 that respectively reads the 21AR1 of Import ﹠ Export Department, 21AR2.
Equally, the 2nd of being exclusively used in above-mentioned 1W1R type functional block 2B is write the 31AW of Import ﹠ Export Department (the 2nd Import ﹠ Export Department of information input usefulness), and 1 the 2nd read the 31AR of Import ﹠ Export Department (the 2nd Import ﹠ Export Department of information output usefulness) and be connected on above-mentioned the 2nd holding circuit 30B.The above-mentioned the 2nd writes the 31AW of Import ﹠ Export Department, with the above-mentioned the 1st to write the 21AW of Import ﹠ Export Department the same, constitute by the P type and N transistor npn npn Tr1, the Tr2 that respectively are 1, and be connected on the functional block 2B by writing data line B-W1, above-mentionedly read the 31AR of Import ﹠ Export Department and above-mentioned to read the 21AR1 of Import ﹠ Export Department the same, constitute by two N transistor npn npn Tr3, Tr4 respectively, and be connected on the functional block 2B by sense data line B-R1.Data are write with word line WLWB be connected on the grid of the above-mentioned N transistor npn npn Tr2 that writes the 31AW of Import ﹠ Export Department, data are read with word line WLRB be connected on the grid of the N transistor npn npn Tr4 that respectively reads the 31AR of Import ﹠ Export Department.
And in Fig. 2,40 is latch circuit (temporary transient holding circuit), is made of the differential circuit that comprises 4 P transistor npn npn Tr5～Tr8 and 3 N transistor npn npn Tr9～Tr11.41 and 42 is transfer circuit, comprises 4 N transistor npn npn Tr12～Tr15, Tr16～Tr19 respectively.Above-mentioned latch circuit 40 is connected on the 2nd holding circuit 30B of above-mentioned the 2nd functional block 2B special use, when the control signal B → LEN with H (height) level is input to the grid of built-in N transistor npn npn Tr11, with the maintenance data latching of above-mentioned the 2nd holding circuit 30B.An above-mentioned transfer circuit 41, be connected on above-mentioned latch circuit 40 and above-mentioned the 1st holding circuit 20A, when on the grid that control signal L → AEN is input to two N transistor npn npn Tr13, Tr15, the latch data of above-mentioned latch circuit 40 is sent on the 1st holding circuit 20A.And, another transfer circuit 42, be connected on the 1st holding circuit 20A and the 2nd holding circuit 30B, when on the grid that control signal A → BEN is input to two N transistor npn npn Tr17, Tr19, the maintenance data of above-mentioned the 1st holding circuit 20A be sent on the 2nd holding circuit 30B.Therefore, be formed in the switched circuit 43 that carries out the exchange of data between the 1st and the 2nd holding circuit 20A, the 30B by above-mentioned latch circuit 40 and above-mentioned two transfer circuits 41,42.
Fig. 3 shows the sequential chart that is carried out the turnaround sequence of data by above-mentioned switched circuit 43.In with figure, initial, control signal B → LEN is by activate, and thus, latch circuit 40 is with the maintenance data latching of the 2nd holding circuit 30B.Then, control signal A → BEN is by activate, and the maintenance data of the 1st holding circuit 20A are sent to the 2nd holding circuit 30B.And, after the data with the 1st holding circuit 20A were received into the 2nd holding circuit 30B, control signal A → BEN was by activate, then, control signal L → AEN is by activate, and the data of the 2nd holding circuit 30B that latchs in above-mentioned latch circuit 40 are sent to the 1st holding circuit 20A.Then, control signal B → LEN and control signal L → AEN become deactivation, have finished the exchanges data between the 1st and the 2nd holding circuit 20A, the 30B.
Here, as shown in Figures 1 and 2, because the 1st holding circuit 20A is exclusively used in the 1st functional block 2A of 1W2R basically, the 2nd holding circuit 30B is exclusively used in the 2nd functional block 2B of 1W1R basically, therefore only of the 1st functional block 2A of 1W2R being write the 21AW of Import ﹠ Export Department and two reads the 21AR1 of Import ﹠ Export Department, 21AR2 and is connected the 1st holding circuit 20A, on the other hand, only of the 2nd functional block 2B of 1W1R being write the 31BW of Import ﹠ Export Department and 1 reads the 31BR of Import ﹠ Export Department and is connected the 2nd holding circuit 30B.In the past, owing to must arrange the total import and export number (2W3R) (=5) of two functional block 2A, 2B to each holding circuit 20A, 30B, therefore in contrast to this, in the present embodiment, as whole SIC (semiconductor integrated circuit), can reduce by half importing and exporting number, can dwindle the area of register file 1 effectively.
And, for example, when own the 1st special-purpose holding circuit 20A being carried out reading/writing of data at the 1st functional block 2A, and, the 2nd functional block 2B carries out after the reading/writing of data to own the 2nd special-purpose holding circuit 30B, when being created in the necessity that necessary swap data uses between holding circuit 20A, the 30B, between the 1st and the 2nd holding circuit 20A, 30B, carry out the exchange of data by the latch circuits 40 in the above-mentioned memory cell array 5.When for example save register being arranged in the outside, through data bus register file 1 and save register are linked together when carrying out the exchange of these data, need so much swap time in cycle of the access number of register file 1, in the present embodiment, only finish with one-period.
Therefore, in the register file 1 of present embodiment, bring into play small size, and carried out the performance that data write/read at a high speed.
And, in above-mentioned Fig. 2, because latch circuit 40, as shown in Figure 2, constitute by differential circuit,, also the maintenance data of the 2nd holding circuit 30B can be latched in the latch circuit 40 preferably even therefore the 2nd holding circuit 30B moves with low supply voltage.So, the 2nd write the 31BW of Import ﹠ Export Department and read the activate rate (visiting frequency) of the 31BR of Import ﹠ Export Department when what be exclusively used in the 2nd functional block 2B even when low and the access speed of the 31BW of these Import ﹠ Export Department, 31BR when being slower than other Import ﹠ Export Department also it doesn't matter, the 2nd holding circuit 30B further can be set at low supply voltage, can further realize the low consumption electrification.
Fig. 4 shows activate rate (visiting frequency), the transistorized threshold voltage of composition of above-mentioned each 21AW of Import ﹠ Export Department, 21AR1 that writes and read, 21AR2,31BW, 31BR, each holding circuit 20A, 30B and latch circuit 40 and accepts the relation of the supply voltage of supply.
In with figure, the 1st writes and reads the 21AW of Import ﹠ Export Department, 21AR1,21AR2, the 1st holding circuit 20A the 1st group, the 2nd the 3rd group the activate rate (visiting frequency) that writes and read the 31AW of Import ﹠ Export Department, 31AR, the 2nd holding circuit 30B the 2nd group and latch circuit 40, form transistorized threshold voltage and the supply voltage accepting to supply with different.Specifically, above-mentioned the 1st group activate rate is higher than the above-mentioned the 2nd and the 3rd group, and higher activate rate is corresponding is set lowlyer with this to form transistorized threshold voltage, and simultaneously, the supply voltage of accepting to supply with is set higherly.And in minimum the 3rd group of activate rate, it is the highest to form transistorized threshold voltage, and the supply voltage of accepting to supply with is set minimumly.In mediate in the activate rate the 2nd group, the supply voltage of forming transistorized threshold voltage and accepting to supply with is set to the value between above-mentioned the 1st group and the 3rd group.
That is to say, when transistorized activate rate (visiting frequency) is higher, must be lower with this transistorized threshold voltage settings, then can reduce power consumption, and transistorized responsiveness will satisfy fixing speed under this threshold voltage if will set for to the supply voltage that this transistor provides, and then can guarantee specified action speed.As mentioned above, because in each group, according to the activate rate of oneself organizing, set the supply voltage of forming transistorized threshold voltage and accepting to supply with, therefore can reduce effectively from forming transistorized leakage current each group, realization low consumption electrification, and responsiveness can be guaranteed the regulation speed.
In addition, because the substrate of the transistorized substrate that will constitute each Import ﹠ Export Department in the memory cell array 5 and each holding circuit and other Import ﹠ Export Department and holding circuit separates, so can the individual settings threshold voltage.And,, then can further reduce power consumption effectively if constitute each Import ﹠ Export Department and holding circuit with the different transistor of threshold voltage in advance.
And, if the access speed of each Import ﹠ Export Department that writes or read because of the specialized range of its requirement not simultaneously, by between its each Import ﹠ Export Department, be generated as different transistor width in advance with forming transistorized transistor width, then can more effectively realize the low consumption electrification.
By above-mentioned with each group be total 3 underlayer voltage control circuits 13a～13c of unit setting and add up to 3 source voltage control circuit 12a～12c with above-mentioned shown in Figure 4 with each group be unit the transistorized threshold voltage of composition, and the supply voltage of accepting to supply be controlled to be above-mentioned setting value, as shown in Figure 1.
Fig. 5 shows the inner structure of above-mentioned underlayer voltage control circuit 13a.Other underlayer voltage control circuit 13b, 13b also are same structure.With the underlayer voltage control circuit 13a shown in the figure, for how changing regardless of temperature change and process, all transistorized threshold voltage is remained the circuit of setting value, its lead-out terminal BN is connected on the substrate of the N transistor npn npn that constitutes the 1st group of Import ﹠ Export Department and holding circuit.Below, the inner structure of underlayer voltage control circuit 13a shown in Figure 5 is illustrated.
In Fig. 5, underlayer voltage control circuit 13a has the N transistor npn npn Trn that the threshold voltage engine is used.This N transistor npn npn Trn be with above-mentioned register file 1 in normal memory one-element group 5a in the same manufacturing process of N transistor npn npn in make.Provide to this N transistor npn npn Trn from constant current source 80 and to decide electric current.This constant current source 80, there is not temperature dependency, for example constitute by the band-gap reference circuit of deciding current characteristics etc. is shown, this flows decides current value under the supply voltage of the N transistor npn npn in offering above-mentioned normal memory one-element group 5a and the current value that equates of the saturation current value that flows with this N transistor npn npn under the set threshold voltage of this N transistor npn npn.The N transistor npn npn Trn that above-mentioned controller is used will carry out the current-voltage conversion from the electric current of deciding of above-mentioned constant current source 80, and the voltage after its conversion (drain voltage) Vd is input to 2 imported comparing sections 81.
Above-mentioned comparing section 81, constitute by differential amplifier etc., import the voltage of transformation Vd of the N transistor npn npn Trn that uses from above-mentioned controller to an one input terminal, the controlling object of importing underlayer voltage control circuit 13a to another input terminal promptly for example constitutes the supply voltage VREF that the 1st N transistor npn npn that writes/read the 21AW of Import ﹠ Export Department, 21AR1,21AR2 and the 1st holding circuit 20A provides, this output is connected on the lead-out terminal BN by voltage limit portion 82, is connected simultaneously on the substrate of the N transistor npn npn Trn that above-mentioned controller uses.The underlayer voltage of the N transistor npn npn Trn that the above-mentioned controller of above-mentioned comparing section 81 controls is used is so that above-mentioned two input voltage Vd, VREF equate.This controlled underlayer voltage from above-mentioned lead-out terminal BN output, becomes the underlayer voltage of the N transistor npn npn that constitutes above-mentioned the 1st group Import ﹠ Export Department and holding circuit.In addition, above-mentioned voltage limit portion 82 will be capping limiting voltage VU and set lower limit limiting voltage VL from the upper limit and the lower limit of the output voltage of lead-out terminal BN.
So, in underlayer voltage control circuit 13a shown in Figure 5, under the supply voltage VREF that supplies with, in fixed value, so its result also remains on the preset threshold magnitude of voltage with the threshold voltage of the N transistor npn npn of this controlling object with the actual saturation current retentive control of the N transistor npn npn of controlling object.In addition, figure 5 illustrates the underlayer voltage retentive control of the N transistor npn npn in the normal memory one-element group 5a structure in setting value, because also is the same with the underlayer voltage retentive control of P transistor npn npn in the situation of setting value, therefore its explanation is omitted.
Source voltage control circuit 12a～12c shown in Figure 1, basically have respectively will oneself group supply voltage be controlled at the function of above-mentioned setting supply voltage value shown in Figure 4, and receive control signal, adjust the supply voltage value that generates, as shown in Figure 1 from delay voltage translation circuit 9.Delay voltage translation circuit 9 shown in Figure 1 and DLL circuit 10, when the temperature change when the above-mentioned the 1st～the 3rd respectively organizes because of use causes that action postpones to change, by in delay voltage translation circuit 9, postponing to be transformed into variation in voltage, in order to this variation in voltage is the generation supply voltage of source voltage control circuit 12a～12c of each group of control signal adjustment of content, the countermeasure that is used as making the responsiveness of each group not influenced by temperature change.
Fig. 6 shows the inner structure of DLL circuit 10 shown in Figure 1.And Fig. 8 shows the inner structure of delay voltage translation circuit 9 shown in Figure 1.The action that the DLL circuit 10 of Fig. 6 generated and read import and export, write import and export and switched circuit 43 postpones standard value.That is to say that DLL circuit 10 comprises: by the voltage control delay circuit 50 that constitutes of 4 impact damper 50a～50d of series connection; Receive the output and the regulation clock signal C L of this voltage control delay circuit 50, the comparer 51 that both are compared; With the output that receives this comparer 51, the charge pump 52 that charges to capacitor C.The charged state of above-mentioned capacitor C is fed back to above-mentioned 4 impact damper 50a～50d.And, the output signal of the original segment impact damper 50a of voltage control delay circuit 50 is exported from lead-out terminal 53a as the virtual delayed clock of reading Import ﹠ Export Department, the output signal of the 2nd segment buffer 50b is exported from lead-out terminal 53b as the virtual delayed clock that writes Import ﹠ Export Department, the output signal of the 3rd segment buffer 50c is exported from lead-out terminal 53c as virtual switching delay clock.Fig. 7 shows the relation of the clock signal of these delayed clocks and regulation.Above-mentioned 3 kinds of delayed clocks are tuned as in advance the visit budget (access budget) of register file 1.
Delay voltage translation circuit 9 shown in Figure 8 receives above-mentioned 3 kinds of delayed clocks from above-mentioned DLL circuit 10 and moves.This delay voltage translation circuit 9 is included in the virtual 9a of Import ﹠ Export Department, virtual 9b of Import ﹠ Export Department and the virtual commutation circuit 9c of writing of reading that forms in any one of virtual memory one-element group 5b～5f shown in Figure 1.These virtual Import ﹠ Export Department and commutation circuits, for the 21AW of Import ﹠ Export Department that is formed on above-mentioned normal memory one-element group 5a ... and the same structure of commutation circuit 43.And, in delay voltage translation circuit 9, comprise 3 comparer 9d～9f of total and counter 9g～9i corresponding to above-mentioned virtual Import ﹠ Export Department and commutation circuit.
And, in delay voltage translation circuit 9, in comparer 9d, will read the output signal of the 9a of Import ﹠ Export Department and compare the clock signal action of regulation virtual from the virtual delayed clock (standard delay clock) of reading Import ﹠ Export Department of above-mentioned DLL circuit 10, when virtual delay (readout time) of reading the 9a of Import ﹠ Export Department is slow, by from the output of comparer 9d with counter circuit 9g increment, adjust control signal, above-mentioned the 1st group of supply voltage value with source voltage control circuit 12a risen.Equally, the virtual output signal that writes the 9b of Import ﹠ Export Department that will receive in comparer 9e that the virtual delayed clock of reading Import ﹠ Export Department from above-mentioned DLL circuit 10 moves and compare from the virtual delayed clock (standard delay clock) that writes Import ﹠ Export Department of above-mentioned DLL circuit 10, when the virtual delay (write time) that writes the 9b of Import ﹠ Export Department is slow, by from the output of comparer 9e with counter circuit 9h increment, adjust control signal, above-mentioned the 2nd group of supply voltage value with source voltage control circuit 12b risen.And, in comparer 9f, will receive the output signal of the virtual commutation circuit 9c that the virtual delayed clock that writes Import ﹠ Export Department from above-mentioned DLL circuit 10 moves and compare from the virtual switching delay clock (standard delay clock) of above-mentioned DLL circuit 10, when the delay of virtual write circuit 9c is slow, by from the output of comparer 9f with counter circuit 9i increment, adjust control signal, above-mentioned the 3rd group of supply voltage value with source voltage control circuit 12c risen.
Therefore, if the words of the DLL circuit 10 of use Fig. 6 and the delay voltage translation circuit 9 of Fig. 8, even because above-mentioned virtual reading/action that writes the 9a of Import ﹠ Export Department, 9b and virtual commutation circuit 9c postpones to change because of temperature change, therefore also can adjust the supply voltage that is supplied to source voltage control circuit 12a～12c accordingly therewith, can not be subjected to the influence of temperature change and will normally read/write the 21AW of Import ﹠ Export Department with above-mentioned virtual circuit 9a～9c has a same delay ... and the action of commutation circuit 43 postpones roughly to remain the fixed value of regulation.
Fig. 9 shows and generates above-mentioned writing/the read 21AW of Import ﹠ Export Department, 31BR ... skeleton diagram with a plurality of transistorized arrangements of holding circuit 20A, 30B.In with figure, on N type substrate 60, form the column of transistors 61 that constitutes above-mentioned Import ﹠ Export Department and holding circuit.Use a plurality of transistors that are positioned at the end in this column of transistors 61, constitute slower Import ﹠ Export Department and the holding circuit of responsiveness, on the other hand, use the inboard a plurality of transistors that are positioned in the above-mentioned column of transistors 61, constitute responsiveness Import ﹠ Export Department and holding circuit faster.By adopting this structure, on above-mentioned N type substrate 60, at layout elements area of isolation (STI) 65 between other column of transistors 62,63 about column of transistors 61, though be subjected to the influence of this STI, the transistor deterioration degree of column of transistors 61 ends is bigger, but owing to be furnished with slower Import ﹠ Export Department of responsiveness and holding circuit, so the influence of this deterioration is less.On the other hand and since responsiveness faster Import ﹠ Export Department and holding circuit constitute by the transistor that is difficult to be subjected to the STI influence of the inboard that is positioned at column of transistors 61, therefore can guarantee its responsiveness faster preferably.
Figure 10 shows in order to use to utilize the actual result who carries out exchanges data of a plurality of virtual holding circuit in the virtual memory one-element group 5d, positively carries out the structure of exchanges data between two holding circuit 20A, the 30B in normal memory one-element group 5a.
In with figure, use the circuit 5d1, the 5d2 that are equivalent to Fig. 2 in two virtual memory one-element group 5d, and in control circuit 8, comprise the testing circuit 70 when detection must be carried out exchanges data; With the output signal that receives this testing circuit 70, the control signal generative circuit 71 of 6 kinds of control signals (exchange control signal) B → LEN_D, the B → LEN that the generation exchanges data is used, A → BEN_D, A → BEN, L → AEN_D, L → AEN.
Because above-mentioned two virtual circuit 5d1,5d2 are identical with the basic structure of Fig. 2 circuit, therefore to continue the symbol of Fig. 2 with a part, label symbol D1, D2 omit its explanation at this respectively.An above-mentioned virtual circuit 5d1 carries out the required time of exchanges data in order to detect from the 1st virtual holding circuit (the 1st virtual information holding circuit) 20AD1 to the 2nd virtual holding circuit (the 2nd virtual information holding circuit) 30BD1, and another virtual circuit 5d2 carries out the required time of exchanges data in order to detect from virtual latch circuit 40D2 to the 1st virtual holding circuit 20AD2.In the 1st virtual circuit 5d1, read the 21AR2D1 of Import ﹠ Export Department and the 2nd with the 1st and read the 31BRD1 of Import ﹠ Export Department and be connected on the control signal generative circuit 71.And in the 2nd virtual circuit 5d2, read the 21AR1D2 of Import ﹠ Export Department with the 1st and be connected on the control signal generative circuit 71.
Above-mentioned testing circuit 70, receive memory bank exchange (bank select) signal, when the memory bank in the visit switches to other memory bank, in other words, after data in should remaining on the 1st and the 2nd holding circuit 20A, 30B are held, detect the potential change of above-mentioned memory bank switching signal, judge the moment that to carry out exchanges data, detection signal is exported.
And above-mentioned control signal generative circuit 71 moves as following.That is to say, as A-stage, for example, in a virtual circuit 5d1, " 1 " data are remained among the 1st virtual holding circuit 20AD1, simultaneously " 0 " is remained among the 2nd virtual holding circuit 30BD1 and the virtual latch circuit 40D1, and in another virtual circuit 5d2, " 0 " is remained among the 1st virtual holding circuit 20AD2, simultaneously " 1 " is remained among the 2nd virtual holding circuit 30BD2 and the virtual latch circuit 40D2.
And, above-mentioned control signal generative circuit 71, after above-mentioned A-stage, receive detection signal from above-mentioned testing circuit 70, in the time of must carrying out exchanges data, above-mentioned virtual circuit 5d1 output is carried out control signal A → BEN_D that exchanges data is used from the 1st virtual holding circuit 20AD1 to the 2nd virtual holding circuit 30BD1, and the normal circuit output of Fig. 2 is carried out control signal A → BEN that exchanges data is used from the 1st holding circuit 20A to the 2nd holding circuit 30B every the time of last defined.Then, in the 2nd virtual holding circuit 30BD1 with exchanges data to the virtual circuit 5d1 of the 1st virtual holding circuit 20AD1, after reading that the 31BRD1 of Import ﹠ Export Department is actual and reading these data " 1 ", allow above-mentioned two control signal A → BEN_D every the time of last defined, the output of A → BEN stops, meanwhile, this time, output is carried out control signal L → AEN_D that exchanges data is used from virtual latch circuit 40D2 to the 1st virtual holding circuit 20AD2 to another virtual circuit 5d2, and, the normal circuit output of Fig. 2 is carried out control signal L → AEN that exchanges data is used from latch circuit 40 to the 1st holding circuit 20A every the time of last defined.
Then, control signal generative circuit 71, in another virtual circuit 5d2, the data " 1 " of virtual latch circuit 40D2 are sent to the 1st virtual holding circuit 20AD2, after reading the 21ARD2 of Import ﹠ Export Department and reading, the output every time of last defined with above-mentioned two control signal L → AEN_D, L → AEN stops.
Because by testing circuit 70 and control signal generative circuit 71 in the above-mentioned control circuit 8 of interior plant, the actual exchange of carrying out data in virtual circuit 5d1,5d2, the result who reflects its actual swap time, in normal circuit shown in Figure 2, carry out two exchanges data between holding circuit 20A, the 30B, therefore can in this normal circuit, positively carry out exchanges data, and, can after data exchanging completed, stop the output of above-mentioned control signal B → LEN, A → BEN, L → AEN.
(using the malformation example of virtual holding circuit control data exchange)
Figure 11 shows after the action of the data that constitute the readout register file, detect the end that in virtual circuit, writes, when finishing the circuit of two exchanges data between the memory cell, the variation of the circuit of 6 kinds of control signals (exchange control signal) B → LEN_D, the B → LEN that the generation exchanges data is used, A → BEN_D, A → BEN, L → AEN_D, L → AEN is equivalent to the circuit 5d1, the 5d2 that are equivalent to Fig. 2 and control signal generative circuit 71 in the virtual memory one-element group 5d shown in Figure 10.
Circuit shown in Figure 11 is the same with described in the explanation of Figure 10 also, uses two virtual circuit Rep1, Rep2.In above-mentioned Figure 10, write the data of bit line for exchange, write to finish in the import and export at one and write, return the structure of A-stage, and in virtual circuit Rep1, Rep2 shown in Figure 11, be set at set potential for being connected two bit lines that write import and export in advance, utilize write control signal WWL and energizing signal/WWL thereof, detect finishing of writing, the information of holding circuit is turned back to the structure of A-stage.In addition, simply represent with the switch mark, in fact form, and control the ON/OFF of MOS transistor by near the control signal the record in the drawings by MOS transistor though be labeled in the symbol 11A of Figure 11.
Figure 12 shows the sequential chart of each node of above-mentioned Figure 11.Utilize this Figure 12 that circuit structure and the action of Figure 11 further are illustrated.
After the clock signal clk of register file rose, the control signal RWL that reads import and export of register file was by activate, and the node DW of dynamic circuit DC1 (circuit that is equivalent to the control signal generative circuit 71 among Figure 10) is by precharge.Then, after reading control signal RWL and becoming deactivation, the energizing signal of write control signal WWL and exchange control signal B → L is by activateization, and the node DBA of dynamic circuit DC3 is by precharge.Because the activateization of above-mentioned write control signal WWL, the node DW discharge of dynamic circuit DC1, the energizing signal of above-mentioned write control signal WWL and exchange control signal B → L becomes deactivation, and A → B is by activateization for the exchange control signal, and the node DCB of dynamic circuit DC2 is by precharge.And, the node DBA of dynamic circuit DC3 is discharged because of the activateization of above-mentioned exchange control signal A → B, then, become deactivation at above-mentioned exchange control signal A → B, exchange control signal L → a-signal is by after the activateization, the node DCB of dynamic circuit DC2 is discharged, and exchange control signal L → A becomes deactivation, has finished to write the message exchange action that detects action and two holding circuits.
Because above-mentioned circuit shown in Figure 11 needn't change writing bit line having how there is favourable point in writing when importing and exporting of import and export, therefore can small sizeization.In addition, in the sequential chart of Figure 12, though in the one-period of clock signal clk, finished and read (Read), write (Write), exchange (Copy) action, but much less also can in the one-period of clock signal, finish and read (Read), write (Write), in the 2nd cycle, finish exchange (Copy) action.At this moment, though, in the application examples of multithreading type processor described later, the deterioration on some performances is only arranged for one-period has taken place in the delay of switching motion.
(other example of supply voltage control)
Figure 13 shows other control example of activate rate (visiting frequency), threshold voltage and the supply voltage of Import ﹠ Export Department shown in Figure 4, holding circuit and latch circuit.In Figure 13, show when register file when the switched circuit (latch circuit) of swap data constitutes by the memory cell MCB of memory cell MCA, the 1R1W of 7R5W with between these two memory cell MCA, MCB, the access speed that makes each memory cell MCA, MCB is regularly a control example almost.Threshold voltage among the figure, supply voltage are illustrated in does not have deviation in the manufacturing process, the desired value when temperature conditions is best.
Usually, in the register file, even in each import and export, activate rate (visiting frequency) also will be controlled to be the access speed of each import and export necessarily, not simultaneously to satisfy the specialized range of its action.When the switched circuit that has added to feature structure key element of the present invention, also make this switched circuit be almost certain access speed.Generally, after the threshold voltage of MOS transistor being raise according to the activate rate in order to cut down power consumption, its access speed is slack-off.Therefore, in order to compensate its access speed, and set supply voltage higher.In above-mentioned Fig. 4 since with low power consumption as fundamental purpose, so the activate rate is low more, just supply voltage is set low more, but after being almost certain access speed, is necessary to set supply voltage high more when visiting frequency is low more.But, even also can further realize the low consumption electrification this moment.This is because for example consider with the CMOS transistor of 90nm, if threshold voltage is than the high approximately words of 200mV of 200mV, then leakage current can be cut to below 1/1000 or 1/1000, on the other hand, when supply voltage is 0.8V and during 1V, because the ratio of leakage current only has 1/4 difference, therefore as a whole, compare with being set at low threshold voltage, leakage current can be cut down 1/250.In Figure 13, the threshold voltage with switched circuit is set at the reason identical with the value of a memory cell MCB with supply voltage value is illustrated afterwards.
Figure 14 (a) shows according to various settings such as activate rate shown in Figure 13 and threshold voltages, and in order to cut down the area of memory cell MCA, MCB, and the deviation of manufacturing process and temperature deviation are sought the threshold voltage circuit diagram during appropriateization.
In Figure 14 (a), with the memory cell MCB of memory cell MCA, the 1R/1W of 7R/5W, the transistorized threshold voltage settings of PMOS of respectively forming of switched circuit (latch circuit) L1 is common, in order only to make its threshold voltage of respectively forming nmos pass transistor different between two memory cell MCA, MCB, in each manufacturing processes, it is fabricated to low threshold voltage and high threshold voltage in advance.The concentration that can be by making each tie point or the material and the thickness of gate oxidation mould change, and come set threshold voltage.
And, provide underlayer voltage from underlayer voltage generative circuit (not illustrating the figure) to the substrate of the composition nmos pass transistor of memory cell MCA, MCB and switched circuit L1, this underlayer voltage is no matter temperature deviation and manufacture process deviation how, all can be set at certain value with the threshold voltage vt of nmos pass transistor.Figure 14 (b) shows the section of the physical arrangement of this moment.
In Figure 14 (b), in the figure of the low threshold voltage LVt that memory cell MCA has in the nmos pass transistor of left end, and for example with shown in figure (d) and the figure (f), from the underlayer voltage generative circuit underlayer voltage VBN is offered PWELL, in the figure of the high threshold HVt that memory cell MCB and switched circuit L1 have in the nmos pass transistor of right-hand member, shown in figure (c) and figure (e), the underlayer voltage of VBNC is offered PWELL1 from the underlayer voltage generative circuit.In the PMOS transistor of Figure 14 (b) central authorities, VBP offers NWELL with underlayer voltage.So, though the activate rate have because of each circuit is different to a certain degree not simultaneously, also can be by considering layout physically, threshold voltage and supply voltage is total, seek small sizeization.That is to say, though the activate rate of memory cell MCB and switched circuit L1 is different, but since common on all enough low point of any one activate rate, therefore make threshold voltage and supply voltage common, will be suppressed at Min. because of the area increase that substrate separately causes.
And,, also can seek small sizeization by making threshold voltage and supply voltage common for the PMOS transistor.This is because the hypothesis pair pmos transistor, difference set threshold voltage between visiting frequency different two kinds of memory cell MCA, MCB, provide respectively can under the situation that is not subjected to temperature deviation and process deviation effects, set the supply voltage of certain threshold voltage vt the time to the transistorized substrate of each PMOS from the underlayer voltage generative circuit, also can produce the necessity that the transistorized NWELL of PMOS is set respectively.In the separation width of NWELL and separating in the width of PWELL, general bigger as the separation width of common trap with darker trap.Therefore, at this moment, be that (overhead) is heavier for the expense of house-keeping because NWELL is separated and compare when PWELL is separated.For example, when being in 90nmCMOS, be respectively 2 μ m and 1 μ m.
And, in Figure 14 (a), set the supply voltage of memory cell MCB to such an extent that be higher than the voltage of memory cell MCA, the supply voltage of switched circuit L1 is set at the magnitude of voltage identical with the supply voltage of memory cell MCB.Structure by this, by at first data being input to switched circuit L1 from a memory cell MCB, secondly, data are input to an above-mentioned memory cell MCB from another memory cell MCA, at last, data are input to above-mentioned another memory cell MCA from switched circuit L1, constitute the structure of carrying out exchanges data.So, has the effect that suppresses to run through electric current.Below, its reason is described in detail.
Suppose, be lower than the supply voltage of switched circuit L1 when the supply voltage that writes import and export of memory cell MCB, when the node of the tie point that writes import and export and holding circuit of memory cell MCB was Hi (height), the magnitude of voltage of this node equated with the supply voltage of switched circuit L1.But because the supply voltage that writes import and export of memory cell MCB is a low-voltage, voltage that therefore might above-mentioned node becomes and is higher than the supply voltage that writes import and export of memory cell MCB.So, even be connected the current potential of this bit line that writes import and export when being L (low), also form the transistorized grid voltage of PMOS, import and export and the supply voltage of the connected node of holding circuit hangs down the so much possibility of the transistorized threshold voltage of PMOS than writing of memory cell MCB by what form the transmission gate that writes import and export.So, the composition PMOS transistor that forms the transmission gate write import and export becomes the ON state.That is to say have perforation electric current to flow to the possibility that writes bit line from the connected node that writes import and export and holding circuit of memory cell MCB.But, if as the structure of Figure 14 (a), the supply voltage of memory cell MCB is set at the words more than the supply voltage of the supply voltage of switched circuit L1 or switched circuit L1, the transistorized grid voltage of composition PMOS that then forms the transmission gate write import and export is not is not imported and exported than writing of memory cell MCB and the low so much phenomenon of the transistorized threshold voltage of PMOS of supply voltage of the connected node of holding circuit, does not run through the mobile phenomenon of electric current.
Secondly, figure 15 illustrates the physical layout figure of the register file when use has utilized the supply circuit of the supply circuit of underlayer voltage of memory cell of Figure 14 and supply voltage.This register file is read action and is finished the write activity of reading after the action in one-period, then, carry out switching motion between a memory cell MCA and another memory cell MCB.Comparer 15D, 15E shown in Figure 15 and counter 15B, 15C are equivalent to the delay voltage translation circuit 9 among Fig. 1, and Figure 16 shows the structure that they and virtual memory unit 1J are lumped together.In addition, in Figure 15, no matter power control circuit B1L, C1M and substrate generative circuit B1P, C1P be in the inside or the outside of register file, and the loss of power supply voltage supplying is nearly all not too become.Therefore, when same supply voltage is provided to other SIC (semiconductor integrated circuit) piece, total these power control circuits in the outside of register file, when not being arranged in the outside, when being arranged in register inside,, therefore can effectively save area because burden such as the area of wiring lead etc. is less.
With reference to Figure 16 the details of this routine Control of Voltage structure further is illustrated.In delay voltage translation circuit 16A shown in Figure 16, MCB virtual circuit (the 1st virtual circuit) 16C and MCA virtual circuit (the 2nd virtual circuit) 16B are positioned at the virtual memory one-element group 1J of Figure 15.In MCA virtual circuit 16B, exist to detect from the data of memory cell MCA read read testing circuit 90, detect write write testing circuit 91 and exchange testing circuit 16D.The above-mentioned testing circuit 90 of reading, input clock signal moves, write testing circuit 91, input is moved from the above-mentioned detection signal of reading of reading testing circuit 90 outputs, exchange testing circuit 16D, input is moved from the above-mentioned detection signal that writes that writes testing circuit 91 outputs.Above-mentionedly read testing circuit 90, write testing circuit 91, the circuit structure of the basic structure of exchange testing circuit 16D and above-mentioned Figure 10 and Figure 11 is similar, constitute by virtual memory unit and dynamic circuit.This pedestrian can design according to Figure 10 and Figure 11.
Because above-mentioned MCA virtual circuit 16B constitutes therefore same nmos pass transistor design with low threshold voltage LVt by the writing Import ﹠ Export Department, read Import ﹠ Export Department of memory cell MCA, any one of holding circuit, the nmos pass transistor of low threshold voltage LVt.Testing circuit 16D is the same with switched circuit (latch circuit) shown in Figure 13 in exchange, is made of the nmos pass transistor of high threshold voltage HVt.
Therefore, MCA virtual circuit 16B finishing after clock signal being input to sense data the storer of reading testing circuit 90, writing a succession of processing of data, swap data to storer, exports output signal.Comparer 15D will be from the output delay of output signal phase place of this MCA virtual circuit 16B with for the standard time clock of the Action clock of register file compares, and its result is outputed to counter circuit 15B.Counter circuit 15B, increment when the output delay of output signal from exchange testing circuit 16D is slower than standard time clock is in the output delay of output signal of exchange testing circuit 16D decrement during faster than standard time clock.The counter result of above-mentioned counter circuit 15B is outputed to power control circuit (supply voltage is adjusted circuit and power supply voltage supplying circuit) C1M.This power control circuit C1M carries out rising supply voltage when increment, reduces the action of supply voltage when decrement.The basic structure of another MCB virtual circuit 16C and action are the same with above-mentioned MCA virtual circuit 16B, all are made of high threshold voltage HVt but read testing circuit 92 and write testing circuit 93.
Figure 17 shows the sequential chart of the circuit of above-mentioned Figure 16.With these Figure 15～Figure 17 action is illustrated.
No matter figure 17 illustrates is MCA virtual circuit 16B at first, or any one of MCB virtual circuit 16C, and supply line voltage is all inappropriate, and is lower.At first, in comparer 15E the output delay of output signal of MCB virtual circuit 16C and the cycle of standard time clock are compared, consequently the supply voltage of MCB virtual circuit 16C being set at is 1.0V at the most appropriate supply voltage of one-period.Since the 2nd cycle, comparer 15E is provided as synchronous output signal, and supply voltage is remained on 1.0V.By set with the corresponding supply voltage of high threshold voltage HVt of MOS transistor (=1.0V), the supply voltage of exchange testing circuit 16D among the MCA virtual circuit 16B is defined as 1.0V, under this state, be set at same-phase by delay and standard clock signal with MCA virtual circuit 16B, it is the 0.8V of the most appropriate supply voltage that the supply voltage of MCA virtual circuit 16B also is set at.Owing to being same-phase, therefore supply voltage value is remained on 0.8V since the 3rd cycle.
As mentioned above, at the circuit of the MOS transistor that will use high threshold voltage HVt with used the circuit of the MOS transistor of low threshold voltage LVt to mix in the path that is loaded in together, the supply voltage of the circuit of high threshold voltage HVt is different with the supply voltage of the circuit of low threshold voltage LVt, in the mode that this most appropriate supply voltage is provided, the circuit of Figure 16 is effective structure.That is to say, in Figure 16, delay and defined length of delay by the circuit that more only constitutes by the MOS transistor of a threshold voltage with regulation, determine the supply voltage of its circuit at first, then, by determining its supply voltage, decide another circuit that mix to carry, i.e. the supply voltage value of the circuit that constitutes by other the MOS transistor of threshold voltage with regulation.
If in all paths, mix the circuit that carries the different MOS transistor of a plurality of threshold voltages, then, any one circuit all be can not determine supply voltage, so feedback circuit (feedback loop) do not assembled owing to there are two underranges.But, as shown in this example, by using the path that constitutes by a plurality of MOS transistor with single threshold voltage, at first, decision has the supply voltage of circuit of MOS transistor of the threshold voltage of regulation, re-use the supply voltage that this is determined, decide the supply voltage of the circuit that contains MOS transistor, can make the feedback circuit convergence with other threshold voltage.And, to compare with the circuit mode of above-mentioned Fig. 8, the manner does not need DLL circuit etc., can further realize small size.
In addition, this example shows the example that pair nmos transistor only mixes the circuit that has carried the different MOS transistor of threshold voltage, even but pair pmos transistor mixes and carries the circuit that is made of the different a plurality of MOS transistor of threshold voltage, and also be the same.And, even when mix carrying the different a plurality of MOS transistor of 3 kinds of threshold voltages, as long as generate by circuit that has circuit that a kind of a plurality of MOS transistor constitutes, is made of a plurality of MOS transistor with two kinds of threshold voltages and the circuit that is made of a plurality of MOS transistor with 3 kinds of threshold voltages, needless to say mode that also can enough example determines supply voltage value.
(other variation of memory cell)
Figure 18 shows other variation of the memory cell of register file.
Write the 31BW of Import ﹠ Export Department, transfer circuit the 42, the 2nd holding circuit 30B and the 2nd structure of reading the 31BR of Import ﹠ Export Department with illustrating and combine the 2nd among Fig. 2, perhaps, combine the 1st and write the memory cell that the 21AW of Import ﹠ Export Department, transfer circuit the 41, the 1st holding circuit 20A and the 1st read the corresponding 1R/1W of structure of the 21AR2 of Import ﹠ Export Department.
In with figure, write and import and export AW, write to become when word line WL2 is Hi (height) at data 2A and do not preserve (desave) state, can not write data.The 2nd phase inverter 18B among among the holding circuit 2B the 1st and the 2nd phase inverter 18A, the 18B is made of a PMOS transistor 94 and two nmos pass transistor 18C, 18d.The drain electrode of 2NMOS transistor 18c is connected on the source electrode of 1NMOS transistor 18d, the grid of 2NMOS transistor 18c is connected data 2A writes on the word line WL2.And, the source electrode of above-mentioned 2NMOS transistor 18c is connected roll data 2A writes in the output of converter circuit INV8 of word line WL2.Below, the action of this circuit is illustrated.
In the memory cell of the register file of above-mentioned Fig. 2, when when writing bit line and write Hi (height), the grid of the nmos pass transistor of the phase inverter I2 in the 1st holding circuit or the 2nd holding circuit is long, is determined by the transistorized current capacity of PMOS that becomes the transistorized current capacity of a pair of PMOS and be connected in the write circuit of bit line.That is to say that the current capacity of the nmos pass transistor of phase inverter I2 must be that the transistorized driving force of PMOS of Hi is little a lot of than making holding circuit.Generally wish the memory cell small sizeization of these register files, use the size of the minimum transistor width that approaches each process MOS transistor from generation to generation.Also require nmos pass transistor and the transistorized minimum transistor width of PMOS of phase inverter I2.For when using the minimum transistor width, satisfy the restriction of this driving force, be next corresponding by the grid length of lengthening nmos pass transistor in the past.For example, in supply voltage 0.8V, satisfy the transistor size of the restriction of this driving force, be that the 90nm process is during the generation, when the transistorized transistor width of the PMOS that makes phase inverter I2 is 0.3 μ m, when grid length was 0.1 μ m, the transistor width that must make the nmos pass transistor of phase inverter I2 was 0.3 μ m, and grid length is 1 μ m.
But in the generation, the limitation owing to photoetching can only form the MOS transistor about the twice that grid length is minimum grid length in the 65nm process.Though by the nmos pass transistor of 0.1 μ m grid length is connected 10 sections, can form the transistor that is equivalent to 1 μ m, in this structure, the area burden becomes too big.This is because when a plurality of MOS transistor series connection were formed, the range of scatter that must make this series connection zone was about twice of minimum grid length (be 0.1 μ m this moment).That is to say that this is because when for 10 sections serial transistors, at the range of scatter that needs on the transistorized grid length direction about 0.1*2*9=1.8 μ m, with constitute by the nmos pass transistor that is 1 μ m at 1 section grid length in compare and become quite big.
In order to address this problem, this case inventor studies the such memory cell of above-mentioned Figure 18.In with figure, because when data 2A write word line WL2 and is Hi (height), nmos pass transistor 18c was ON (a leading to) state, so phase inverter 18B brings into play the function of general paraphase logical circuit.On the other hand, because when data 2A write word line and is L (low), nmos pass transistor 18c was disconnected, so can make the driving force of nmos pass transistor 18c lower, can write Hi to holding circuit 2B at an easy rate.Structure even in manufacture process from now on, also can realize can not producing the memory cell of useless area burden by this.
And the feature of memory cell shown in Figure 180 also is: be not directly with the source ground of nmos pass transistor 18c, write in the output of phase inverter INV8 of word line WL2 but be connected data 2A.
Suppose, the phase inverter INV8 that data 2A writes word line WL2 is made of transducer, because the nmos pass transistor 18d of phase inverter 18B and the output node between the PMOS transistor 94 are via nmos pass transistor 18d, 18c, be the interior nmos pass transistor ground connection of phase inverter INV8 that data 2A writes word line WL2 then, so these nmos pass transistors become the circuit structure of 3 sections series connection.Influence because of DIBL (Drain Induced Barrier Lower), source drain voltage is low more can cut down leakage current more, in one section nmos pass transistor and two sections series connection nmos pass transistor, the ratio of leakage current is 1: 1/4, becomes 1: 1/10 in 3 sections series connection nmos pass transistors.Therefore, and the directly grounded situation of the source electrode of nmos pass transistor 18c is compared, leakage current can be reduced about 6 one-tenth.
And, owing to needn't reset nmos pass transistor, but connect with the nmos pass transistor in the transducer INV8 of original existence, therefore there is not the phenomenon of area increase yet.In addition, needing not to be converter circuit though data 2A writes the phase inverter INV8 of word line WL2, also can be other circuit, and the series connection hop count of the nmos pass transistor that ground connection connects is many more, can cut down leakage current more.
In addition, the frequency that is output as L as phase inverter 18A is more than for the frequency of H the time, preferably the source electrode of nmos pass transistor 18d is connected the outgoing side of converter circuit INV8, connect the drain electrode of nmos pass transistor 18d and the source electrode of nmos pass transistor 18c, the drain electrode of nmos pass transistor 18c is connected the input side of phase inverter 18A.So, can cut down grid leakage current further, and, read the discharge time of importing and exporting AR owing to can cut down, therefore can reduce power consumption.
Figure 19 is the figure of variation that shows other memory cell of register file, shows the memory cell of 3W/1R.
The 2nd phase inverter 19B among the holding circuit 2B, by 1 PMOS transistor 95,1 1NMOS transistor 19c and 3 2NMOS transistor 19d, 19e, 19f of connecting between this transistor 95 and the grid constitute.The grid of above-mentioned 3 nmos pass transistor 19d, 19e, 19f is connected corresponding 3 writes respectively the writing on word line WL2, WL3, the WL4 of import and export.In phase inverter 19B, because when 3 data write word line WL2～WL4 and are Hi (height), all nmos pass transistor 19c, 19d, 19e, 19f were on-state, so phase inverter 19B brings into play the effect of general paraphase logical circuit with figure.On the other hand, when any one data 2A write word line and is L, corresponding nmos pass transistor 19c, 19d, 19e, 19f disconnected, and therefore can at an easy rate Hi be write holding circuit 2B.
And, be connected 1NMOS transistor 19c 2NMOS transistor farthest apart from the 2nd phase inverter 19B, it is the highest promptly to write the activate rate of word line WL4 apart from the data 2C of the nearest 2NMOS transistor 19f of ground connection, with other 2NMOS transistor 19e, 19d be linked in sequence them, make the activate rate more and more lower.Structure is cut down grid leakage current by this.This is because to write word line at any one be L, and when other write word line and is Hi, the result that the source drain voltage of 2NMOS transistor 19f, 19e, 19d is compared was that the source drain voltage of nmos pass transistor 19f is minimum.Because the exponential constant of the source drain voltage of grid leakage current and MOS transistor is proportional, therefore by on the grid that writes the nmos pass transistor 19f that approaches ground connection most in 4 nmos pass transistors that word line is connected phase inverter 19B that the activate rate is the highest, can cut down grid leakage current.
In addition, the frequency that is output as L as phase inverter 19A is more than for the frequency of H the time, preferably the drain electrode of nmos pass transistor 19d is connected the input of phase inverter 19A, the drain electrode of nmos pass transistor 19c is connected the source electrode of nmos pass transistor 19f, make the source ground of nmos pass transistor 19c.So, can cut down grid leakage current further, and, read the discharge time of importing and exporting AR owing to can cut down, therefore can reduce power consumption.
(application examples)
Figure 20 (a) shows the concrete application examples of Fig. 1.
In with figure, 100 is multithreading type processor, switches a plurality of threads.After switch threads, generation will be preserved context (context) necessity of involution in the storer.1 is register file of the present invention also shown in Figure 1, and 1a is that the register that involution is used preserved in context, and structure is the 2nd holding circuit 30B that comprises a plurality of Fig. 2.1b is the general register that above-mentioned processor 100 uses when it is carried out, and structure is the 1st holding circuit 20A that comprises a plurality of Fig. 2.103 is arithmetical unit, is the concrete application examples of the functional block 2A of Fig. 2.107 is data bus, 106 for being connected the external memory storage of the outside of processor 100 by data bus 107,104 for both being saved in context the external memory storage 106 from above-mentioned register 1a, make the conveyer of context again, be the concrete application examples of the functional block 2A of Fig. 2 from external memory storage 106 involutions to register 1a.105 is the cache of taking in the data of external memory storage 106,101 control parts for control above-mentioned conveyer 104, register file 1 and arithmetical unit 103.
The figure on opportunity of the action of Figure 20 (b) when showing the thread of switch handler 100.Here, be the boundary with moment T, thread switches to thread B from thread A.After near moment T, the contextual involution of beginning thread B.The part of representing with the oblique line that is tilted to the right shows contextual involution, utilize cache store dash 105 and external memory storage 106 between do not carry out the time that data transmit, with context from external memory storage 106 involutions to register 1a.In processor 100 execution thread A, prepare the context of thread B.And, after becoming moment T, use the function of register file of the present invention, the content of the content of exchange register 1a and register 1b.By doing like this, make the context of thread A switch to the context of thread B.
Then, after moment T, carry out the contextual preservation of thread A.The part of representing with the oblique line that is tilted to the left shows contextual preservation, utilize cache store dash 105 and external memory storage 106 between do not carry out the time that data transmit, context is saved in the external memory storage 106 from register 1a.In processor 100 execution thread B, the context of thread A is saved in the external memory storage 106.
In above-mentioned processor 100, preserve the contextual loss of involution in order to cover, register 1 also comprises the register 1a that context preservation involution is used except the general register 1b that comprises processor 100 and use when it is carried out.Structure by this can be prepared the context of thread B in the execution of thread A, can be at moment T switch to thread B in a flash.Therefore, though the register of the capacity at double of the register 1b that necessary actual installation was used when carrying out, the register file of the application of the invention can be realized small size, low power consumption and high speed motion.
Figure 21 shows the variation of multithreading type processor.In with figure, 400 is multithreading type processor, switches a plurality of threads.In above-mentioned processor shown in Figure 20 100, with arithmetical unit 103 double as load memory and arithmetic operator, in this routine processor 400, actual installation has 408,409,410 and load memory devices 403 of 3 arithmetical unit.And it is 1 that arithmetical unit 408,409,410 writing separately imported and exported number, and reading and importing and exporting number is 2, and it is 2 that the writing of load memory device 403 imported and exported number, and reading and importing and exporting number is 1.And, 407 is data bus, 406 for being connected the external memory storage of processor 400 outsides by data bus 407,404 for the register 501a that both the context preservation involution of context in register file 501 is used is saved in the external memory storage 406, makes the conveyer of context from external memory storage 406 involutions to above-mentioned register 501a again.405 is the cache of taking in the data of external memory storage 406, and 401 are the above-mentioned conveyer 404 of control, register file 501, the control part of arithmetical unit 408,409,410 and load memory device 403.
In the processor 400 of said structure, the opportunity of the action the during switch threads that illustrates, figure was the same with above-mentioned Figure 20 (b).
In above-mentioned processor 400, preserve the contextual loss of involution in order to cover, the general register 501b that register file 501 uses when comprising the execution of processor 400, comprise that also context preserves the register 501a that involution is used.Therefore, though the register of the capacity at double of the register 501b that necessary actual installation was used when carrying out, the register file of the application of the invention can be realized small size, low power consumption and high speed motion.Particularly in this variation that the import and export number of register 501a and register 501b differs widely, its effect is greater than Figure 20 the time.
(practicality)
As mentioned above, the present invention is compared with the past, and can effectively reduce by a memory cell institute must Must the import and export number, simultaneously, many import and export of finishing in the short time as the access time with data The semiconductor integrated circuit of type register file is very useful, is applicable to have comprised this semiconductor integrated electric The portable phone on road, IC-card chip or placed type electric product.

Claims (36)

1, a kind of SIC (semiconductor integrated circuit) is characterized in that:
Comprise: the 1st and the 2nd information holding circuit, be formed on memory cell array, information is kept;
The 1st Import ﹠ Export Department only is connected on above-mentioned the 1st information holding circuit, is used for information and inputs or outputs;
The 2nd Import ﹠ Export Department only is connected on above-mentioned the 2nd information holding circuit, is used for information and inputs or outputs; And
Switched circuit receives the exchange control signal, intercourses information that remains in above-mentioned the 1st information holding circuit and the information that remains in above-mentioned the 2nd information holding circuit in above-mentioned memory cell array.
2, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd Import ﹠ Export Department is made of transistor circuit respectively;
The above-mentioned the 1st and the transistor circuit of the 2nd Import ﹠ Export Department, the transistor that is differed from one another by threshold voltage constitutes.
3, SIC (semiconductor integrated circuit) according to claim 2 is characterized in that:
In the above-mentioned the 1st and the 2nd Import ﹠ Export Department, under the situation that visiting frequency differs from one another;
Constitute the transistorized threshold voltage of the higher Import ﹠ Export Department of visiting frequency, be lower than the transistorized threshold voltage that constitutes the lower Import ﹠ Export Department of visiting frequency.
4, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd Import ﹠ Export Department, the supply voltage of accepting to supply with differs from one another.
5, SIC (semiconductor integrated circuit) according to claim 4 is characterized in that:
The supply voltage of the Import ﹠ Export Department that visiting frequency is lower is lower than the supply voltage of the higher Import ﹠ Export Department of visiting frequency.
6, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd information holding circuit is made of transistor circuit respectively;
The above-mentioned the 1st and the transistor circuit of the 2nd information holding circuit, the transistor that is differed from one another by threshold voltage constitutes.
7, SIC (semiconductor integrated circuit) according to claim 6 is characterized in that:
Constitute the transistorized threshold voltage of the higher information holding circuit of visiting frequency, be lower than the transistorized threshold voltage that constitutes the lower information holding circuit of visiting frequency.
8, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd information holding circuit, the supply voltage of accepting to supply with differs from one another.
9, SIC (semiconductor integrated circuit) according to claim 8 is characterized in that:
The supply voltage of the information holding circuit that visiting frequency is lower is lower than the supply voltage of the higher information holding circuit of visiting frequency.
10, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
Above-mentioned switched circuit has the temporary transient temporary transient holding circuit of getting up that keeps of information;
The information that keeps in the above-mentioned the 1st and the 2nd information holding circuit according to above-mentioned exchange control signal, exchanges mutually by above-mentioned temporary transient holding circuit.
11, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
Detect the exchange that the information in the above-mentioned the 1st and the 2nd information holding circuit that will remain on exchanges mutually and stop action, the output of above-mentioned exchange control signal is stopped when stopping detecting this exchange.
12, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The state-detection that the information in the above-mentioned the 1st and the 2nd information holding circuit that should remain on has been maintained in these the 1st and the 2nd information holding circuits is come out, and after detecting, the information that remains in the above-mentioned the 1st and the 2nd information holding circuit is exchanged mutually.
13, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd Import ﹠ Export Department is made of transistor circuit respectively;
The above-mentioned the 1st and the transistor circuit of the 2nd Import ﹠ Export Department, constitute by the transistor of access speed corresponding crystal pipe width of Import ﹠ Export Department respectively with oneself;
The transistor width of the transistor circuit of the Import ﹠ Export Department that access speed is slower is narrower than the access speed transistor width of the transistor circuit of Import ﹠ Export Department faster.
14, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd information holding circuit is made of transistor circuit respectively;
The above-mentioned the 1st and the transistor circuit of the 2nd information holding circuit, respectively by with the information holding circuit that is connected oneself on the transistor of access speed corresponding crystal pipe width of Import ﹠ Export Department constitute;
The transistor width of the transistor circuit of the information holding circuit that access speed is slower is narrower than the access speed transistor width of the transistor circuit of information holding circuit faster.
15, SIC (semiconductor integrated circuit) according to claim 10 is characterized in that:
Above-mentioned temporary transient holding circuit is made of latch circuit.
16, SIC (semiconductor integrated circuit) according to claim 15 is characterized in that:
Above-mentioned latch circuit is differential circuit.
17, SIC (semiconductor integrated circuit) according to claim 8 is characterized in that:
Above-mentioned switched circuit comprises: latch circuit, with temporary transient maintenance of information that remains in the lower information holding circuit of supply voltage, and the information that will keep outputs in the higher information holding circuit of supply voltage.
18, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are made of transistor circuit respectively;
Group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and the group that is made of above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit have the underlayer voltage control circuit respectively;
Above-mentioned underlayer voltage control circuit, the transistorized threshold voltage that will constitute the Import ﹠ Export Department of oneself group and each transistor circuit of information holding circuit respectively is controlled to be the corresponding threshold voltage of visiting frequency with the own Import ﹠ Export Department that organizes.
19, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
Group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and the group that is made of above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit have source voltage control circuit respectively;
Above-mentioned source voltage control circuit respectively according to information readout time and write time in the oneself Import ﹠ Export Department, is controlled Import ﹠ Export Department and the supply voltage that provides of information holding circuit to oneself.
20, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are made of transistor circuit respectively;
Group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and the group that is made of above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit have underlayer voltage control circuit and source voltage control circuit respectively;
Above-mentioned underlayer voltage control circuit, the transistorized threshold voltage that will constitute the Import ﹠ Export Department of oneself group and each transistor circuit of information holding circuit respectively is controlled to be the threshold voltage of defined;
Above-mentioned source voltage control circuit is provided respectively by Import ﹠ Export Department and the supply voltage that provides of information holding circuit to oneself, makes the time that information readout time in oneself the Import ﹠ Export Department and write time be respectively setting.
21, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are formed on the transistor that a plurality of transistors are arranged in juxtaposition portion arranged side by side;
Import ﹠ Export Department that responsiveness is slower and information holding circuit are positioned at the end of above-mentioned transistor portion arranged side by side;
Responsiveness is Import ﹠ Export Department and information holding circuit faster, is positioned at the inboard of above-mentioned transistor portion arranged side by side.
22, SIC (semiconductor integrated circuit) according to claim 11 is characterized in that:
Comprise: the 1st and the 2nd virtual information holding circuit, be formed on formed the above-mentioned the 1st and the cell array of the 2nd information holding circuit in;
Above-mentioned exchange control signal reflects the mutual switching time that exchanges of information reality that will remain in the above-mentioned the 1st and the 2nd virtual information holding circuit, is exporting through stopping after this switching time.
23, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The substrate that has formed above-mentioned the 1st Import ﹠ Export Department is separated with the substrate that has formed above-mentioned the 2nd Import ﹠ Export Department.
24, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The substrate that has formed above-mentioned the 1st information holding circuit is separated with the substrate that has formed above-mentioned the 2nd information holding circuit.
25, SIC (semiconductor integrated circuit) according to claim 10 is characterized in that:
Above-mentioned temporary transient holding circuit, constitute by transistor circuit, if and the visiting frequency of above-mentioned switch-over control signal is higher than the above-mentioned the 1st or the visiting frequency of the 2nd information holding circuit, the transistorized threshold voltage that then constitutes above-mentioned temporary transient holding circuit is lower than the transistorized threshold voltage that constitutes the above-mentioned the 1st or the 2nd information holding circuit.
26, SIC (semiconductor integrated circuit) according to claim 10 is characterized in that:
Above-mentioned temporary transient holding circuit is set at visiting frequency correspondent voltage with above-mentioned switch-over control signal with the supply voltage of supplying with.
27, SIC (semiconductor integrated circuit) according to claim 4 is characterized in that:
The above-mentioned the 1st and the access speed of the 2nd Import ﹠ Export Department be fixing speed;
The supply voltage of the Import ﹠ Export Department that visiting frequency is higher is lower than the supply voltage of the lower Import ﹠ Export Department of visiting frequency.
28, SIC (semiconductor integrated circuit) according to claim 8 is characterized in that:
The supply voltage of the information holding circuit that visiting frequency is higher is lower than the supply voltage of the lower information holding circuit of visiting frequency.
29, SIC (semiconductor integrated circuit) according to claim 8 is characterized in that:
The supply voltage of above-mentioned switched circuit is higher than the supply voltage that the lower information of supply voltage is imported the Import ﹠ Export Department of usefulness;
Above-mentioned switched circuit, comprise: latch circuit, the temporary transient maintenance of information that will in the information holding circuit of the Import ﹠ Export Department that is connected the higher information input usefulness of supply voltage, keep, and the information that will keep outputs in the information holding circuit of the Import ﹠ Export Department that is connected the lower information input usefulness of supply voltage.
30, SIC (semiconductor integrated circuit) according to claim 10 is characterized in that:
Above-mentioned temporary transient holding circuit is made of the 1st phase inverter and the 2nd phase inverter;
The output of above-mentioned the 1st phase inverter is connected in the input of above-mentioned the 2nd phase inverter;
Above-mentioned the 2nd phase inverter has the 1st and 2NMOS transistor of series connection;
The input of above-mentioned the 1st phase inverter is connected on the 1NMOS transistor drain of the output of the 1st or the 2nd Import ﹠ Export Department of information input usefulness and above-mentioned the 2nd phase inverter;
The above-mentioned 1NMOS transistor of above-mentioned the 2nd phase inverter, its grid are connected in the output of above-mentioned the 1st phase inverter, and its source electrode is connected on the above-mentioned 2NMOS transistor drain;
Import the output of the 1st or the 2nd Import ﹠ Export Department of above-mentioned information input usefulness to the transistorized grid of the above-mentioned 2NMOS of above-mentioned the 2nd phase inverter.
31, SIC (semiconductor integrated circuit) according to claim 30 is characterized in that:
The information input is one with the number of the 1st or the 2nd Import ﹠ Export Department;
Import the energizing signal of above-mentioned information input to the transistorized source electrode of the above-mentioned 2NMOS of above-mentioned the 2nd phase inverter with the signal of the 1st or the 2nd Import ﹠ Export Department.
32, SIC (semiconductor integrated circuit) according to claim 30 is characterized in that:
The information input is a plurality of with the number of the 1st or the 2nd Import ﹠ Export Department;
The transistorized number of above-mentioned 2NMOS of above-mentioned the 2nd phase inverter is the number that equates with the above-mentioned the 1st or the number of the 2nd Import ﹠ Export Department;
Above-mentioned a plurality of 2NMOS transistor is cascaded, and will wherein be positioned at apart from the transistorized source ground of 2NMOS of the 1NMOS transistor position farthest of above-mentioned the 2nd phase inverter;
Signal to corresponding the above-mentioned the 1st or the 2nd Import ﹠ Export Department of transistorized each the grid input of above-mentioned a plurality of 2NMOS.
33, SIC (semiconductor integrated circuit) according to claim 32 is characterized in that:
A plurality of information inputs are input to the transistorized grid of 2NMOS of the 1NMOS transistor position farthest that is positioned at above-mentioned the 2nd phase inverter of distance with the signal of the higher Import ﹠ Export Department of the activate rate in the 1st or the 2nd Import ﹠ Export Department.
34, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
Comprise: the 1st virtual circuit, to above-mentioned the 1st information holding circuit carry out reading of data and subsequent data write and the 1st and the 2nd information holding circuit between exchanges data, and
The 2nd virtual circuit, to above-mentioned the 2nd information holding circuit carry out reading of data and subsequent data write and the 1st and the 2nd information holding circuit between exchanges data;
Constitute a plurality of MOS transistor of above-mentioned the 1st virtual circuit, the MOS characteristic of diffusion layer concentration, underlayer voltage or gate oxidation mould is all identical;
Constitute a plurality of MOS transistor of above-mentioned the 2nd virtual circuit, its part has same MOS characteristic with above-mentioned MOS characteristic, and remaining part has the different MOS characteristic of MOS characteristic with the MOS transistor that constitutes above-mentioned the 1st virtual circuit;
SIC (semiconductor integrated circuit), have adjustment offer respectively the above-mentioned the 1st and the supply voltage of the supply voltage of the 2nd virtual circuit adjust circuit;
Above-mentioned supply voltage is adjusted circuit, the supply voltage value that adjustment provides to above-mentioned the 1st virtual circuit, make the output delay of output signal value of above-mentioned the 1st virtual circuit become the predefined the 1st with reference to length of delay, the supply voltage value that will adjust offers the MOS transistor of the same MOS characteristic of the MOS transistor with above-mentioned the 1st virtual circuit in above-mentioned the 2nd virtual circuit simultaneously; And, the supply voltage value that the MOS transistor of the MOS characteristic that the MOS transistor with above-mentioned 1st virtual circuit of adjustment in above-mentioned the 2nd virtual circuit is different provides makes the output delay of output signal value of above-mentioned the 2nd virtual circuit become the predefined the 2nd with reference to length of delay.
35, SIC (semiconductor integrated circuit) according to claim 1 is characterized in that:
The the above-mentioned the 1st and the 2nd Import ﹠ Export Department and the above-mentioned the 1st and the 2nd information holding circuit are made of transistor circuit respectively;
The group that group that is made of above-mentioned the 1st Import ﹠ Export Department and above-mentioned the 1st information holding circuit and above-mentioned the 2nd Import ﹠ Export Department and above-mentioned the 2nd information holding circuit and above-mentioned switched circuit constitute has the power supply voltage supplying circuit of the supply voltage that different value is provided respectively;
The summation that the above-mentioned supply voltage value of respectively organizing power supply voltage supplying circuit is set at information readout time, write time and swap time in oneself the Import ﹠ Export Department respectively becomes the supply voltage value of stipulated time.
36, according to any described SIC (semiconductor integrated circuit) of claim 1～35, it is characterized in that:
SIC (semiconductor integrated circuit) is multithreading type processor.
CNB2005800006399A 2004-06-09 2005-06-08 Semiconductor integrated circuit Expired - Fee Related CN100517506C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004171853 2004-06-09
JP171853/2004 2004-06-09
JP028766/2005 2005-02-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CNA2009102033969A Division CN101582291A (en) 2004-06-09 2005-06-08 Semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
CN1820324A CN1820324A (en) 2006-08-16
CN100517506C true CN100517506C (en) 2009-07-22

Family

ID=36919546

Family Applications (2)

Application Number Title Priority Date Filing Date
CNA2009102033969A Pending CN101582291A (en) 2004-06-09 2005-06-08 Semiconductor integrated circuit
CNB2005800006399A Expired - Fee Related CN100517506C (en) 2004-06-09 2005-06-08 Semiconductor integrated circuit

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CNA2009102033969A Pending CN101582291A (en) 2004-06-09 2005-06-08 Semiconductor integrated circuit

Country Status (1)

Country Link
CN (2) CN101582291A (en)

Also Published As

Publication number Publication date
CN1820324A (en) 2006-08-16
CN101582291A (en) 2009-11-18

Similar Documents

Publication Publication Date Title
US6259623B1 (en) Static random access memory (SRAM) circuit
US7304883B2 (en) Semiconductor integrated circuit
US6107836A (en) Semiconductor integrated circuit device having power reduction mechanism
US9361950B1 (en) Semiconductor device with reduced leakage current and method for manufacture of the same
US20030012048A1 (en) VDD modulated sram for highly scaled, high performance cache
JP2004318941A (en) Semiconductor integrated circuit
CN104952481A (en) Semiconductor device and semiconductor storage device
JPH0786916A (en) Semiconductor integrated circuit
JP2003151280A (en) Semiconductor memory device
JP3142414B2 (en) Semiconductor integrated circuit having current consumption reduction function
US20040125683A1 (en) Semiconductor integrated circuit device
WO2003071553A1 (en) Semiconductor integrated circuit
JPH06162776A (en) Semiconductor memory circuit
US6990034B2 (en) Static semiconductor memory device and method of controlling the same
US5369620A (en) Dynamic random access memory device having column selector for selecting data lines connectable with bit lines
US5408438A (en) Semiconductor memory
US5546352A (en) Semiconductor memory device having decoder
CN100517506C (en) Semiconductor integrated circuit
JP3255159B2 (en) Semiconductor integrated circuit
US7095673B2 (en) Semiconductor memory device capable of operating at high speed
JP3567160B2 (en) Semiconductor integrated circuit
JP3255158B2 (en) Semiconductor integrated circuit
JP3085526B2 (en) Storage device
JPH052888A (en) Memory cell circuit for gate array
KR0167679B1 (en) Row address buffer having dual current pass

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20151105

Address after: Kanagawa

Patentee after: Co., Ltd. Suo Si future

Address before: Osaka Japan

Patentee before: Matsushita Electric Industrial Co., Ltd.

CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090722

Termination date: 20170608

CF01 Termination of patent right due to non-payment of annual fee