CN100514622C - Semiconductor packaging supported films and packaging construction for increasing pin intensity - Google Patents
Semiconductor packaging supported films and packaging construction for increasing pin intensity Download PDFInfo
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- CN100514622C CN100514622C CN 200710000366 CN200710000366A CN100514622C CN 100514622 C CN100514622 C CN 100514622C CN 200710000366 CN200710000366 CN 200710000366 CN 200710000366 A CN200710000366 A CN 200710000366A CN 100514622 C CN100514622 C CN 100514622C
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
The invention relates to a semiconductor package carrier film and configuration for enhancing pin strength. The semiconductor package carrier film mainly comprises a flexible dielectric layer, a plurality of pins formed on the flexible dielectric layer, a reinforced metal layer and a solder mask layer locally covering the pins, wherein at least one pin is provided with a bending point covered by the reinforced metal layer. Moreover, the solder mask layer further covers the reinforced metal layer. Accordingly, the invention can prevent the pin from fracturing at the bending point due to the stress. The invention also discloses a semiconductor package configuration using the carrier film.
Description
Technical field
The present invention relates to a kind of chip carrier that is applicable to semiconductor packages, particularly relate to a kind of semiconductor packages film carrier of pin intensity and semiconductor packaging structure that uses this film carrier of increasing.
Background technology
According to the applicability of semiconductor product and purposes change different, its chip carrier can be selected printed circuit board (PCB), lead frame and circuit film for use, wherein circuit film has the advantage of flexibility and thinning.For example, (Tape Carrier Package, TCP) (Chip-On-Film package all is to adopt circuit film as chip carrier COF) with the membrane of flip chip encapsulation in present coil type carrying encapsulation.Before encapsulation, circuit film is the unit in the winding, and can carry out the semiconductor packages operation with the winding transmission means.
As shown in Figures 1 and 2, existing known semiconductor packages film carrier 100 comprises a flexible dielectric layer 110, a plurality of pin 120 and a welding resisting layer 130.Those pins 120 are to be formed on this flexible dielectric layer 110, and this welding resisting layer 130 is local those pins 120 that cover.Most pin 120 is to divide into pin 124 in the oblique fan-out line 123 and of an outer pin 122,, and those fan-out lines 123 are to connect pins 124 and those outer pins 122 in those, and those outer pins 122 can be disperseed more.As shown in Figure 2, the surface of those pins 120 is to be formed with an electrodeposited coating 140, and this electrodeposited coating 140 outside the part on the pin 122 be for appearing, for being engaged to an external printed circuit board or a face glass.This welding resisting layer 130 is to have an opening 131, and it is the interior pin 124 that appears those pins 120, for joint wafer.Yet outside those, be formed with a plurality of inflection points 121 between pin 122 and those fan-out lines 123, it is to be positioned at the deflection position of this semiconductor packaging structure on user mode, the both sides of crooked this film carrier 100 all can cause the external carbuncle of those pins 120 can be concentrated to those inflection points 121, cause those pins 120 of minority to have fracture (fracture place 121A as shown in Figure 1), have the problem that electrically opens circuit, so make whole semiconductor package product to operate.
Because the defective that above-mentioned conventional semiconductor packages film carrier and packaging structure exist, the inventor is based on being engaged in this type of product design manufacturing abundant for many years practical experience and professional knowledge, and the utilization of cooperation scientific principle, actively studied innovation, in the hope of founding a kind of semiconductor packages film carrier and packaging structure of novel increase pin intensity, can improve general conventional semiconductor packages film carrier and packaging structure, make it have more practicality.Through constantly research, design, and, create the present invention who has practical value finally through after studying sample and improvement repeatedly.
Summary of the invention
Main purpose of the present invention is, a kind of semiconductor packages film carrier and the packaging structure that uses this film carrier that increases pin intensity is provided, and utilizes the reinforcement of weld layer to strengthen the anti-disconnected property in inflection point of pin, can prevent that this film from producing the problem of pin breakage at its flexible pars convoluta.
The object of the invention to solve the technical problems realizes by the following technical solutions.According to the present invention, a kind of semiconductor packages film carrier that increases pin intensity is to comprise a flexible dielectric layer, a plurality of pin, a reinforcement of weld layer and a welding resisting layer.Those pins are to be formed on this flexible dielectric layer, and wherein at least one pin is to have an inflection point.This reinforcement of weld layer is that the part is formed on this pin, to cover this inflection point.This welding resisting layer is to be formed on this flexible dielectric layer, with the position that covers those pins at least and a position of this reinforcement of weld layer.Whereby, increase the intensity of those pins privileged site on this film, produce pin breakage to prevent to be subjected to stress.In addition, disclose the semiconductor packaging structure that uses this semiconductor packages film carrier in addition.
Purpose of the present invention can be applied to the following technical measures to achieve further.
In aforesaid semiconductor packages film carrier, each pin is to have an oblique fan-out line and an outer pin, this fan-out line is to 180 degree between 90 degree with the minimum angle that is somebody's turn to do outer pin, this inflection point be this fan-out line and should outer pin between, and this outer pin be to have an exposed surface that is not covered by this welding resisting layer.
In aforesaid semiconductor packages film carrier, the exposed surface of this outer pin is to be formed with an electrodeposited coating, more can be formed on the whole pin and covers this reinforcement of weld layer.
In aforesaid semiconductor packages film carrier, the material of this reinforcement of weld layer is to be selected from one of them of copper, tin, gold, silver.
In aforesaid semiconductor packages film carrier, this reinforcement of weld layer is the protective sleeve of ㄇ tee section.
In aforesaid semiconductor packages film carrier, this reinforcement of weld layer is the cover layer of sheet strip.
By technique scheme, semiconductor packages film carrier and packaging structure that the present invention increases pin intensity have following advantage at least:
A kind of semiconductor packages film carrier and the packaging structure that uses this film carrier that increases pin intensity of the present invention utilizes the reinforcement of weld layer to strengthen the anti-disconnected property in inflection point of pin, prevents that this film from producing the problem of pin breakage at its flexible pars convoluta.
In sum, the present invention has above-mentioned plurality of advantages and practical value, no matter it all has bigger improvement on product structure or function, obvious improvement is arranged technically, and produced handy and practical effect, and have the outstanding effect of enhancement than conventional semiconductor packages film carrier and packaging structure, thus be suitable for practicality more, and have the extensive value of industry, really be a new and innovative, progressive, practical new design.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Fig. 1 is the end face schematic diagram of known semiconductor packages film carrier.
Fig. 2 is that known semiconductor packages film carrier is in the schematic partial cross-sectional view of fracture place.
Fig. 3 is according to first specific embodiment of the present invention, a kind of end face schematic diagram that increases the semiconductor packages film carrier of pin intensity.
Fig. 4 is according to first specific embodiment of the present invention, the schematic partial cross-sectional view of this semiconductor packages film carrier.
Fig. 5 uses the schematic cross-section of a kind of semiconductor packaging structure of this film carrier according to first specific embodiment of the present invention.
Fig. 6 is according to second specific embodiment of the present invention, and another kind increases the end face schematic diagram of the semiconductor packages film carrier of pin intensity.
Fig. 7 is according to second specific embodiment of the present invention, the schematic partial cross-sectional view of this semiconductor packages film carrier.
10: wafer 11: projection
20: adhesive body 100: the semiconductor packages film carrier
110: flexible dielectric layer 120: pin
121: inflection point 121A: fracture place
122: outer pin 123: fan-out line
124: interior pin 130: welding resisting layer
131: opening 140: electrodeposited coating
200: semiconductor packages film carrier 210: flexible dielectric layer
220: pin 221: inflection point
222: outer pin 223: fan-out line
224: interior pin 225: exposed surface
230: reinforcement of weld layer 240: welding resisting layer
241: opening 250: electrodeposited coating
300: semiconductor packages film carrier 310: flexible dielectric layer
320: pin 321: inflection point
322: outer pin 323: fan-out line
324: interior pin 330: reinforcement of weld layer
340: welding resisting layer 341: opening
350: electrodeposited coating
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, semiconductor packages film carrier and its embodiment of packaging structure, structure, feature and the effect thereof of the increase pin intensity that foundation the present invention is proposed, describe in detail as after.
According to first specific embodiment of the present invention, disclose a kind of semiconductor packages film carrier that increases pin intensity.As shown in Figures 3 and 4, this semiconductor packages film carrier 200 mainly comprises a flexible dielectric layer 210, a plurality of pin 220, a reinforcement of weld layer 230 and a welding resisting layer 240.
This flexible dielectric layer 210 is to be organic dielectric film layer, usually the material of this flexible dielectric layer 210 be can be polyimides (polyimide, PI) or polyesters (PET) etc., fixing and those pins 220 of electrical isolation for the attaching of those pins 220.Before encapsulation, a plurality of film carriers 200 can be integrally formed at a winding, for coil type transmission carrying out semiconductor packages operation.
Those pins 220 are to be formed on this flexible dielectric layer 210.Those pins 220 are to be the high-conductivity metal material, copper for example, and should considerably approach so that suitable flexibility to be provided, its thickness is far below the pin thickness of conventional wires frame.And wherein at least one pin 220 is to have one to cause the inflection point 221 that stress is concentrated easily.Each pin 220 is to have pin 224 in an outer pin 222, at least one oblique fan-out line 223 and from outside to inside, and those fan-out lines 223 are to 180 degree between 90 degree with the minimum angle of those outer pins 222.In the present embodiment, those fan-out lines 223 are in order to connect outer pin 222 than coarse pitch to the interior pin 224 than fine pith, this fan-out line 223 and minimum angle that should outer pin 222 be between 90 degree to 180 degree, this inflection point 221 is at this fan-out line 223 and outside being somebody's turn to do between the pin 222.In addition, as shown in Figure 4, this outer pin 222 is to have an exposed surface 225 that is not covered by this welding resisting layer 240, for engaging an external printed circuit board or a glass substrate (figure does not draw).
This reinforcement of weld layer 230 is that the part is formed on this pin 220, to cover this inflection point 221 at least.This reinforcement of weld layer 230 is the protective sleeve of ㄇ tee section generally, to cover upper surface and the two sides that this pin 220 comprises a section of this inflection point 221.In the present embodiment, this reinforcement of weld layer 230 is the exposed surfaces 225 that more can be formed at this outer pin 222.The material of this reinforcement of weld layer 230 is to can be selected from one of them of copper, tin, gold, silver, and can form with plating mode.As shown in Figure 4, and cooperate this reinforcement of weld layer 230, can strengthen the inflection point 221 anti-disconnected property of those pins 220, can prevent that this film from producing the problem of pin breakage at its flexible pars convoluta by the structure that this welding resisting layer 240 is covered.Preferably, should be more to be formed with an electrodeposited coating 250 on the exposed surface 225 of outer pin 222, it is can be formed on the corresponding whole pin 220 and cover to go up rheme this reinforcement of weld layer 230 on this inflection point 221, promoting the covering property of this reinforcement of weld layer 230, and prevent the reinforcement of weld layer oxidation that expose.
This welding resisting layer 240 is to be formed on this flexible dielectric layer 210, with the position that covers those pins 220 at least and a position of this reinforcement of weld layer 230, can prevent those pins 220 and the anchorage of this reinforcement of weld layer 230 because of exposing contaminated short circuit and strengthening this reinforcement of weld layer 230.This welding resisting layer 240 is to have an opening 241, and it is the interior pin 224 that appears those pins 220, for a plurality of projections 11 joints (as shown in Figure 5) of a wafer 10.Usually this welding resisting layer 240 is to can be liquid photosensitive welding cover layer (liquid photoimagable solder mask, LPI), photosensitive cover lay (photoimagable cover layer, PIC) or can be the non-conductive printing ink or the diaphragm-type cover layer (cover layer) of general non-photosensitive dielectric material.
According to first specific embodiment of the present invention, this semiconductor packages film carrier 200 can further be applied to the semiconductor packaging structure.See also Fig. 5, a kind of semiconductor packaging structure mainly comprises this film carrier 200 and a wafer 10.This wafer 10 is to be arranged at this film carrier 200 and to be electrically connected to those pins 220.In the present embodiment, this wafer 10 is to be provided with a plurality of projections 11, and it is the interior pin 224 that is engaged to those pins 220.This packaging structure can include an adhesive body 20 in addition, for example a kind of before curing the spot printing colloid of tool high fluidity, it is those projections 11 of sealing.Wherein, this reinforcement of weld layer 230 is between this wafer 10 and the deflection position between the pin 222 outside those at this film carrier 200, concentrate on the inflection point 221 that connects pin 222 outside those to avoid this film carrier 200 at case of bending to have stress, prevent that those pins 220 from producing fracture.
In second specific embodiment, disclose the another kind of semiconductor packages film carrier that increases pin intensity.As Figure 6 and Figure 7, this semiconductor packages film carrier 300 is to comprise a flexible dielectric layer 310, a plurality of pin 320, a reinforcement of weld layer 330 and a welding resisting layer 340.Those pins 320 are to be formed on this flexible dielectric layer 310, and wherein at least one pin 320 is to have an inflection point 321.This reinforcement of weld layer 330 is that the part is formed on this pin 320, to cover this inflection point 321.In the present embodiment, this reinforcement of weld layer 330 is cover layers of sheet strip, to cover the upper surface that this pin 320 comprises a section of this inflection point 321.This welding resisting layer 340 is to be formed on this flexible dielectric layer 310, with the position that covers those pins 320 at least and a position of this reinforcement of weld layer 330.Whereby, increase the intensity of those pins 320, produce pin breakage to prevent to be subjected to stress at these film 300 privileged sites.
In the present embodiment, each pin 320 is to have pin 324 in an outer pin 322, at least one fan-out line 323 and from outside to inside, this fan-out line 323 is to 180 degree between 90 degree with the minimum angle that is somebody's turn to do outer pin 322, this inflection point 321 be this fan-out line 323 and should outer pin 322 between, and should outer pin 322 be to have one not by the exposed surface of these welding resisting layer 340 coverings.Can be formed with an electrodeposited coating 350 on this exposed surface, it is not cover this reinforcement of weld layer 330, and both materials can be difference, and for example this electrodeposited coating 350 is to can be tin, and this reinforcement of weld layer 330 is to can be copper.In the present embodiment, this reinforcement of weld layer 330 more covers other inflection point (as shown in Figure 6) that connects those fan-out lines 323 except covering this inflection point 321.Moreover the some of the interior pin 324 of those pins 320 is openings 341 that are revealed in this welding resisting layer 340, for electrically connecting a wafer.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the technology contents that can utilize above-mentioned announcement is made a little change or is modified to the equivalent embodiment of equivalent variations, in every case be the content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (10)
1, a kind of semiconductor packages film carrier that increases pin intensity is characterized in that comprising:
One flexible dielectric layer;
A plurality of pins, it is to be formed on this flexible dielectric layer, wherein at least one pin is to have an inflection point;
One reinforcement of weld layer, it is that the part is formed on this pin, to cover this inflection point; And
One welding resisting layer, it is to be formed on this flexible dielectric layer, with the position that covers those pins at least and a position of this reinforcement of weld layer.
2, the semiconductor packages film carrier of increase pin intensity according to claim 1, it is characterized in that described each pin is to have an oblique fan-out line and an outer pin, this fan-out line is to 180 degree between 90 degree with the minimum angle that is somebody's turn to do outer pin, this inflection point be this fan-out line and should outer pin between, and this outer pin be to have an exposed surface that is not covered by this welding resisting layer.
3, the semiconductor packages film carrier of increase pin intensity according to claim 2, an exposed surface that it is characterized in that described outer pin are to be formed with an electrodeposited coating, and it is more to be formed on the corresponding whole pin to cover this reinforcement of weld layer.
4, the semiconductor packages film carrier of increase pin intensity according to claim 1 is characterized in that described reinforcement of weld layer is the protective sleeve of ㄇ tee section.
5, the semiconductor packages film carrier of increase pin intensity according to claim 1 is characterized in that described reinforcement of weld layer is the cover layer of sheet strip.
6, a kind of semiconductor packaging structure is characterized in that comprising:
One film carrier, it is to comprise:
One flexible dielectric layer;
A plurality of pins, it is to be formed on this flexible dielectric layer, wherein at least one pin is to have an inflection point;
One reinforcement of weld layer, it is that the part is formed on this pin, to cover this inflection point; And
One welding resisting layer, it is to be formed on this flexible dielectric layer, with the position that covers those pins at least and a position of this reinforcement of weld layer; And
One wafer, it is to be arranged at this film carrier and to be electrically connected to those pins.
7, semiconductor packaging structure according to claim 6, it is characterized in that described each pin is to have an oblique fan-out line and an outer pin, this fan-out line is to 180 degree between 90 degree with the minimum angle that is somebody's turn to do outer pin, this inflection point be this fan-out line and should outer pin between, and this outer pin be to have an exposed surface that is not covered by this welding resisting layer.
8, semiconductor packaging structure according to claim 6, an exposed surface that it is characterized in that described outer pin are to be formed with an electrodeposited coating, and it is more to be formed on the corresponding whole pin to cover this reinforcement of weld layer.
9, semiconductor packaging structure according to claim 6 is characterized in that described reinforcement of weld layer is the protective sleeve of ㄇ tee section.
10, semiconductor packaging structure according to claim 6 is characterized in that described reinforcement of weld layer is the cover layer of sheet strip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710000366 CN100514622C (en) | 2007-01-22 | 2007-01-22 | Semiconductor packaging supported films and packaging construction for increasing pin intensity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710000366 CN100514622C (en) | 2007-01-22 | 2007-01-22 | Semiconductor packaging supported films and packaging construction for increasing pin intensity |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101231986A CN101231986A (en) | 2008-07-30 |
| CN100514622C true CN100514622C (en) | 2009-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710000366 Expired - Fee Related CN100514622C (en) | 2007-01-22 | 2007-01-22 | Semiconductor packaging supported films and packaging construction for increasing pin intensity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100514622C (en) |
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2007
- 2007-01-22 CN CN 200710000366 patent/CN100514622C/en not_active Expired - Fee Related
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| CN101231986A (en) | 2008-07-30 |
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