CN100514316C - Dynamic self-adaptive bus arbiter based on microprocessor-on-chip - Google Patents
Dynamic self-adaptive bus arbiter based on microprocessor-on-chip Download PDFInfo
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- CN100514316C CN100514316C CNB2007100250774A CN200710025077A CN100514316C CN 100514316 C CN100514316 C CN 100514316C CN B2007100250774 A CNB2007100250774 A CN B2007100250774A CN 200710025077 A CN200710025077 A CN 200710025077A CN 100514316 C CN100514316 C CN 100514316C
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Abstract
The present invention discloses a dynamic self-adapting bus arbiter based on a SOC (system on a chip) multiprocessor system, consisting of an interface control module, a stochastic number producing module, a dynamic lottery number producing module, a timer module and a lottery bus arbitration module. The stochastic number producing module receives the range of the stochastic number outputted by the signal of the interface control module and configures the stochastic number into a total lottery number applied to and demanded by each processor to the bus. The dynamic lottery number producing module stores the initial number of the lottery held by each processor and responds to an activation of the interrupted signal produced by the timer module. The lottery bus arbitration module controls the using priority of the system bus according to the number of the lottery held by each processor. The present invention lowers the arithmetic complexity, reduces the bus waiting time of each processor and can better control the bandwidth occupied by each processor, thereby enhancing the system performance and providing a significant reference value for the design of a SOC multiprocessor system.
Description
Technical field
The present invention relates to a kind of on-chip multi-processor system that is applied to bus architecture, especially a kind of being applied to takies the high-performance on-chip multi-processor system that the bus bandwidth ratio has strict demand and has real-time to require, specifically a kind of dynamic self-adapting bus arbiter based on the on-chip multi-processor system to processor.
Background technology
Supported high-speed parallel to calculate in recent years and the multiprocessor SOC (system on a chip) of multimedia application (Multi-Processor System-on-a-Chip, MPSoC) development is rapid.The performance of the MPSoC system of employing shared bus framework depends on the efficient of arbitration mechanism to a great extent.Moderator is responsible for distributing the priority of each processor access shared resource, solves the competition that a plurality of processors sharing resources cause, distributes shared resource rationally, efficiently and guarantees the overall system performance optimum.
(Advanced High-performance Bus, AHB) system of Gou Chenging mainly is made of bus master, bus slave, bus arbitration, code translator, MUX etc., as shown in Figure 1 based on the AMBA high performance bus.Wherein bus address signal is HADDR, and reading data signal HRDATA, write data signal are HWDATA.The AMBA-AHB bus has been stipulated the agreement of arbitration, but arbitrating affairs can be according to the application demand specific design.The arbitrating signals of agreement regulation is as shown in table 1, wherein x indication equipment numbering.
Table 1
| Signal name | Signal source | Signal instruction |
| HBUSREQx | Main equipment | Main equipment is to the request signal of bus, and each main equipment all has its corresponding HBUSREQx signal, supports 16 main equipments at most |
| HLOCKx | Main equipment | When signal when being high, represent that corresponding main equipment is current to interrupting occupying of bus |
| HGRANTx | Moderator | Expression main equipment x current priority is the highest, and when HGRANTx and HREADY are when high, main equipment obtains the bus right of possession corporeal right |
| HMASTER[3:0] | Moderator | Provide current main equipment numbering of occupying bus to slave unit |
| HMASTLOCK | Moderator | Current main equipment transmits continuously, can not interrupt |
| HSPLITx[15:0] | Slave unit | The corresponding main equipment of SPLIT transmission before the expression |
The Lottery bus arbiter is a kind of more advanced arbitration mechanism that branch school, San Diego, USA California proposed in calendar year 2001.Its core concept is to adopt " the Lottery manager " of Weighted random algorithm.On the bus " lottery ticket " of each main equipment fixed allocation some (Ticket), " lottery ticket " is many more, the probability that this main equipment is authorized to is big more.Lottery ticket " number is the bus bandwidth ratio that each processor occupies.If the random number that moderator produces is that certain main equipment is held " lottery ticket ", then this equipment just obtains the bus right to use.For example: " lottery ticket " number that four processor systems, each processor are held is respectively 1,2,3 and 4, and they have all sent request to bus, and then " lottery ticket " adds up to 1+2+3+4=10 and open.The number of tandom number generator output this moment be 8,8 No. four processors hold " lottery ticket " the interval [6,10) in, so No. four processors acquisition bus rights to use.The probability that each main equipment obtains bus grant is as shown in Equation (1):
T wherein
1, t
2... t
nBe followed successively by main equipment 1,2..., " lottery ticket " number of n, r
1, r
2... r
nBe the variable of a series of Boolean types, represent that each equipment sends the situation of request.If any request, r
i=1, otherwise r
iBe 0.
The Lottery manager is used for distributing and controlling the bus bandwidth that each main equipment takies.Linear feedback shift register (LFSR) is used for producing the random number within the claimed range, thereby guarantees that each main equipment all has certain probability to be authorized to, and phenomenon wards off starvation.This referee method makes that higher priority devices operating lag in different request sequences is less.General modified Lottery bus arbiter has proposed to reduce the method for bus cache size or raising bus bandwidth control ability etc., but algorithm is all comparatively complicated, has increased the difficulty of design circuit and the hardware resource that moderator is consumed thereby increased at least 10 design parameters.
The Lottery bus arbitration is a kind of more advanced arbitration mechanism, can control the shared communication bandwidth of each processor well and capability of fast response is provided for the high priority communication.But its performance depends on to be each processor distribution communication bandwidth how reasonably.Because the right of priority setting is comparatively complicated among the high-performance MPSoC, is difficult to prediction.So, be necessary in MPSoC each processor for bus bandwidth requirements can not predetermined situation under, adopt the algorithm that dynamically produces " lottery ticket " number to satisfy the actual bus bandwidth demand of each processor.
Summary of the invention
In order to overcome the problem that prior art exists, the purpose of this invention is to provide a kind of dynamic self-adapting bus arbiter based on the on-chip multi-processor system, it has improved the entire system performance, reduce the bus stand-by period of each processor, and can control the bus bandwidth that each processor occupies well.
The objective of the invention is to be achieved through the following technical solutions:
A kind of dynamic self-adapting bus arbiter based on the on-chip multi-processor system is characterized in that: it comprises interface control module, random number generation module, dynamic " lottery ticket " number generation module, timer module and Lottery bus arbitration module; Be responsible for sending signal to the random number generation module with the interface control module of bus communication; The random number generation module is provided with the interface signal of random number range value, " lottery ticket " sum under scope of its output random number is configured to each processor application requires to bus; Dynamically " lottery ticket " number generation module is stored initial " lottery ticket " number that each processor is held, and, increase continuously it according to bus stand-by period of processor and hold " lottery ticket " number and obtain the bus response until processor in response to the activation of the look-at-me that timer module produced; Simultaneously in response to the activation of the look-at-me that timer module produced, take bus time according to processor and reduce it continuously and hold " lottery ticket " number and finish the use bus until processor; Lottery bus arbitration module receives the dynamically data of " lottery ticket " number generation module, and according to " lottery ticket " number that each processor is held, comes the use right of priority of control system bus.
Lottery ticket described in the present invention " number is the bus bandwidth ratio that each processor occupies.
Dynamically " lottery ticket " number generation module is provided with " lottery ticket " number upper and lower bound value, and after reaching the limit of, each processor is held " lottery ticket " number and no longer changed.
Interface control module meets the AMBA-AHB bus standard.
The result proves that the present invention has reached intended purposes.Thereby postpone the overall performance of the method raising on-chip multi-processor system of the bus grant probability of larger process device and the processor priority that reduction takies bus for a long time by continuous increase, and do not need to come the actual required bus bandwidth ratio that takies of each processor in the analytic system by a large amount of emulation.Compare with traditional moderator, the present invention has reduced algorithm complex, has reduced the bus stand-by period of each processor and can control the bus bandwidth that each processor occupies better, has improved system performance.
Description of drawings
Fig. 1 is based on system's connection layout of ahb bus;
Fig. 2 is the moderator signal graph;
Fig. 3 is the arbiter grants signal timing diagram;
Data line sequential chart when Fig. 4 is the transfer of the bus right to use;
Fig. 5 is the on-chip multi-processor system architecture diagram;
Fig. 6 is a bus bridge transmission state transition diagram;
Fig. 7 is a structural representation of the present invention;
Fig. 8 is a random number generation module synoptic diagram.
Embodiment
Work in the dynamic self-adapting bus arbiter based on the on-chip multi-processor system a kind of of the present invention on the AMBA-AHB bus of four processors sharing, see accompanying drawing 7, the module that comprises has: the interface control module 1, random number generation module 2, dynamic " lottery ticket " number generation module 3, timer module 4 and the Lottery bus arbitration module 5 that meet the AMBA-AHB bus standard; Interface control module 1 is responsible for the communication with bus, timer module 4 is sent interrupt request according to current processor wait bus situation and is given dynamically " lottery ticket " number generation module 3, thereby determine " lottery ticket " number of current each main equipment, random number generation module 2 produces the random number that meets area requirement, and Lottery bus arbitration module 5 produces according to the output with upper module and obtains bus usufructuary processor ID number.
Random number generation module 2 is provided with the interface signal of random number range value, " lottery ticket " sum under scope of its output random number can be configured to different processors application requires to bus.
Dynamically the initial shared bus bandwidth ratio of " lottery ticket " number generation module 3 each processor of storage is initial " lottery ticket " number that each processor is held; In response to the activation of the look-at-me of moderator timer internal, hold " lottery ticket " number and obtain the bus response until processor and increase continuously it according to bus stand-by period of processor; In response to the activation of the look-at-me of moderator timer internal 4, reduce it continuously and hold " lottery ticket " number and finish to use bus until processor and take bus time according to processor.Dynamically " lottery ticket " number generation module 3 is provided with " lottery ticket " number upper and lower bound value, and after reaching the limit of, each processor is held " lottery ticket " number and no longer changed.
" lottery ticket " number that Lottery bus arbitration module 5 is held according to each processor is the bus bandwidth ratio that each processor occupies, and comes the use right of priority of control system bus.
A kind of stratification bus system that comprises shared system bus and four processors as the master control device, this system comprises: four ground floor buses that each processor independently takies respectively are used for the visit to its privately owned storer; Bus bridge is used for being connected of ground floor bus and second layer bus, and processor controls is to the visit of different bus; Shared storage can be used for the synchronous and swap data between the different processor by four processor access; With second layer bus be each processor shared bus, comprising: the dynamic self-adapting bus arbiter, " lottery ticket " number that each processor is held is represented the shared bus bandwidth ratio of each processor, adopt the Weighted random algorithm to come the use right of priority of processor controls to system bus, activation in response to the look-at-me of moderator timer internal, increasing continuously it according to bus stand-by period of processor holds " lottery ticket " number and obtains the bus response until processor, activation in response to the look-at-me of moderator timer internal, reduce it continuously and hold " lottery ticket " number and finish to use bus and take bus time until processor according to processor, dynamically adjust the priority of processor with " lottery ticket " number, thereby reach the purpose that reduces the processor bus stand-by period by dynamic change; MUX is used for selecting effective one group of AMBA-AHB bus signals to return to bus master or slave unit according to the output GRANT signal of moderator.
The external signal of dynamic self-adapting bus arbiter as shown in Figure 2.According to the AMBA-AHB bus protocol, each processor may send effective HBUSREQ signal to the bus request right to use in the clock cycle in office.Moderator is at each rising edge clock request signal of all can sampling, and according to the next processor that can access bus of the dynamic self-adapting arbitration algorithm decision of inside.When the processor request locking of current use bus was visited, the HLOCK signal was changed to effectively, and moderator will can not license to other processor until current end of transmission (EOT).When a processor was obtained the authorization the burst transmission of carrying out a regular length, the HBUSREQ signal can not keep always.Moderator comes the data length of decision processor transmission according to the HBURST signal.If the burst of random length transmission, the request signal of processor is then remained valid until end of transmission (EOT).When not having processor application bus usufructuary, moderator then can license to default processor.
The sequential chart of moderator is asked for an interview Fig. 3 and Fig. 4.After the current end of transmission (EOT), promptly the HREADY signal is a high level among Fig. 3, and processor obtains the authorization simultaneously that moderator upgrades the HMASTER signal.The usufructuary switching of data line can be later than the usufructuary switching of address wire.When the HREADY signal is that high level indicates current end of transmission (EOT), current processor of obtaining the authorization can use address wire, but must wait until that last end of transmission (EOT) just can use data line, as shown in Figure 4.
The dynamic self-adapting bus arbiter is operated in the on-chip multi-processor system of a stratification bus architecture, and system architecture as shown in Figure 5.Four ground floor buses that processor independently takies respectively are used to visit its privately owned storer; Bus bridge is used for being connected of ground floor bus and second layer bus, and processor controls is to the visit of different bus, and its state machine is seen Fig. 6; With second layer bus be each processor shared bus, comprising: dynamic self-adapting moderator and MUX are used for selecting effective one group of AMBA-AHB bus signals to return to bus master or slave unit according to the output GRANT signal of moderator.When processor need be visited shared storage device, it sent request to the dynamic self-adapting bus arbiter, and moderator then return authorization signal is given corresponding processor.
Dynamic " lottery ticket " number generation module 3 is key components among the present invention.Below this module is described in detail.
Dynamically " lottery ticket " thus the number generation module is responsible for reaching according to the priority that the stand-by period of each processor is regulated each processor automatically the purpose of bus stand-by period and optimization system performance between the Balance Treatment device.Functions of modules comprises that the initial shared bus bandwidth ratio of each processor of storage is initial " lottery ticket " number that each processor is held, and, hold " lottery ticket " number and obtain the bus response until processor and increase continuously it according to bus stand-by period of processor in response to the activation of the look-at-me of moderator timer internal; In response to the activation of the look-at-me of moderator timer internal, reduce it continuously and hold " lottery ticket " number and finish bus until processor and use and take bus time according to processor.The dynamic self-adapting arbitration algorithm is seen formula (2), and wherein, subscript i represents each processor 1,2..., n; T
iRepresentative " lottery ticket " number, it is the amount of t (clock period) variation in time; t
iInitial value for each processor " lottery ticket " number; r
iBe request signal, g
iBe authorization signal, r
i, g
iIt all is the variable of Boolean type.
In this arbitration algorithm, if certain processor never obtains bus grant and its stand-by period arrives bus delay upper limit t
Max, then the look-at-me of timer is activated.Dynamically " lottery ticket " number generation module responds this look-at-me, and each clock period all can increase respective processor " lottery ticket " number and be responded until request.On the contrary, if the stand-by period less than bus delay lower limit t
Min, timer can send another look-at-me, and then " lottery ticket " each clock period of number all can be lowered up to it and not re-use bus or restart to wait for the bus response.Take big register for fear of moderator simultaneously and deposit " lottery ticket " number and cause performance to descend, Ti is provided with upper limit T
MaxAnd lower limit T
MinBe provided with for avoiding " lottery ticket " number occurring bearing.More than four parametric t
Max, t
Min, T
Max, T
MinCan be configured according to concrete application program and on-chip multi-processor system.Common T
MinBe 1, and T
MaxCan according to circumstances be provided with; t
MinBe generally 1, t
MaxThe 2-3 that is generally a multibyte transmission time doubly.Can further improve system performance by adjustment to these two groups of parameters.
Random number generation module synoptic diagram is seen Fig. 8.It is a linear feedback shift register (LFSR), can produce (2
10-1) pseudo-random number sequence of individual different random number state.According to the request situation of current processor to bus, " lottery ticket " sum that moderator adds up out current is as the maximal value of random number.The input of Lottery bus arbitration module comprises clock signal, request signal and " lottery ticket " number signal, according to algorithm shown in the formula (1), calculates the highest processor ID of current priority, exports corresponding authorization signal.
The on-chip multi-processor system of the stratification bus architecture among the present invention passes through rtl simulation, and connect up based on Altera Stratix II EP2S180 device layout, frequency of operation is 50MHz, has used 50163 ALUT, and wherein the dynamic self-adapting moderator only takies 1.5 ‰ area.Simulation result shows that the dynamic self-adapting bus arbiter compares with the conventional bus moderator, reduced by 68% task deadline, has shortened for 78% bus stand-by period and can control the shared bus bandwidth of each processor better.
Claims (3)
1, a kind of dynamic self-adapting bus arbiter based on the on-chip multi-processor system is characterized in that: it comprises interface control module (1), random number generation module (2), dynamic " lottery ticket " number generation module (3), timer module (4) and Lottery bus arbitration module (5); Be responsible for sending signal to random number generation module (2) with the interface control module (1) of bus communication, random number generation module (2) is provided with the interface signal of random number range value, " lottery ticket " sum under scope of its output random number is configured to each processor application requires to bus; Dynamically " lottery ticket " number generation module (3) is stored initial " lottery ticket " number that each processor is held, and the activation of the look-at-me that is produced in response to timer module (4), increase continuously it according to bus stand-by period of processor and hold " lottery ticket " number and obtain the bus response until processor; Simultaneously taking bus time according to processor reduces it continuously and holds " lottery ticket " number and finish the use bus until processor; Lottery bus arbitration module (5) receives the dynamically data of " lottery ticket " number generation module (3), according to " lottery ticket " number that each processor is held, comes the use right of priority of control system bus; The bus bandwidth ratio that described " lottery ticket " number occupies for each processor.
2, the dynamic self-adapting bus arbiter based on the on-chip multi-processor system according to claim 1, it is characterized in that: dynamically " lottery ticket " number generation module (3) is provided with " lottery ticket " number upper and lower bound value, after reaching the limit of, each processor is held " lottery ticket " number and is no longer changed.
3, the dynamic self-adapting bus arbiter based on the on-chip multi-processor system according to claim 1, it is characterized in that: interface control module (1) meets the AMBA-AHB bus standard.
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| CN101930422A (en) * | 2010-08-26 | 2010-12-29 | 浪潮电子信息产业股份有限公司 | Multi-core CPU interconnection structure based on multilayer AHB bus |
| CN102075578A (en) * | 2011-01-19 | 2011-05-25 | 南京大学 | Distributed storage unit-based hierarchical network on chip architecture |
| CN102662892B (en) * | 2012-03-02 | 2014-12-31 | 北京航空航天大学 | FlexRay communication controller |
| JP6819096B2 (en) * | 2016-06-30 | 2021-01-27 | オムロン株式会社 | Image processing equipment, image processing methods, and image processing programs |
| CN107391413A (en) * | 2017-07-21 | 2017-11-24 | 南京华捷艾米软件科技有限公司 | Synchronous zero-waiting bus and its access method |
| CN110825312B (en) * | 2018-08-10 | 2023-06-23 | 昆仑芯(北京)科技有限公司 | Data processing device, artificial intelligent chip and electronic equipment |
| CN112199317B (en) * | 2020-10-27 | 2022-10-18 | 南京大学 | Bridging system and bridging method for RISCV processor to access Flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1139241A (en) * | 1995-01-16 | 1997-01-01 | 三星电子株式会社 | Distributed arbiter |
| CN1474296A (en) * | 2003-04-11 | 2004-02-11 | 大唐移动通信设备有限公司 | Data interacting method and device between multiple processors based on shared storage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1139241A (en) * | 1995-01-16 | 1997-01-01 | 三星电子株式会社 | Distributed arbiter |
| CN1474296A (en) * | 2003-04-11 | 2004-02-11 | 大唐移动通信设备有限公司 | Data interacting method and device between multiple processors based on shared storage |
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Effective date of registration: 20200521 Address after: 210049 second floor, unit B, No. 300, Zhihui Road, Qilin science and Technology Innovation Park, Jiangning District, Nanjing City, Jiangsu Province Patentee after: NANJING NINGQI INTELLIGENT COMPUTING CHIP RESEARCH INSTITUTE Co.,Ltd. Address before: 8, 210093 floor, Meng Meng Road, Nanjing University, 22 Hankou Road, Jiangsu, Nanjing Patentee before: NANJING University |