CN100512360C - Asymmetric digital customer wire modem and method for regulating its hardware moudel - Google Patents
Asymmetric digital customer wire modem and method for regulating its hardware moudel Download PDFInfo
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- CN100512360C CN100512360C CNB2004100499158A CN200410049915A CN100512360C CN 100512360 C CN100512360 C CN 100512360C CN B2004100499158 A CNB2004100499158 A CN B2004100499158A CN 200410049915 A CN200410049915 A CN 200410049915A CN 100512360 C CN100512360 C CN 100512360C
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Abstract
In the invention, hardware module carries out scheduling for hardware modules in ADSL modem. The scheduler module includes counting unit, scheduling unit, and storage unit. The counting unit supplies basis time signal in use for scheduling, frame termination signal and super frame signal at sending side and receiving side. Storage unit stores microcode run by modulation at sending side and demodulation at receiving side. Being received frame termination signal from sending side or receiving side, the scheduling unit fetches, decodes and executes microcode run at the side: first, resetting each control signal; then based on whether super frame signal at the side is valid or not, controlling each hardware module to carry out modulation or demodulation process of synchronizing frame or data frame; after receiving termination signal of next frame from the side, running microcode circularly. Features are: simple structure, fast response speed and adaptability through modifying microcode.
Description
Technical field
The present invention is mainly used in the broadband access field, specifically, is applied to the modulator-demodulator in the ADSL (Asymmetric Digital Subscriber Line) (ADSL).
Background technology
Digital subscriber line (DSL, Digital Subscriber Line) is to be the transmission technology of transmission medium with copper telephone wire, and wherein ADSL belongs to asymmetric transmission, and its up-downgoing transmission rate reaches 8kbit/s and 8Mbit/s respectively.
Fig. 1 is the system block diagram of existing ADSL.The major function of the modulator-demodulator (Modem) of ADSL transceiver unit in central office among the figure (ATU-C, ADSL Transceiver Unit at the central office end) comprising:
At transmitter side, the data that are sent to far-end ADSL transceiver unit (ATU-R, ADSL TransceiverUnit at the remote terminal end) are carried out framing, constellation mapping and inverse fast fourier transform (IFFT), finally export by twisted-pair feeder.
At receiver side, the data of coming are carried out fast Fourier transform (FFT), constellation is separated mapping and conciliate frame to receiving from ATU-R simultaneously.
The implementation of ADSL modem chip is the DSP+ hardware mode among the ATU-C at present, in this implementation, mainly be to use software to realize some algorithms such as reed-solomon (RS) encoding and decoding of ADSL, FFT/IFFT etc., these algorithm computation amounts are very big, if realize multi-channel A SL integrated (present ADSL nest plate integrated 8 road or 16 tunnel), then the algorithm computation amount is bigger, must use the operating frequency of a plurality of DSP or raising DSP, this all can make chip produce very big power consumption.
In hardware implementation mode, each module that algorithm is relevant, as FFT/IFFT, constellation mapping/separate mapping, framing/separate frame can adopt corresponding hardware to realize, but how to make each hardware module can be good at co-ordination, is that key issue to be solved is arranged.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator, and each hardware module of chip internal can co-ordination, and simple in structure, response speed is fast.
In order to solve the problems of the technologies described above, the invention provides a kind of ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator, comprise hard-wired inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate frame module, it is characterized in that, also comprise the hard-wired scheduler module that links to each other with described each hardware module, this scheduler module further comprises counting unit, scheduling unit and memory cell, wherein:
Described counting unit comprises a plurality of counters, the frame end signal and the superframe signal of signal, transmission and receiver side when described scheduling unit output scheduling basic;
Described memory cell is deposited the microcode that transmitter side modulation and receiver side demodulation are moved;
Described scheduling unit, comprise and send and the receiving scheduling subelement, go out the instruction of transmitter side and receiver side respectively from described cell array area, the decoding back is in conjunction with described transmission and receiver side superframe signal, start described inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate the control signal of frame module work by time of process settings and order output, receive to get again behind the frame end signal to refer to carry out.
Further, above-mentioned ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator can have following characteristics: described counting unit comprises two basic counters and two frame counters, described two basic counters are exported the count signal of 250 μ s one-periods respectively to described transmission and receiving scheduling subelement, signal and frame end signal during as described base.
Further, above-mentioned ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator can have following characteristics: described two basic counters are difference output frame end signal when once counting finishes, trigger described two frame counters and add 1, these two frame counters count down to the superframe signal of exporting described transmission and receiver side after the 68 respectively New count of laying equal stress on.
Further, above-mentioned ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator can have following characteristics: described memory cell is erasable memory.
Further, above-mentioned ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator can have following characteristics: described transmission and receiving scheduling subelement include to get and refer to circuit, decoding circuit, executive circuit and address control circuit, wherein: the described finger circuit of getting is used for reading corresponding instruction from described memory cell; Described decoding circuit is used for the instruction decoding to reading; Described executive circuit, signal, transmission and receiver side superframe signal when being used for, triggering for generating relevant hardware control signal according to decode results and described base; Described address control circuit is used to generate the address of reading command, after an instruction executes, the address is added 1 address after taking off an instruction or pointing to redirect, receive the frame end signal after, the address is pointed to again first address location of current operation microcode.
Further, above-mentioned ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator can have following characteristics: described microcode exists with the form of table, transmitter side and receiver side respectively have two tables, the first address of the microcode table that the address control circuit of described transmitter side and receiver side is read according to the table switch-over control signal decision of input respectively.
The another technical problem that the present invention will solve provides a kind of dispatching method of ADSL (Asymmetric Digital Subscriber Line) modem hardware module, can make the hardware module co-ordination in the ADSL Modem chip.
In order to solve the problems of the technologies described above, the invention provides a kind of dispatching method of ADSL (Asymmetric Digital Subscriber Line) modem hardware module, described hardware module comprises and said method comprising the steps of inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate frame module:
(a) be provided with when using hard-wired scheduler module, this scheduler module to comprise to provide the scheduling base, the counting unit of frame end signal and superframe signal, store the memory cell of the microcode that will move and control the scheduling unit of each hardware module work;
(b) described scheduling unit is received the frame end signal of transmission or receiver side;
(c) described scheduling unit reading command, decoding and execution from the microcode of this side operation, during execution, each control signal at first resets;
(d) described scheduling unit judges whether this side superframe signal is effective, if effectively, control inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate modulation or demodulation process that frame module carries out synchronization frame, otherwise control modulation or demodulation process that described each hardware module is carried out Frame;
(e) after described scheduling unit is received the next frame end signal of this side, return step (c).
Further, above-mentioned dispatching method can have following characteristics: the instruction of described microcode form is made up of command code and control signal code, and described order comprises: idle, reset, trigger, wait for, judge and finish; Described control signal comprises: beginning framing signals, beginning constellation mapping signal, beginning inverse fast fourier transform signal, begin to separate frame signal, the beginning constellation is separated mapping signal, beginning fast fourier transform signal, transmitter side superframe signal, receiver side superframe signal.
Further, above-mentioned dispatching method can have following characteristics: in the described step (d), the flow process that described each hardware module of described scheduling unit control is carried out the modulation treatment of synchronization frame is: send beginning constellation mapping signal, wait for that the constellation mapping process finishes, send beginning inverse fast fourier transform signal, wait for that the inverse fast fourier transform process finishes; The flow process that described each hardware module of described scheduling unit control is carried out the modulation treatment of Frame is: send the beginning framing signals, the wait framing procedure finishes, send beginning constellation mapping signal, wait for that the constellation mapping process finishes, send beginning inverse fast fourier transform signal, wait for that the inverse fast fourier transform process finishes.
Further, above-mentioned dispatching method can have following characteristics: in the described step (d), the flow process that described each hardware module of described scheduling unit control is carried out the demodulation process of synchronization frame is: send beginning fast fourier transform signal, the wait fast fourier transform finishes, send the beginning constellation and separate mapping signal, wait for that the constellation mapping process finishes; The flow process that described each hardware module of described scheduling unit control is carried out the demodulation process of Frame is: send beginning fast fourier transform signal, the wait fast fourier transform finishes, send the beginning constellation and separate mapping signal, wait for that the constellation mapping process finishes, send and begin to separate frame signal, wait for that separating the frame process finishes.
Further, above-mentioned dispatching method can have following characteristics: described memory cell respectively has two microcode tables at transmitter side and receiver side, in the described step (c), described scheduling unit earlier by the table switch-over control signal from two microcode tables of transmitter side or from both microcode tables of receiver side, select to read wherein one, reading command therefrom again.
As from the foregoing, the present invention utilizes hard-wired scheduler module that each hardware module of ADSL Modem is dispatched, and make each hardware module co-ordination, and scheduler module is simple in structure, cost be can save, scheduling and response speed improved each hardware module; Hardware automatically performs microcode, does not need software control, takies software resource hardly; By software programming, can also improve the flexibility of scheduler module greatly to microcode.After having adopted the present invention, the ADSL modem chip can be realized with devices at full hardware, and tunable work, and not only operating frequency is low, and speed is faster.
Description of drawings
Fig. 1 is the system block diagram of ADSL.
Fig. 2 is embodiment of the invention scheduler module and the structure chart that is connected with other hardware module thereof.
Fig. 3 is the structure chart of embodiment of the invention counting unit.
Fig. 4 is the frame assumption diagram of ADSL.
Fig. 5 is the structure chart of embodiment of the invention memory cell and scheduling unit.
Fig. 6 A and Fig. 6 B are respectively the control flow chart of embodiment of the invention scheduler module to transmitter side and receiver side.
Embodiment
In order to make each hardware module co-ordination of ADSL modem chip, the present invention is provided with hard-wired scheduler module, this module is made of scheduling unit, memory cell and counting unit, all realize with hardware, when counting unit provides required basic of scheduling unit, frame end signal and superframe signal, memory cell is deposited the microcode of dispatching office utilization, and scheduling unit then is used to finish the control to each hardware module.The structure that Fig. 2 shows scheduler module and is connected with other hardware module.
As shown in Figure 3, counting unit comprises two counter groups, and each counter group has two counters.
First set of counters comprises basic counter of transmitter side and the basic counter of receiver side, these two basic counters are 12 bit bit wide counters, be respectively transmitter side and receiver side 12 count signal: tx_basetime[11:0 of 250 μ s one-periods be provided in real time] and rx_basetime[11:0], 250 μ s are the time widths that Frame is shared.Basic rolling counters forward after the pairing count value of 250 μ s (concrete count value is relevant with clock frequency) New count of laying equal stress on resets, thereby this count signal can certainly adopt independent frame end signal to output to scheduling unit also as the frame end signal that expression one frame receives or transmission finishes.
Second set of counters comprises transmitter side frame counter and receiver side frame counter, when being used to provide a superframe basic.ADSL agreement regulation, each ADSL Frame is 250 μ s, and each ADSL superframe is 17ms, comprises 67 Frames and a synchronization frame (synchronization frame does not have valid data), and the ADSL frame structure is as shown in Figure 4.Can be when corresponding basic rolling counters forward finishes to the frame counter output frame end signal of homonymy, the frame counter that triggers same side adds 1.And the frame counter of transmitter side and receiver side can be respectively to scheduling unit output transmitter side superframe signal (tx_sframe_end) and receiver side superframe signal (rx_sframe_end) after counting down to 68, represent that current transmission or reception are synchronization frames, an ADSL superframe sends or receives, and counts again then.
Fig. 5 shows the structure of memory cell and scheduling unit.Trigger among the RAM of action with the form write storage unit of microcode of control signal, the microcode that writes among the RAM exists with the form of showing, transmitter side has two table: table0 (table 0) and table1 (table 1), and receiver side also has two table: table2 (table 2) and table3 (table 3).Two tables of homonymy adopt ping-pong structure, select current which table that reads by the table switch-over control signal.Wherein during the microcode in table, can carry out read-write operation to the microcode in another table, like this in operation, can be under the situation that does not influence hardware operation, finish down the configuration of the hardware operation under a kind of situation, when needs enter down a kind of configuration, switch the microcode table and get final product.
Scheduling unit is further formed by sending scheduling sublayer unit and receiving scheduling subelement, and each subelement further comprises:
Get the finger circuit, be used for from corresponding microcode table sense order;
Decoding circuit is used for the instruction of reading is deciphered, and the implication of each instruction of present embodiment will be described in detail below;
Executive circuit, be used for according to decode results and during from counting unit input basic, transmitter side and receiver side superframe signal, trigger the relevant hardware control signal, control the action of each hardware module;
Address control circuit is used to generate the address of reading microcode, and during operation, after an instruction executed, scheduling unit can refer to that the address adds 1 address after taking off an instruction or pointing to redirect getting.There is the long weak point that has the time of implementation of every instruction, and as waiting for instruction, when having only value when basic counter to equal to wait for value in the microcode, gets the finger address and just adds 1.The first address of the microcode table that address control circuit is read according to the table switch-over control signal decision of input is selected an operation from two tables.
In actual moving process, scheduling unit is finished automatically and is got finger, and decoding is carried out, and these microcodes of circular flow.Because the data of adsl link are continuous, so the end of each frame is exactly the beginning of next frame, and counting unit can provide the frame end signal, after scheduling unit is received the frame end signal, restart the finger process of getting, simultaneously the address is pointed to first address location of current use microcode table.
The microcode of present embodiment is the 16-bit data, is made up of order and control signal.Wherein order is the 4-bit width, total following 7 kinds:
Idle (IDLE): do not have operation, represent with Binary Zero 000.
(RESET) resets: control signal is put 0, represent with Binary Zero 001.
Set (SET): control signal is put 1, represent with Binary Zero 010.
Trigger (TRIGGER): this action makes control signal produce a pulse signal, represents with Binary Zero 011.
Wait for (WAIT): continue to carry out the later microcode of this microcode after waiting for basic rolling counters forward to a set point, represent with Binary Zero 100.
Judge (IF): judge order, represent, for true, then carry out the following microcode of this order, till running into the finish command if judge order with Binary Zero 101.For false, then carry out END instruction microcode afterwards if judge order.
Finish (END): the finish command, represent with Binary Zero 110, corresponding with the IF order before it.
Control signal is the 12-bit width, has 8, is divided into transmitter side, receiver side and counting unit control signal.Wherein:
The transmitter side control signal has:
Beginning framing (frame_begin): label is 0, triggers framing procedure.
Beginning constellation mapping (map_begin): label is 1, triggers the constellation mapping process.
Beginning IFFT (IFFT_begin): label is 2, triggers the IFFT process.
The receiver side control signal has:
Begin to separate frame (deframe_begin): label is 4, triggers the frame process of separating.
Begin to separate mapping (demap_begin): label is 5, triggers constellation and separates mapping process.
Beginning FFT (FFT_begin): label is 6, triggers the FFT process.
Wherein begin framing and begin to separate frame signal to output to framing/separate frame module, beginning constellation mapping and begin to separate mapping signal and output to constellation mapping/separate mapping block, beginning IFFT and beginning FFT signal output to the IFFT/FFT module
The signal that counting unit outputs to scheduling unit comprises:
Transmitter side superframe signal (tx_sframe_end): label is 3, and expression transmitter side superframe finishes.Provided by the transmitter side frame counter when the transmitter side frame counter count down to 67, it is a pulse signal.
Receiver side superframe signal (rx_sframe_end): label is 7, and expression receiver side superframe finishes.Being provided by the receiver side frame counter when the receiver side frame counter count down to 67, also is pulse signal.
Introduce the dispatching method of scheduler module to transmitter side and receiver side hardware module below, when present embodiment was encoded to ADSL transmitter side data, it was as follows to write the microcode that will carry out earlier in the transmission microcode table table0 of current use:
0,001 0,000 0,000 0000: the beginning framing signals resets
0,001 0,000 0,000 0001: the beginning constellation mapping that resets signal
0,001 0,000 0,000 0010: beginning IFFT signal resets
0,001 0,000 0,000 0011: transmitter side superframe signal resets
0,101 0,000 0,000 0011: judge whether superframe finishes
0,011 0,000 0,000 0001: true if top superframe finishes to be judged as, trigger the constellation mapping process
0,100 0,000 1,000 0000: wait for 128 time quantums (time quantum determines by system clock frequency, and promptly basic counter adds for 1 the time interval, suppose 128 time quantums finish the constellation mapping process)
0,011 0,000 0,000 0010: trigger the IFFT process
0,100 0,000 1,100 0000: wait for 192 time quantums (supposing 192 time quantums of IFFT process need)
0,110 0,000 0,000 0000: carry out END command
0,011 0,000 0,000 0000: if top superframe finishes to be judged as vacation, then trigger framing signals, the beginning framing procedure
0,100 0,000 0,100 0000: wait for 64 time quantums (need supposing 64 time quantums to finish framing procedure)
0,011 0,000 0,000 0001: trigger the constellation mapping process
0,100 0,000 1,000 0000: wait for 128 time quantums
0,011 0,000 0,000 0010: trigger the IFFT process
0,100 0,000 1,100 0000: wait for 192 time quantums
0,000 0,000 0,000 0000: carry out idle order.
Whether above-mentioned microcode is true time judging that superframe finishes, if be true, illustrates that present frame is a synchronization frame, owing to do not comprise data in the synchronization frame, only needs through constellation mapping and IFFT process; If be not true, illustrate that present frame is a Frame, need through framing, constellation mapping and IFFT process.
During work, send the scheduling sublayer unit after receiving the frame end signal of transmitter side, get finger in order from the table0 of transmitter side, decoding is carried out, and in the different control signal of different time trigger, finishes the modulated process of transmitter side data.Its flow process may further comprise the steps as shown in Figure 6A:
Step 110, each control signal of initialization comprises beginning framing signals, beginning constellation mapping signal, beginning IFFT signal, transmitter side superframe signal;
Step 120 judges whether transmitter side superframe pulse signal arrives, if, show that present frame is a synchronization frame, carry out next step, otherwise show that present frame is a Frame, execution in step 180;
Step 130, scheduling unit are sent beginning constellation mapping signal, beginning constellation mapping process;
Step 140 waits for that the constellation mapping process finishes;
Step 150, scheduling unit are sent beginning IFFT signal, and beginning is transformed into time domain to data from frequency domain;
Step 160 waits for that the IFFT process finishes;
Step 170 is carried out the finish command, and execution in step 250 then;
Step 180, scheduling unit are sent the beginning framing signals, and beginning is the packing data framing;
Step 190 is waited for into frame module and is finished framing procedure;
Step 200, scheduling unit are sent beginning constellation mapping signal, beginning constellation mapping process;
Step 210 waits for that the constellation mapping process finishes;
Step 220, scheduling unit are sent beginning IFFT signal, and beginning is transformed into time domain to data from frequency domain.
Step 230 waits for that the IFFT process finishes;
Step 240 is carried out idle order;
Step 250, receive the frame end signal after, return step 110;
When instruction was end or idle order, scheduling unit was no longer carried out other instruction, but waits for that it is the present frame end signal that next frame begins, and after receiving the present frame end signal, began to carry out from step 110 again.
When present embodiment was decoded to ADSL receiver side data, it was as follows to write the microcode that will carry out earlier in the reception microcode table table2 of current use:
0,001 0,000 0,000 0100: resetting begins to separate frame signal
0,001 0,000 0,000 0101: resetting begins to separate mapping signal
0,001 0,000 0,000 0110: beginning FFT signal resets
0,001 0,000 0,000 0111: receiver side superframe signal resets
0,101 0,000 0,000 0111: judge whether superframe finishes
0,011 0,000 0,000 0110: true if superframe finishes to be judged as, then trigger the FFT process
0,100 0,000 0,100 0000: wait for 64 time quantums (suppose 64 time quantums finish the FFT process)
0,011 0,000 0,000 0101: trigger constellation and separate mapping process
0,100 0,000 0,100 0000: wait for 64 time quantums (suppose constellation separate mapping process and need 64 time quantums)
0,110 0,000 0,000 0000: carry out END command
0,011 0,000 0,000 0110:, then trigger the FFT process if be not superframe by the IF command determination
0,100 0,000 0,100 0000: wait for 64 time quantums
0,011 0,000 0,000 0101: trigger constellation and separate mapping process
0,100 0,000 0,100 0000: wait for 64 time quantums
0,011 0,000 0,000 0100: trigger the frame process of separating
0,100 0,000 0,100 0000: wait for 64 time quantums (supposing to separate 64 time quantums of frame process need)
0,000 0,000 0,000 0000: carry out idle order.
Whether above-mentioned microcode is true time judging that superframe finishes, if be true, illustrates that the present frame that receives is a synchronization frame, owing to do not comprise data in the synchronization frame, only needs to conciliate mapping process through FFT; If be not true, illustrate that present frame is a Frame, need through FFT, constellation mapping and framing procedure.
During work, the receiving scheduling subelement is after receiving the frame end signal of receiver side, and beginning is got finger in order from the table2 of receiver side, and decoding is carried out, and in the different control signal of different time trigger, finishes the demodulating process of receiver side to data.Its flow process may further comprise the steps shown in Fig. 6 B:
Step 310, each control signal of initialization, comprise begin to separate frame signal, begin to separate mapping signal, beginning FFT signal and receiver side superframe signal;
Step 320 judges whether receiver side superframe pulse signal arrives, if show that present frame is a synchronization frame, carries out next step; Otherwise show that present frame is a Frame, execution in step 380;
Step 330, scheduling unit are sent beginning FFT signal, are transformed into frequency domain receiving data from time domain;
Step 340 waits for that the FFT process finishes;
Step 350, scheduling unit are sent and are begun to separate mapping signal, and the beginning constellation is separated mapping process;
Step 360, wait constellation are separated mapping process and are finished;
Step 370, behind execution the finish command, execution in step 450 then;
Step 380, scheduling unit trigger beginning FFT signal, are transformed into frequency domain receiving data from time domain;
Step 390 waits for that the FFT process finishes;
Step 400, scheduling unit trigger and begin to separate mapping signal, data are carried out constellation separate mapping;
Step 410, wait constellation are separated mapping process and are finished;
Step 420, scheduling unit trigger and begin to separate frame signal, begin to separate the frame process;
Step 430 waits for that separating the frame process finishes;
Step 440 is carried out idle order;
Step 450, receive the frame end signal after, return step 310.
When instruction was end or idle order, scheduling unit was no longer carried out other instruction, but waits for that it is the present frame end signal that next frame begins, and after receiving the present frame end signal, began to carry out from step 310 again.
In sum, the present invention directly uses the hardware controls signal to remove control hardware, except realizing making each hardware coordination work of ADSL modem chip, can also realize very fast response speed; Hardware automatically performs microcode, does not need software control, takies software resource hardly.
On the basis of the foregoing description, can do various conversion.In real process, can be by microcode be carried out software programming, satisfy under the different situations control to hardware.For example, in adsl link, the situation that also has bit exchange when stable state occurs; In initialization procedure, different states has different operations; G.992.1 and G.992.3 the flow process of embodiment then can change accordingly according to the ADSL agreement, waits for the different time, triggers different control signals.Correspondingly need increase control signal or increase control command in scheduler module, the figure place of microcode also can make scheduler module that very big flexibility be arranged along with the increase of order and control signal is expanded.In addition, RAM also can adopt other erasable memory device.
Claims (11)
1, a kind of ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator, comprise hard-wired inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate frame module, it is characterized in that, also comprise the hard-wired scheduler module that links to each other with described each hardware module, this scheduler module further comprises counting unit, scheduling unit and memory cell, wherein:
Described counting unit comprises a plurality of counters, the frame end signal and the superframe signal of signal, transmission and receiver side when described scheduling unit output scheduling basic;
Described memory cell is deposited the microcode that transmitter side modulation and receiver side demodulation are moved;
Described scheduling unit, comprise and send scheduling sublayer unit and receiving scheduling subelement, go out the instruction of transmitter side and receiver side respectively from described cell array area, the decoding back is in conjunction with described transmission and receiver side superframe signal, start described inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate the control signal of frame module work by time of process settings and order output, receive to get again behind the frame end signal to refer to carry out.
2, ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator as claimed in claim 1, it is characterized in that, described counting unit comprises two basic counters and two frame counters, described two basic counters are exported the count signal of 250 μ s one-periods respectively to described transmission scheduling sublayer unit and receiving scheduling subelement, signal and frame end signal during as described base.
3, ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator as claimed in claim 2, it is characterized in that, described two basic counters when once counting finishes respectively the output frame end signal trigger described two frame counters and add 1, these two frame counters count down to the superframe signal of exporting described transmission and receiver side after the 68 respectively New count of laying equal stress on.
4, ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator as claimed in claim 1 is characterized in that, described memory cell is erasable memory.
5, ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator as claimed in claim 1 is characterized in that, described transmission scheduling sublayer unit and receiving scheduling subelement include to get and refer to circuit, decoding circuit, executive circuit and address control circuit, wherein:
The described finger circuit of getting is used for reading corresponding instruction from described memory cell;
Described decoding circuit is used for the instruction decoding to reading;
Described executive circuit, signal, transmission and receiver side superframe signal when being used for, triggering for generating relevant hardware control signal according to decode results and described base;
Described address control circuit is used to generate the address of reading command, after an instruction executes, the address is added 1 address after taking off an instruction or pointing to redirect, receive the frame end signal after, the address is pointed to again first address location of current operation microcode.
6, ADSL (Asymmetric Digital Subscriber Line) modulator-demodulator as claimed in claim 5, it is characterized in that, described microcode exists with the form of table, transmitter side and receiver side respectively have two tables, the first address of the microcode table that the address control circuit of described transmitter side and receiver side is read according to the table switch-over control signal decision of input respectively.
7, a kind of dispatching method of ADSL (Asymmetric Digital Subscriber Line) modem hardware module, described hardware module comprises and said method comprising the steps of inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate frame module:
(a) be provided with when using hard-wired scheduler module, this scheduler module to comprise to provide the scheduling base, the counting unit of frame end signal and superframe signal, store the memory cell of the microcode that will move and control the scheduling unit of each hardware module work;
(b) described scheduling unit is received the frame end signal of transmission or receiver side;
(c) described scheduling unit reading command, decoding and execution from the microcode of this side operation, during execution, each control signal at first resets;
(d) described scheduling unit judges whether this side superframe signal is effective, if effectively, control inverse fast fourier transform/fast fourier transform module, constellation mapping/separate mapping block and framing/separate modulation or demodulation process that frame module carries out synchronization frame, otherwise control modulation or demodulation process that described each hardware module is carried out Frame;
(e) after described scheduling unit is received the next frame end signal of this side, return step (c).
8, dispatching method as claimed in claim 7 is characterized in that, the instruction of described microcode form is made up of command code and control signal code, and described order comprises: idle, reset, trigger, wait for, judge and finish; Described control signal comprises: beginning framing signals, beginning constellation mapping signal, beginning inverse fast fourier transform signal, begin to separate frame signal, the beginning constellation is separated mapping signal, beginning fast fourier transform signal, transmitter side superframe signal, receiver side superframe signal.
9, dispatching method as claimed in claim 7, it is characterized in that, in the described step (d), the flow process that described each hardware module of described scheduling unit control is carried out the modulation treatment of synchronization frame is: send beginning constellation mapping signal, wait for that the constellation mapping process finishes, send beginning inverse fast fourier transform signal, wait for that the inverse fast fourier transform process finishes; The flow process that described each hardware module of described scheduling unit control is carried out the modulation treatment of Frame is: send the beginning framing signals, the wait framing procedure finishes, send beginning constellation mapping signal, wait for that the constellation mapping process finishes, send beginning inverse fast fourier transform signal, wait for that the inverse fast fourier transform process finishes.
10, dispatching method as claimed in claim 7, it is characterized in that, in the described step (d), the flow process that described each hardware module of described scheduling unit control is carried out the demodulation process of synchronization frame is: send beginning fast fourier transform signal, the wait fast fourier transform finishes, send the beginning constellation and separate mapping signal, wait for that the constellation mapping process finishes; The flow process that described each hardware module of described scheduling unit control is carried out the demodulation process of Frame is: send beginning fast fourier transform signal, the wait fast fourier transform finishes, send the beginning constellation and separate mapping signal, wait for that the constellation mapping process finishes, send and begin to separate frame signal, wait for that separating the frame process finishes.
11, dispatching method as claimed in claim 7, it is characterized in that, described memory cell respectively has two microcode tables at transmitter side and receiver side, in the described step (c), described scheduling unit earlier by the table switch-over control signal from two microcode tables of transmitter side or from two microcode tables of receiver side, select to read wherein one, reading command therefrom again.
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