CN100512004C - An automatic failure detection and removal circuit for plate-level single grain crossbar lock - Google Patents
An automatic failure detection and removal circuit for plate-level single grain crossbar lock Download PDFInfo
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- CN100512004C CN100512004C CNB2007101185433A CN200710118543A CN100512004C CN 100512004 C CN100512004 C CN 100512004C CN B2007101185433 A CNB2007101185433 A CN B2007101185433A CN 200710118543 A CN200710118543 A CN 200710118543A CN 100512004 C CN100512004 C CN 100512004C
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Abstract
本发明公开了一种板级单粒子闩锁故障自动检测与解除电路，是由电压比较器、三个模拟开关、与门和三个二极管以及电阻电容组成的模拟电路。电压比较器对接收的三路取样电压分别与三路参考电压作比，获得各路是否产生闩锁效应的判断依据，并将三个判断依据送入与门；与门对接收的闩锁故障判断信号进行与处理，输出逻辑信号用于驱动各模拟开关的接通或断开，从而使负载得到保护。该电路是由正电源和负电源混合供电的多电源电路，不管是正电源供电的器件发生闩锁效应还是负电源供电的器件发生闩锁效应，电压比较器都能正确地识别出闩锁故障并控制模拟开关切断全部电源的供电通路。只有当全部闩锁故障解除后，供电通路才能同时接通。
The invention discloses a board-level single-event latch fault automatic detection and release circuit, which is an analog circuit composed of a voltage comparator, three analog switches, an AND gate, three diodes, and resistors and capacitors. The voltage comparator compares the received three-way sampling voltage with the three-way reference voltage to obtain the judgment basis for whether each circuit has a latch-up effect, and sends the three judgment basis to the AND gate; The judgment signal is carried out and processed, and the output logic signal is used to drive the on or off of each analog switch, so that the load is protected. The circuit is a multi-supply circuit powered by a mix of positive and negative power supplies. No matter whether the device powered by the positive power supply has a latch-up effect or the device powered by a negative power supply has a latch-up effect, the voltage comparator can correctly identify the latch-up fault and The analog switch is controlled to cut off the power supply paths of all power supplies. Only when all the latch faults are removed, the power supply paths can be connected at the same time.
Description
Technical field
The present invention relates to a kind of be applicable to automatic detection of the plate level single event latch-up fault in the detecting signal unit and relieving circuit on the spacecraft of using in the space.
Background technology
Space flight practice shows: single particle effect is one of major incentive of spacecraft operation irregularity and fault, is having a strong impact on the safety to the significant all kinds of spacecrafts of national defence and economic construction.(single eventlatch-up is a kind of of single particle effect SEL) to single event latch-up, and electronic circuit part most probable generation single event latch-up effect is cmos device in the spacecraft.May be subjected to the bombardment of heavy particle when spacecraft flies across the Atlantic the sky, negative magnetic region (40 ° in west longitude), solar proton event and galactic comic ray all contain a large amount of high energy charged particles in addition.When single high energy charged particles is hit cmos device, the transient current that incident produces triggers SCR structure and makes its conducting, because silicon controlled positive feedback characteristic constantly increases electric current, enter big regeneration of current state, promptly cause breech lock, can be for some cmos device breech lock electric current up to order of amps.In case cmos circuit is in latch mode, both ends of power just is in the state that is close to short circuit, the big electric current that the generation latch portion flows through causes the device local temperature to raise, the too high meeting of temperature causes the device permanent damage, so not only make the cmos circuit can't operate as normal, also can destroy the operating state of other circuit on the same circuit board simultaneously.In case the safety that the single event latch-up effect might threaten spacecraft takes place, therefore must take counter-measure at the cmos circuit breech lock fault in the spacecraft.
In order to satisfy the systemic-function requirement, the supply power voltage of electronic devices and components often is not single on the circuit board, but two kinds or more of supply power voltage.When certain device generation breech lock fault, can block the supply access that this device uses by the testing circuit drive analog switch, be subjected to the damage of localized hyperthermia to prevent its internal structure.But there is the power supply of some devices not single, and some device also has specific (special) requirements to the order that turns on and off of power supply, may cause damage to device during the power supply of cutoff, therefore safer method is: when certain device generation breech lock, all power paths on the circuit board are cut off simultaneously; Behind clear-latch, connect all power supplies simultaneously.So both prevent the device localized hyperthermia damage that breech lock may bring, also prevented the damage that power supply order violation requirement on devices is brought.Based on this demand, the invention provides a kind of plate level single event latch-up fault and detect automatically and relieving circuit, this circuit is applicable to that the circuit board level breech lock fault of hybrid power supply detects automatically and removes, and particularly comprises the circuit board of positive supply and negative supply simultaneously.
Summary of the invention
The present invention is that a kind of plate level single event latch-up fault detects and relieving circuit automatically, the technical scheme that adopts is: circuit board employing+5V, + 3.3V and-5V power supply power supply, each supply power voltage and reference voltage respectively by sampling resistor insert voltage comparator, with door, by driving the break-make of three analog switches with the output of door, thereby connect and cut off the power supply of load, play the purpose that single event latch-up detects and removes.
The invention discloses a kind of plate level single event latch-up fault and automatically detect and relieving circuit, the analog circuit of forming by voltage comparator, three analog switches, with door and three diodes and resistance capacitance.Voltage comparator is made ratio with three road reference voltages respectively to three tunnel sampling voltages that receive, and obtains the basis for estimation whether each road produces latch-up, and three bases for estimation are sent into and door; With door the breech lock fault judgement signal that receives is carried out and processing, output logic signal is used to drive being switched on or switched off of each analog switch, thereby load is protected.This circuit is the many power circuits by positive supply and negative supply hybrid power supply, no matter be the device generation latch-up of positive supply power supply or the device generation latch-up of negative supply power supply, voltage comparator can both correctly identify the breech lock fault and control the supply access that analog switch cuts off whole power supplys.Have only after whole breech lock trouble shootings, supply access could be connected simultaneously.
+ 5V power supply is exported the first voltage f after first sample resistance, first sampling voltage
1Give voltage comparator, first sampling voltage is the A electric by first analog switch simultaneously; + 5V power supply is exported the first reference voltage f behind first divider resistance, first reference voltage
2Give voltage comparator; + 3.3V power supply is exported the second voltage f after second sample resistance, second sampling voltage
3Give voltage comparator, second sampling voltage is the B electric by second analog switch simultaneously; + 3.3V power supply is exported the second reference voltage f behind second divider resistance, second reference voltage
4Give voltage comparator;-5V power supply is exported tertiary voltage f after the 3rd sample resistance, the 3rd sampling voltage
5Give voltage comparator, the 3rd sampling voltage is the C electric by the 3rd analog switch simultaneously;-5V power supply is exported the 3rd reference voltage f behind the 3rd divider resistance, the 3rd reference voltage
6Give voltage comparator; Voltage comparator is made ratio with three road reference voltages respectively to three tunnel sampling voltages that receive, and obtains the basis for estimation whether each road produces latch-up, and this basis for estimation is sent into and door; With door the breech lock fault judgement signal that receives is carried out and handle, output logic signal is used to drive being switched on or switched off of first analog switch, second analog switch, the 3rd analog switch, thereby load is protected.
Plate level single event latch-up fault of the present invention detects automatically and the main feature of relieving circuit is: (1) circuit design is simple, the employing analog circuit is built, the main devices that relates to have only voltage comparator LM139AJRQMLV, with door a CD54HC11F3A, analog switch ADG801, MAX4690, diode 1N3600 and some resistance capacitances; (2) be easy to expand to adapt to the circuit board of the demand of different electrical power number, particularly positive supply and negative supply hybrid power supply.Comprise three groups of identical three inputs and door with door CD54HC11F3A, utilize a chip can expand to the situation of handling the power supply of 7 road power supplys; (3) owing to do not pass through any processor or delay circuit, as long as each power supply service restoration is normal, this circuit just can recover power supply at once to powering in the plate; (4) breech lock fault detect and removing function are rolled into one, alleviated the complexity of circuit, avoided the taking of processor limited resources adapted to the space demands of applications.
Description of drawings
Fig. 1 is the structured flowchart of automatic detection of plate level single event latch-up fault of the present invention and relieving circuit.
Fig. 2 is the circuit theory diagrams of automatic detection of plate level single event latch-up fault of the present invention and relieving circuit.
Embodiment
The present invention will be further described below in conjunction with drawings and Examples.
See also shown in Figure 1; the present invention is that a kind of plate level single event latch-up fault detects and relieving circuit automatically; this circuit application and door chip D4, voltage comparator and three diodes (diode V1, diode V2, diode V3); the output spike potential that three diodes have played to make voltage comparator is not less than the forward conduction voltage of diode, has played the effect of limited amplitude protection voltage comparator.Whether the load that judge to insert power supply by voltage comparator latch phenomenon occurs, and produces and judge that signal is sent to and door, with door according to the breech lock fault judgement signal that receives, drive all analog switches that link to each other with its output and make corresponding change action; Analog switch switches on or off the power supply of corresponding power supply to the protected circuit intralamellar part according to coupled and door output signal.By change with door input number and with the gate logic combining form, can finish the detection and the releasing of the breech lock fault of different electrical power number.
+ 5V power supply is exported the first voltage f after first sample resistance, first sampling voltage
1Give voltage comparator, first sampling voltage is the A electric by first analog switch simultaneously; + 5V power supply is exported the first reference voltage f behind first divider resistance, first reference voltage
2Give voltage comparator;
+ 3.3V power supply is exported the second voltage f after second sample resistance, second sampling voltage
3Give voltage comparator, second sampling voltage is the B electric by second analog switch simultaneously; + 3.3V power supply is exported the second reference voltage f behind second divider resistance, second reference voltage
4Give voltage comparator;
-5V power supply is exported tertiary voltage f after the 3rd sample resistance, the 3rd sampling voltage
5Give voltage comparator, the 3rd sampling voltage is the C electric by the 3rd analog switch simultaneously;-5V power supply is exported the 3rd reference voltage f behind the 3rd divider resistance, the 3rd reference voltage
6Give voltage comparator;
Voltage comparator is made ratio with three road reference voltages respectively to three tunnel sampling voltages that receive, and obtains the basis for estimation whether each road produces latch-up, and three bases for estimation are sent into and door;
With door the breech lock fault judgement signal that receives is carried out and processing, output logic signal is used to drive being switched on or switched off of each analog switch, thereby load is protected.
Through voltage comparator do than after basis for estimation, and with door in the processing procedure of logical AND is described in detail as follows: (one) voltage comparator is to the first voltage f
1With the first reference voltage f
2Make ratio, whether produce the basis for estimation of latch-up under the acquisition+5V power supply supply power mode, and this basis for estimation is sent into and door; (2) voltage comparator is to the second voltage f
3With the second reference voltage f
4Make ratio, whether produce the basis for estimation of latch-up under the acquisition+3.3V power supply supply power mode, and this basis for estimation is sent into and door; (3) voltage comparator is to tertiary voltage f
5With the 3rd reference voltage f
6Make ratio, whether produce the basis for estimation of latch-up under the acquisition-5V power supply supply power mode, and this basis for estimation is sent into and door.With door above-mentioned three tunnel bases for estimation that receive are made logical AND and handle the digital control amount f that output is used to control first analog switch
1+2Give first analog switch, be used to control the digital control amount f of second analog switch
3+4Give second analog switch, be used to control the digital control amount f of the 3rd analog switch
5+6Give the 3rd analog switch; First analog switch is according to digital control amount f
1+2Control first sampling voltage and give the power supply of A load; Second analog switch is according to digital control amount f
3+4Control second sampling voltage and give the power supply of B load; The 3rd analog switch is according to digital control amount f
5+6Control the 3rd sampling voltage and give the power supply of C load.
See also shown in Figure 2ly, in the present invention, voltage comparator is chosen the LM139AJRQMLV chip, choose the CD54HC11F3A chip with door, first analog switch is chosen the ADG801 chip, and second analog switch is chosen the ADG801 chip, and the 3rd analog switch is chosen the MAX4690 chip.
Plate level single event latch-up fault detects with each terminal of relieving circuit automatically and is connected to:
It is as follows that each terminal of voltage comparator N1 connects situation: positive power source terminal 3 connects with+5V power supply, and and simulate between the ground and be connected with capacitor C 1; Negative power end 12 connects with-5V power supply, and and simulation ground between be connected with capacitor C 2; Be connected with resistance R 4 between the end 1 of the normal phase input end 5 and the first analog switch D1; Inverting input 4 and+be connected with resistance R 1 between the 5V power supply, and and simulation ground between be connected with resistance R 2; Output 2 and+be connected with resistance R 5 between the 5V power supply, and with end 1 short circuit of door D4; Be connected with resistance R 9 between the end 1 of the normal phase input end 7 and the second analog switch D2; Inverting input 6 and+be connected with resistance R 6 between the 5V power supply, and and simulation ground between connection electrical resistance R7; Output 1 and+be connected with resistance R 10 between the 5V power supply, and with end 2 short circuits of door D4; Normal phase input end 9 and simulation are connected with resistance R 15 between the ground, and and a 5V power supply between be connected with resistance R 12; Be connected with resistance R 13 between the end 9 of inverting input 8 and the 3rd analog switch D3; Output 14 and+be connected with resistance R 14 between the 5V power supply, and with end 13 short circuits of door D4;
It is as follows that each terminal of the first analog switch D1 connects situation: end 1 and+be connected with resistance R 3 between the 5V power supply, end is 2 for the A load provides+the 5V power supply, and end 3 connects simulation ground, end 4 with connect with the end 12 of door D4, end 6 connects with+5V power supply, and and simulate between the ground and be connected with capacitor C 3;
It is as follows that each terminal of the second analog switch D2 connects situation: end 1 and+the 3.3V power supply between connection electrical resistance R8, end is 2 for the B load provides+the 3.3V power supply, and end 3 connects simulation ground, end 4 with connect with the end 12 of door D4, end 6 connects with+5V power supply, and and simulate between the ground and be connected with capacitor C 4;
It is as follows that each terminal of the 3rd analog switch D3 connects situation: end 2 with hold 7 short circuits after with connect with the end 12 of door D4, hold 4 external-5V power supplys, and and being connected with capacitor C 5 between the simulation ground, end 5 connects simulation ground, end 9 and end 16 short circuits, and hold 16 and-be connected with resistance R 11 between the 5V power supply, end 11 and end 14 short circuits hold 14 for the C load provides-the 5V power supply, end 12 and end 13 short circuits, end 13 connects+the 5V power supply, and and simulation ground between be connected with capacitor C 6;
The positive termination simulation ground of diode V1, negative terminal connects 2 ends of voltage comparator N1;
The positive termination simulation ground of diode V2, negative terminal connects 1 end of voltage comparator N1;
The positive termination simulation ground of diode V3, negative terminal connects 14 ends of voltage comparator N1;
With end 14 external+5V power supplys of door D4, end 3, end 4, end 5, end 7, end 9, end 10, end 11 connect simulation ground.
The breech lock of three power supply parts detects with the releasing mechanism analysis as follows:
Under the normal running conditions, 5 ends of voltage comparator N1 are slightly higher than 4 terminal voltages, 7 ends are slightly higher than 6 terminal voltages, 9 ends are slightly higher than 8 terminal voltages, by with the effect of door D4 logical AND after, export high level respectively with 12 ends of door D4 and drive the first analog switch D1 simultaneously, 2 ends of 4 ends of the second analog switch D2 and the 3rd analog switch D3,7 ends, make 1 of the first analog switch D1,2 end closures, 1 of the second analog switch D2,2 end closures, 16 ends of the 3rd analog switch D3 and 14 end closures, 9 ends and 11 end closures, thus make insert from the outside+5V, + 3.3V and-the 5V power supply is able to smoothly to load (A load, the B load, the C load) power supply.If some load generation breech locks, cause the electrorheological of one road sampling resistor wherein big, with+the 5V power supply partly is an example, thereby causing the electric current of sampling resistor R3 to increase 1 terminal potential that makes the analog switch D1 that wins, reduces latch-up.Because resistance R 4 does not almost have electric current to pass through, then 5 ends of voltage comparator N1 are identical with 1 terminal potential of the first analog switch D1, to a certain degree cause 5 terminal potentials of voltage comparator N1 to be lower than 4 terminal potentials if the electric current by resistance R 3 increases to, then 2 ends of voltage comparator N1 are output as low level.At this moment; regardless of with 2 ends, the 13 end states of door D4; with 12 ends of door D4 all with output low level; driving disconnects inductive switch with the first analog switch D1 that links to each other with 12 ends of door D4, the second analog switch D2, the 3rd analog switch D3; make the load that breech lock takes place break away from latch mode, thereby play the effect of protection load circuit.Behind 1 end and the disconnection of 2 ends of the first analog switch D1, reduce to zero by the electric current of resistance R 3, thereby 5 terminal potentials of voltage comparator N1 are raise; Behind 1 end and the disconnection of 2 ends of the second analog switch D2, reduce to zero by the electric current of resistance R 8, thereby 7 terminal potentials of voltage comparator N1 are raise; After 14 ends of the 3rd analog switch D3 and 16 ends, 9 ends and 11 ends all disconnect, reduce to zero by the electric current of resistance R 11, thereby 9 terminal potentials of voltage comparator N1 are raise; After 1 end, 2 ends, 14 ends of voltage comparator were all exported high level, the first analog switch D1, the second analog switch D2, the closed once more respective switch of the 3rd analog switch D3 powered to the load.
In the present invention ,+working mechanism of 3.3V power pack with+the 5V power pack is identical.
In the present invention, the working mechanism of-5V power pack analyzes: under the normal operation, 9 terminal potentials of voltage comparator N1 are higher than 8 ends, the 14 ends output high level of voltage comparator N1.When the load generation latch-up of-5V causes the electric current of sampling resistor R11 to increase, make 8 terminal potentials of voltage comparator N1 raise, when it is higher than 9 terminal potentials, the 14 end output low levels of voltage comparator N1, through with the logical AND effect of door D4 after, the switch of controlling the first analog switch D1, the second analog switch D2, the 3rd analog switch D3 with the 12 end output low levels of door D4 disconnects, and makes the load that breech lock takes place break away from breech lock.It recovers electric process and sees also+and the working mechanism of 5V power pack is described.
Claims (4)
1, a kind of plate level single event latch-up fault detects and relieving circuit automatically, it is characterized in that: this circuit application and door chip D4, voltage comparator and three diodes, the output spike potential that three diodes have played to make voltage comparator is not less than the forward conduction voltage of diode, has played the effect of limited amplitude protection voltage comparator; Whether the load that judge to insert power supply by voltage comparator latch phenomenon occurs, and produces and judge that signal is sent to and door, with door according to the breech lock fault judgement signal that receives, drive all analog switches that link to each other with its output and make corresponding change action; Analog switch switches on or off the power supply of corresponding power supply to the protected circuit intralamellar part according to coupled and door output signal; By change with door input number and with the gate logic combining form, finish the detection and the releasing of the breech lock fault of different electrical power number;
+ 5V power supply is exported the first voltage f after first sample resistance, first sampling voltage
1Give voltage comparator, first sampling voltage is the A electric by first analog switch simultaneously; + 5V power supply is exported the first reference voltage f behind first divider resistance, first reference voltage
2Give voltage comparator;
+ 3.3V power supply is exported the second voltage f after second sample resistance, second sampling voltage
3Give voltage comparator, second sampling voltage is the B electric by second analog switch simultaneously; + 3.3V power supply is exported the second reference voltage f behind second divider resistance, second reference voltage
4Give voltage comparator;
-5V power supply is exported tertiary voltage f after the 3rd sample resistance, the 3rd sampling voltage
5Give voltage comparator, the 3rd sampling voltage is the C electric by the 3rd analog switch simultaneously;-5V power supply is exported the 3rd reference voltage f behind the 3rd divider resistance, the 3rd reference voltage
6Give voltage comparator;
Voltage comparator is made ratio with three road reference voltages respectively to three tunnel sampling voltages that receive, and obtains the basis for estimation whether each road produces latch-up, and this basis for estimation is sent into and door;
With door the breech lock fault judgement signal that receives is carried out and handle, output logic signal is used to drive being switched on or switched off of first analog switch, second analog switch, the 3rd analog switch, thereby load is protected.
2, plate level single event latch-up fault according to claim 1 detects and relieving circuit automatically, it is characterized in that: voltage comparator is chosen the LM139AJRQMLV chip, choose the CD54HC11F3A chip with door, first analog switch is chosen the ADG801 chip, second analog switch is chosen the ADG801 chip, and the 3rd analog switch is chosen the MAX4690 chip.
3, plate level single event latch-up fault according to claim 1 detects and relieving circuit automatically, it is characterized in that the hardware connection of each circuit is:
The positive power source terminal 3 of voltage comparator N1 connects with+5V power supply, and and simulation ground between be connected with capacitor C 1; Negative power end 12 connects with-5V power supply, and and simulation ground between be connected with capacitor C 2; Be connected with resistance R 4 between the end 1 of the normal phase input end 5 and the first analog switch D1; Inverting input 4 and+be connected with resistance R 1 between the 5V power supply, and and simulation ground between be connected with resistance R 2; Output 2 and+be connected with resistance R 5 between the 5V power supply, and with end 1 short circuit of door D4; Be connected with resistance R 9 between the end 1 of the normal phase input end 7 and the second analog switch D2; Inverting input 6 and+be connected with resistance R 6 between the 5V power supply, and and simulation ground between connection electrical resistance R7; Output 1 and+be connected with resistance R 10 between the 5V power supply, and with end 2 short circuits of door D4; Normal phase input end 9 and simulation are connected with resistance R 15 between the ground, and and-be connected with resistance R 12 between the 5V power supply; Be connected with resistance R 13 between the end 9 of inverting input 8 and the 3rd analog switch D3; Output 14 and+be connected with resistance R 14 between the 5V power supply, and with end 13 short circuits of door D4;
It is as follows that each terminal of the first analog switch D1 connects situation: end 1 and+be connected with resistance R 3 between the 5V power supply, end is 2 for the A load provides+the 5V power supply, and end 3 connects simulation ground, end 4 with connect with the end 12 of door D4, end 6 connects with+5V power supply, and and simulate between the ground and be connected with capacitor C 3;
It is as follows that each terminal of the second analog switch D2 connects situation: end 1 and+the 3.3V power supply between connection electrical resistance R8, end is 2 for the B load provides+the 3.3V power supply, and end 3 connects simulation ground, end 4 with connect with the end 12 of door D4, end 6 connects with+5V power supply, and and simulate between the ground and be connected with capacitor C 4;
It is as follows that each terminal of the 3rd analog switch D3 connects situation: end 2 with hold 7 short circuits after with connect with the end 12 of door D4, hold 4 external-5V power supplys, and and being connected with capacitor C 5 between the simulation ground, end 5 connects simulation ground, end 9 and end 16 short circuits, and hold 16 and-be connected with resistance R 11 between the 5V power supply, end 11 and end 14 short circuits hold 14 for the C load provides-the 5V power supply, end 12 and end 13 short circuits, end 13 connects+the 5V power supply, and and simulation ground between be connected with capacitor C 6;
The positive termination simulation ground of diode V1, negative terminal connects 2 ends of voltage comparator N1;
The positive termination simulation ground of diode V2, negative terminal connects 1 end of voltage comparator N1;
The positive termination simulation ground of diode V3, negative terminal connects 14 ends of voltage comparator N1;
With end 14 external+5V power supplys of door D4, end 3, end 4, end 5, end 7, end 9, end 10, end 11 connect simulation ground.
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| CNB2007101185433A CN100512004C (en) | 2007-07-09 | 2007-07-09 | An automatic failure detection and removal circuit for plate-level single grain crossbar lock |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007101185433A CN100512004C (en) | 2007-07-09 | 2007-07-09 | An automatic failure detection and removal circuit for plate-level single grain crossbar lock |
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| CN100512004C true CN100512004C (en) | 2009-07-08 |
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| US11942857B2 (en) | 2021-12-02 | 2024-03-26 | Industrial Technology Research Institute | Power supply |
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| CN102064814B (en) * | 2010-11-26 | 2012-09-05 | 中国电子科技集团公司第五十八研究所 | Single event resistant latch structure based on state saving mechanism |
| US9214198B2 (en) * | 2014-04-30 | 2015-12-15 | Sandisk Enterprise Ip Llc | Continuous capacitor health monitoring and power supply system |
| CN105823977A (en) * | 2015-07-28 | 2016-08-03 | 维沃移动通信有限公司 | Latch detection circuit and integrated circuit |
| CN106655078B (en) * | 2016-10-25 | 2018-09-11 | 哈尔滨工业大学 | Integrated circuit latch protection system and method under a kind of space environment |
| CN107608332A (en) * | 2017-09-04 | 2018-01-19 | 西安微电子技术研究所 | A kind of accelerator simulation source single particle radiation electric source for test purposes switching control |
| CN111679937B (en) * | 2020-06-01 | 2023-02-24 | 西安微电子技术研究所 | Single event lock release method based on local potential collapse |
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| 空间单粒子锁定及防护技术研究. 杨世宇等.核电子学与探测技术，第27卷第3期. 2007 * |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11942857B2 (en) | 2021-12-02 | 2024-03-26 | Industrial Technology Research Institute | Power supply |
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