CN100511164C - Method for using information of synchronous serial interface output and asynchronous serial port debugging on DSP - Google Patents

Abstract

This invention provides a kind of method of using the timing serial port to output the asynchronous serial port debug information on the DSP and constructs the asynchronous serial port data frame by using the structure corresponding relationship of the synchronous serial port and the asynchronous serial port data frame and the corresponding relationship of bit clock of the synchronous serial port and the baud rate of the asynchronous serial port; at the same time synchrony the frame of synchronous serial port on the DSP and logical operate the base pin which is used to deliver the data and extend the output values making it met the time sequence of the asynchronous serial port and output the asynchronous serial port debug information. Comparing with the present technology it overcomes the defect that there is no debug information output channel during the reality process for the DSP; it has the well reality and it can capture the abnormal station for the DSP and offer the trace of the location problem; the UART baud rate can be modified and it is convenience to the user.

Description

On DSP, utilize the method for information of synchronous serial interface output and asynchronous serial port debugging

Technical field

The present invention relates to utilize on the inherent DSP of digital signal processor application the method for information of synchronous serial interface output and asynchronous serial port debugging, relate more specifically to a kind ofly on the DSP that TI company produces, utilize synchronous serial interface McBsp (Multichannel Buffered Serial Port multichannel buffer serial line interface) to make up asynchronous serial port UART (Universal Asynchronous Receiver/Transmitter universal asynchronous receiving-transmitting serial ports), and with the method for its output Debugging message.

Background technology

In the performance history of DSP (Digital Singnal Processor digital signal processor) chip, the output of its Debugging message is a problem of making us paying close attention to always, particularly is even more important in reproduction and orientation problem.Can export Debugging message by the jtag mouth with emulator in early days what DSP developed, having arrived the commercialization stage can be exported by main frame by host interface for the Debugging message of Host-Slave----principal and subordinate machine pattern DSP, and for the mode that the Standalone----single cpu mode generally adopts daily record to preserve, just Debugging message is kept among the FLASH.This dual mode exists significant disadvantages: the former is subject to host interface, if the unusual Debugging message of this path then can't normally export; The latter is effective poor, and daily record needs to read with emulator afterwards.

Asynchronous serial port UART is the first-selections of many modern processors as Debugging message output with its convenient and swift flexible characteristic.In addition, the EDMA of DSP (Enhanced Direct Memory Access enhancement mode direct memory access) need not CPU and intervenes the work that gets final product after startup, even also be like this under the situation that DSP crashes.

So based on above-mentioned technical background, the present invention need realize asynchronous serial port UART operation by existing synchronous serial interface McBsp in dsp chip.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of method of utilizing synchronous serial interface McBsp output and asynchronous serial port UART Debugging message on DSP.Pin and clock to McBsp are done some changes and configuration, thereby make its transmission time sequence that meets UART construct asynchronous serial port; Some key messages are concentrated print in the transmission buffer zone of McBsp, be responsible for UART (seeing outside the DSP) output that just makes up from McBsp by EDMA.

In order to address the above problem, the invention provides a kind of method of on DSP, utilizing information of synchronous serial interface output and asynchronous serial port debugging, utilize the structure corresponding relation of the Frame of synchronous serial interface and asynchronous serial port, and the corresponding relation of the baud rate of the bit clock of synchronous serial interface and asynchronous serial port, construct the asynchronous serial-port data frame; Simultaneously the frame synchronizing signal of the last synchronous serial interface of DSP and the Debugging message of transmission are carried out the logical and operation, and according to construct the asynchronous serial-port data frame to output Debugging message expand, make described Debugging message meet the asynchronous serial port sequential, output is based on the Debugging message of asynchronous serial port.

Further, method of the present invention is characterized in that, described synchronous serial interface comprises: McBsp; Described asynchronous serial port comprises: UART;

Further, method of the present invention is characterized in that, described synchronous serial interface McBsp data frame structure comprises: the McBsp synchronization frame of the low level frame synchronization of 1 bit and 6 to 12 bits, and the baud rate of its bit clock and UART is with frequently;

Further, method of the present invention is characterized in that, described asynchronous serial port UART data frame structure comprises: 1 bit start bit, 5 to 8 Bit data positions, the optional parity check bit of 1 bit, and 0.5 bit or 1 to 2 bit position of rest;

Further, method of the present invention is characterized in that, the structure corresponding relation of the Frame of described asynchronous serial port UART and synchronous serial interface McBsp comprises: the low level frame synchronization of 1 bit, the 1 bit start bit of corresponding UART; The McBsp synchronization frame of 6 to 12 bits, 5 to the 8 Bit data positions of corresponding UART, the optional parity check bit of 1 bit and 0.5 bit or 1 to 2 bit position of rest;

Further, method of the present invention is characterized in that, the corresponding relation of the baud rate of the bit clock of described synchronous serial interface McBsp and asynchronous serial port UART comprises: the same frequency of the baud rate of the bit clock of synchronous serial interface McBsp and asynchronous serial port UART;

Further, method of the present invention, it is characterized in that, described structure asynchronous serial-port data frame, comprise: according to above-mentioned with the structure corresponding relation of the Frame of relation and described two kinds of serial ports frequently, adopting broadening synchronous clock method, is original 8 times by the bit clock that improves synchronous serial interface McBsp, has obtained the frame synchronization with asynchronous serial port UART start bit same widths;

Further, method of the present invention is characterized in that, the bit clock of described synchronous serial interface McBsp is obtained by DSP major clock frequency division, and this moment, the width of frame synchronization was the wide multiple of serial data word;

Further, method of the present invention is characterized in that, described output valve is expanded, and comprising:

Add 0 data of 8 bits at the front end of output valve, the rear end adds 1 data of 8 bits.

Adopt the method for the invention, compared with prior art, overcome the drawback that does not have the Debugging message output channel in the DSP real process, reliable and stable debugging output channel is provided; Ageing property is good, can catch DSP and state when unusual occur, and the clue of orientation problem is provided; The UART baud rate can be changed, and is user-friendly to.

Description of drawings

Fig. 1 is the design diagram of Host-Slave pattern in the dsp system;

Fig. 2 is the design diagram of Standalone pattern in the dsp system;

Fig. 3 is the corresponding relation synoptic diagram of UART serial ports sequential and McBsp sequential;

Fig. 4 is the synoptic diagram of structure UART asynchronous serial port in the embodiment of the invention;

Fig. 5 is the synoptic diagram of data expansion process in the embodiment of the invention;

Fig. 6 utilizes synchronous serial interface McBsp structure asynchronous serial port UART to export the structural representation of Debugging message on DSP in the embodiment of the invention;

Fig. 7 is the workflow diagram of the embodiment of the invention shown in Figure 6.

Embodiment

The present invention is in order to solve the drawback that conventional solution exists, further set forth a kind of method of on DSP, utilizing synchronous serial interface McBsp output and asynchronous serial port UART Debugging message of the present invention by following specific embodiment, below embodiment is described in detail, but not as a limitation of the invention.

As shown in Figure 1, be the design diagram of Host-Slave pattern in the dsp system.Wherein 101 is the HOST chips that have network interface 103, and by Jtag 104 output Debugging message, commercialization post debugging information is responsible for output by host interface by HOST 101 at initial stage of development DSP 102.

As shown in Figure 2, be the design diagram of Standalone pattern in the dsp system.By Jtag 202 output Debugging message, commercialization post debugging information generally adopts the method for preserving daily record at initial stage of development DSP 201, and daily record is kept in the FLASH storage medium 203.

As shown in Figure 3, be the corresponding relation synoptic diagram of UART serial ports sequential and McBsp sequential.Wherein, the 301st, the sequential chart of UART serial ports, UART one frame data are made up of the position of rest (this example is 1bit) of the low level start bit of 1bit, 5～8bit data bit, the optional parity check bit of 1bit, 1～2bit high level;

302～304th, corresponding McBsp sequential, wherein 302 is bit clocks, frequently same with the baud rate of UART; The 303rd, frame synchronizing signal, low level 1bit is wide, high level n+2bit wide (n=5～8); 304 is frame McBsp data, and width is mbit (m=n+3).

As seen, complete frame UART data are made up of 1bit start bit, 5～8bit data bit, the optional parity check bit of 1bit, 1～2bit (desirable 0.5bit) position of rest.Such data frame structure can be interpreted as comprising the McBsp synchronization frame of 1bit low level frame synchronization (start bit), 6～12 data (data bit+parity check bit+position of rest) for McBsp, the baud rate of bit clock and UART is with frequently.

As shown in Figure 4, being the synoptic diagram of structure UART asynchronous serial port in the embodiment of the invention, is example with the UART of 1bit start bit, 8bit data bit, no parity position, 1bit position of rest.Wherein, the 401st, the pin configuration of the last McBsp of DSP goes up the frame synchronization of McBsp and carries out the logical and operation with the pin that sends data to DSP;

402 be in 401 through and obtain the UART signal that signal is promptly constructed behind the door;

Bit clock 403 is and the clock of URAT baud rate with frequency;

Bit clock 404 is obtained by the major clock frequency division of DSP and as the clock source of McBsp module, the frame synchronization width must guarantee this moment be the wide multiple of serial data word, and such as the wide data of 8bit, the frame synchronization width should be that 8bit is wide;

The 405th, meet the frame synchronization output of UART sequential, low level is effective;

The 406th, through expanded data, the data of the actual corresponding 1byte of each byte among byte0～byte7, each byte is complete 0 or is complete 1, adds 1 complete 0 byte before this 8byte, adds 1 complete 1 byte afterwards, to constitute the sequential of UART.

As shown in Figure 5, be the synoptic diagram of data expansion process in the embodiment of the invention. In H be example, the data of having demonstrated the expansion process of data and finally in buffer zone, having needed to store, the ASCII character of H is 0x48, corresponding binary number is 01001000b.Start bit that data after the expansion also need be expanded before depositing buffer zone in and position of rest.That is to say original character of every sign, need in buffer zone, distribute the storage space of 10byte.

As shown in Figure 6, be on DSP, to utilize synchronous serial interface McBsp structure asynchronous serial port UART to export the structural representation of Debugging message in the embodiment of the invention.Form by the DSP 501, level conversion device 502, connection PC and the DB9 cable of UART mouth, the display terminal PC 504 of Debugging message that utilize synchronous serial interface McBsp to make up UART.Each important information collection module is responsible for collecting the Debugging message that needs output in DSP 501, through delivering to the buffer zone of McBsp after the data expansion, is responsible for from the UART mouth output of constructing by EDMA; Before the input of PC serial ports, need through level conversion device 502, be the CMOS level conversion RS232 level; Be connected to DB9 stube cable 503 through the lead-in wire after the level conversion then; Deliver to the display terminal PC 504 of Debugging message at last.The input of the GPIO pin in 501 is read in when the DSP initialization as UART baud rate preset value, the relation such as the following table of the value of GPIO1～0 and UART baud rate and McBsp bit clock:

GPIO1～0	The UART baud rate	The McBsp bit clock
			00	9600	76800
01	19200	153600
			10	38400	307200
11	115200	460800

In the last table, adopt the method for broadening synchronous clock, promptly improve the method for bit clock: bit clock rises to original 8 times; The data of original like this 1bit, needing broadening is 8bit, and 0 becomes 8bit0 (0x00), and 1 becomes 8bit1 (0xFF).From the DSP inboard, still be synchronous serial interface McBsp, and, be exactly the UART serial ports that transmitting terminal is with regard to 1 line in the DSP outside.

PC 504 also can send the order that changes baud rate to DSP 501 by the DB9 cable, in the hope of reaching the purpose of dynamic change baud rate.

As shown in Figure 7, be the workflow diagram of the embodiment of the invention shown in Figure 6.May further comprise the steps:

Step 601, DSP reads in the value of GPIO input pin earlier, calculates corresponding McBsp bit clock, frame synchronization frequency;

Step 602, according to the clock that calculates, frame synchronization frequency, configuration McBsp empties the transmission buffer zone, starts McBsp.UART mouth that DSP outside structure good on can only obtain have only start bit and position of rest, data bit complete empty signal owing to do not have information gathering to the transmission buffer zone this moment;

Step 603, DSP has a plurality of important information bleeding points and collects Debugging message in operational process, and these information comprise stack, important register etc.;

Step 604 after Debugging message process character stringization, the expansion assembly unit, is delivered to the transmission buffer zone.Buffer zone is because be regularly output, and Debugging message does not regularly write, so information output is not uniform.In the time interval that buffer zone switches,, can repeat to send the information in the buffer zone if there is not new Debugging message to write.Utilize this characteristic, can catch the state of DSP when unusual, the clue of orientation problem is provided;

In fact step 605, the Debugging message after assembly unit is good are exactly that the frame synchronizing signal that sends data and McBsp is carried out and operation by the good UART mouth output of structure;

Step 606, the output of UART mouth is delivered to the DB9 cable as level conversion;

Step 607, the DB9 cable send Debugging message PC to show, need the empty information some redundancies reject before demonstration.

Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.

Claims (9)

1, a kind of method of on DSP, utilizing information of synchronous serial interface output and asynchronous serial port debugging, it is characterized in that, utilize the structure corresponding relation of the Frame of synchronous serial interface and asynchronous serial port, and the corresponding relation of the baud rate of the bit clock of synchronous serial interface and asynchronous serial port, construct the asynchronous serial-port data frame; Simultaneously the frame synchronizing signal of the last synchronous serial interface of DSP and the Debugging message of transmission are carried out the logical and operation, and according to construct the asynchronous serial-port data frame to output Debugging message expand, make described Debugging message meet the asynchronous serial port sequential, output is based on the Debugging message of asynchronous serial port.

2, the method for claim 1 is characterized in that, described synchronous serial interface comprises: McBsp; Described asynchronous serial port comprises: UART.

3, method as claimed in claim 2 is characterized in that, described synchronous serial interface McBsp data frame structure comprises:

The McBsp synchronization frame of the low level frame synchronization of 1 bit and 6 to 12 bits, the baud rate of its bit clock and UART is with frequently.

4, method as claimed in claim 3 is characterized in that, described asynchronous serial port UART data frame structure comprises:

1 bit start bit, 5 to 8 Bit data positions, the optional parity check bit of 1 bit, and 0.5 bit or 1 to 2 bit position of rest.

5, method as claimed in claim 4 is characterized in that, the structure corresponding relation of the Frame of described asynchronous serial port UART and synchronous serial interface McBsp comprises:

The low level frame synchronization of 1 bit, the 1 bit start bit of corresponding UART;

The McBsp synchronization frame of 6 to 12 bits, 5 to the 8 Bit data positions of corresponding UART, the optional parity check bit of 1 bit and 0.5 bit or 1 to 2 bit position of rest.

6, method as claimed in claim 5 is characterized in that, the corresponding relation of the baud rate of the bit clock of described synchronous serial interface McBsp and asynchronous serial port UART comprises:

The same frequency of the baud rate of the bit clock of synchronous serial interface McBsp and asynchronous serial port UART.

7, method as claimed in claim 6 is characterized in that, described structure asynchronous serial-port data frame comprises:

According to above-mentioned with the structure corresponding relation of the Frame of relation and described two kinds of serial ports frequently, adopt broadening synchronous clock method, bit clock by raising synchronous serial interface McBsp is original 8 times, has obtained the frame synchronization with asynchronous serial port UART start bit same widths.

8, method as claimed in claim 7 is characterized in that, the bit clock of described synchronous serial interface McBsp is obtained by DSP major clock frequency division, and this moment, the width of frame synchronization was the wide multiple of serial data word.

9, method as claimed in claim 2 is characterized in that, described output valve is expanded, and comprising:

Add 0 data of 8 bits at the front end of output valve, the rear end adds 1 data of 8 bits.

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