CN110888793A - On-chip code breakpoint debugging method, on-chip processor and chip breakpoint debugging system - Google Patents
On-chip code breakpoint debugging method, on-chip processor and chip breakpoint debugging system Download PDFInfo
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Abstract
The disclosure relates to a method for debugging breakpoints of codes on a chip, a processor on the chip and a system for debugging breakpoints of the chip, wherein the method comprises the following steps: the on-chip processor starts and executes the on-chip code, and an output function is arranged at the breakpoint of the on-chip code; the on-chip processor acquires output information of the output function, wherein the output information is the output information of the output function when the on-chip code is executed to the output function; the on-chip processor stores the output information to an off-chip memory. In the embodiment of the disclosure, according to the output information of the output function stored in the off-chip memory, the on-chip processor can acquire the execution condition of each breakpoint of the on-chip code in real time, so as to achieve the purpose of simultaneously punching a plurality of breakpoints in the on-chip code for debugging, and improve the debugging efficiency of the on-chip code.
Description
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a method for debugging a breakpoint of an on-chip code, an on-chip processor, and a system for debugging a breakpoint of a chip.
Background
In the traditional chip algorithm debugging process, the real-time output of the algorithm result cannot be realized. The result of the whole chip algorithm needs to be copied to other platforms for result output. The debugging process of the chip algorithm cannot be carried out, so that the debugging efficiency of the chip algorithm is low.
Disclosure of Invention
In view of this, the present disclosure provides an on-chip code breakpoint debugging method, an on-chip processor, and a chip breakpoint debugging system, so as to solve the problem of low chip breakpoint debugging efficiency.
According to an aspect of the present disclosure, there is provided an on-chip code breakpoint debugging method, the method including:
the on-chip processor starts and executes the on-chip code, and an output function is arranged at the breakpoint of the on-chip code;
the on-chip processor acquires output information of the output function, wherein the output information is the output information of the output function when the on-chip code is executed to the output function;
the on-chip processor stores the output information to an off-chip memory.
In one possible implementation, the method further includes:
and the on-chip processor determines a breakpoint debugging result of the on-chip code according to the output information in the off-chip memory.
In one possible implementation, the output function includes: a print number function or a print string function.
In one possible implementation, the outputting information includes: preset digital information or character string information, or output information of functions other than the output function in the on-chip code.
In one possible implementation manner, the obtaining, by the on-chip processor, output information of the output function includes:
and the on-chip processor acquires the output information of the output function in the RAM of the on-chip system.
In one possible implementation, the method further includes:
the on-chip processor outputs output information in the off-chip memory.
In one possible implementation, the method further includes:
and the on-chip processor outputs the output information in the off-chip memory by using a driving program.
In one possible implementation, the outputting, by the on-chip processor, output information in the off-chip memory includes:
when the output information in the off-chip memory is updated, the on-chip processor outputs the updated output information.
In one possible implementation, when there is an update in the output information in the off-chip memory, the on-chip processor outputs the updated output information, including:
the on-chip processor queries output information in the off-chip memory by using a first thread;
when the output information is inquired to be updated, the first thread updates the state identifier of the off-chip memory;
the on-chip processor queries the state identifier of the off-chip memory by using a second thread;
and when the state identifier is inquired to be updated, the second thread outputs the updated output information in the off-chip memory.
In one possible implementation, the on-chip processor querying the output information in the off-chip memory using a first thread includes:
the on-chip processor starts the first thread to inquire the output information in the off-chip memory by using a driving program;
the on-chip processor querying the off-chip memory for the status identifier using a second thread, comprising:
the on-chip processor initiates the second thread to query the off-chip memory for the status identification using a HOST program.
In one possible implementation, the state identification of the off-chip memory includes: read identification or unread identification.
In one possible implementation, the outputting, by the on-chip processor, output information in the off-chip memory includes:
the off-chip memory triggers an interrupt function to enter a hardware interrupt state according to the received output information;
the on-chip processor queries a hardware state of the off-chip memory by using a third thread, wherein the hardware state comprises a hardware interrupt state or a hardware non-interrupt state;
and when the state of the off-chip memory is inquired to be a hardware interrupt state, the third thread outputs the output information in the off-chip memory.
According to an aspect of the present disclosure, there is provided an on-chip processor including:
the starting module is used for starting and executing the on-chip code, and an output function is arranged at the breakpoint of the on-chip code;
an output information obtaining module, configured to obtain output information of the output function, where the output information is output information of the output function when the on-chip code is executed to the output function;
and the storage module is used for storing the output information to an off-chip memory.
In one possible implementation, the on-chip processor further includes:
and the breakpoint debugging result determining module is used for determining the breakpoint debugging result of the on-chip code according to the output information in the off-chip memory.
In one possible implementation, the output function includes: a print number function or a print string function.
In one possible implementation, the outputting information includes: preset digital information or character string information, or output information of functions other than the output function in the on-chip code.
In a possible implementation manner, the output information obtaining module includes:
and the on-chip processor acquires the output information of the output function in the RAM of the on-chip system.
In one possible implementation, the on-chip processor further includes:
and the output module is used for outputting the output information in the off-chip memory.
In one possible implementation, the output module includes:
and the first output submodule is used for outputting the output information in the off-chip memory by using a driving program.
In one possible implementation, the output module includes:
and the second output submodule is used for outputting updated output information when the output information in the off-chip memory is updated.
In a possible implementation manner, the second output submodule is configured to:
querying output information in the off-chip memory using a first thread;
when the output information is inquired to be updated, the first thread updates the state identifier of the off-chip memory;
querying a state identifier of the off-chip memory with a second thread;
and when the state identifier is inquired to be updated, the second thread outputs the updated output information in the off-chip memory.
In one possible implementation, querying output information in the off-chip memory using a first thread includes:
starting the first thread by using a driving program to inquire the output information in the off-chip memory;
querying, with a second thread, a status identification of the off-chip memory, comprising:
initiating the second thread with a HOST program to query the state identification of the off-chip memory.
In one possible implementation, the state identification of the off-chip memory includes: read identification or unread identification.
In one possible implementation, the output module includes:
a third output sub-module, configured to query, by using a third thread, a hardware state of the off-chip memory, where the hardware state includes a hardware interrupt state or a hardware non-interrupt state, and the hardware interrupt state of the off-chip memory is a hardware interrupt state in which the off-chip memory triggers an interrupt function to enter according to received output information; and when the state of the off-chip memory is inquired to be a hardware interrupt state, the third thread outputs the output information in the off-chip memory.
According to an aspect of the present disclosure, there is provided a system for debugging a chip point, the system comprising: a breakpoint debug chip and an off-chip memory,
the breakpoint debugging chip comprises the on-chip processor and is used for debugging breakpoints on a chip;
and the off-chip memory is used for storing the output information of the breakpoint debugging chip.
The disclosed embodiments may set the output function at the breakpoint of the on-chip code. When the on-chip processor starts to execute the on-chip code and executes the on-chip code to the output function, the on-chip processor stores the output information to the off-chip memory by acquiring the output information of the output function. According to the output information of the output function stored in the off-chip memory, the on-chip processor can acquire the execution condition of each breakpoint of the on-chip code in real time, the purpose of simultaneously printing a plurality of breakpoints in the on-chip code for debugging can be achieved, and the debugging efficiency of the on-chip code is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 shows a flow diagram of a method for on-chip code breakpoint debugging in accordance with an embodiment of the present disclosure;
FIG. 2 illustrates a flow diagram of a method for on-chip code breakpoint debugging in accordance with an embodiment of the present disclosure;
FIG. 3 illustrates a flow diagram of a method for on-chip code breakpoint debugging in accordance with an embodiment of the present disclosure;
FIG. 4 shows a flow diagram of a method for on-chip code breakpoint debugging in accordance with an embodiment of the present disclosure;
FIG. 5 shows a flowchart of step S51 in a method for debugging breakpoints of code on a chip according to an embodiment of the present disclosure;
FIG. 6 shows a flow diagram of a method for on-chip code breakpoint debugging in accordance with an embodiment of the present disclosure;
FIG. 7 shows a block diagram of an on-chip processor according to an embodiment of the present disclosure;
fig. 8 shows a block diagram of a chip breakpoint debugging system according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Fig. 1 shows a flowchart of an on-chip code breakpoint debugging method according to an embodiment of the present disclosure, and as shown in fig. 1, the on-chip code breakpoint debugging method includes:
in step S10, the on-chip processor starts executing the on-chip code, and an output function is set at a breakpoint of the on-chip code.
In a possible implementation manner, an application program may be written in any language capable of generating machine instructions, such as C language, C + + language, and the on-chip processor may implement the on-chip code breakpoint debugging method in the embodiment of the present disclosure by using the application program. The application may be provided to a system on a chip. The on-chip processor may execute the application when executing the on-chip code.
In one possible implementation, the on-chip code is code that may run on a system-on-chip. A system on a chip may be a hardware system integrated on a single or multiple chips that may run code to implement the logical functions of the code. For example, the on-chip code may include various types of function functions such as kernel functions. The output function may output information without interrupting the execution of code on the chip. The present disclosure does not limit the type and content of the on-chip code. The on-chip processor may initiate execution of the on-chip code in accordance with the startup command.
In one possible implementation, one or more breakpoints may be artificially determined in the on-chip code according to debugging requirements. The output function may be set at a breakpoint of the on-chip code.
In one possible implementation, the output function includes: a print number function or a print string function.
In one possible implementation, the output function may include a print number function. The print number function may be used to print preset numbers or acquired numbers. For example, the preset number is a binary number "01011". When the print number function is executed, the binary number "01011" can be printed.
In one possible implementation, the output function may include a print string function. The print string function may be used to print a preset string, or may be used to print an acquired string.
In one possible implementation, the print number function and the print string function may be set in the on-chip code at the same time. It is also possible to set only one of the print number function and the print character string function in the on-chip code. When the on-chip code includes a plurality of print number functions or a plurality of print string functions, the plurality of print number functions or the plurality of print string functions may be the same or different.
In one possible implementation, an output function is set at a breakpoint of the on-chip code, and the output function includes: and output functions are respectively arranged at a plurality of break points of the on-chip codes.
In one possible implementation, the output function may be set at each break point. The output functions at the multiple break points may be the same or different.
In a possible implementation manner, when the on-chip code executes normally, the output function at each breakpoint can execute normally, and information is output normally. When the on-chip code executes abnormally, an output function related to the code executing the abnormal part cannot normally output information or output information representing the abnormal execution state.
For example, the on-chip code may include a plurality of sub-codes, i.e., sub-code 1, sub-code 2, and sub-code 3 … …. Output functions can be set for each subcode (for example, a break point can be set at the end of the subcode and an output function can be set at the break point), respectively output function 1, output function 2, and output function 3 … …. Each output function may be used to output a preset number. Output function 1 is for outputting a digital "1", output function 2 is for outputting a digital "2", and output function 3 is for outputting a digital "3" … …. In the execution process of the on-chip code, if the sub-code 3 cannot be normally executed and the output function from the output function 3 cannot be normally executed, the output function from the output function 3 cannot normally output information. The output information of the output function of the final on-chip code is only the number "1" and the number "2".
Each output function may also be configured to output an execution state of the corresponding sub-code, and when the sub-code is normally executed, the corresponding output function may output a state value of "0". When the sub-code execution is abnormal, the corresponding output function may output a state value of "1". During execution of the on-chip code, the output function associated with the sub-code executing the exception outputs a state value of "1".
Step S20, the on-chip processor obtains output information of the output function, where the output information is output information of the output function when the on-chip code is executed to the output function.
In one possible implementation, during execution of the on-chip code, the on-chip processor may output information to a Random Access Memory (RAM) of the on-chip system when executing the output function.
In one possible implementation, the obtaining, by an on-chip processor, output information of the output function includes: and the on-chip processor acquires the output information of the output function in the RAM of the on-chip system.
In one possible implementation, the on-chip processor may obtain the output information of the output function in real time in the RAM. The on-chip processor may also periodically retrieve the output information of the output function in the RAM. The on-chip processor may further obtain output information of the output function in the RAM according to the obtaining instruction.
In one possible implementation, the outputting information includes: preset numeric information or character string information.
In one possible implementation, the output function may output preset numeric information or character string information. The same output information may be set for different output functions at different break points, i.e. the same numeric information or character string information is preset. For example, the output information of the output function at each breakpoint is a binary number 1. Different output information, that is, different digital information or character string information, can also be preset for different output functions at different breakpoint points. For example, the output information of the first output function is binary number 1, the output information of the second output function is binary number 2, and so on.
In one possible implementation, the outputting information includes: output information of functions other than the output function in the on-chip code.
In one possible implementation, the output function may output the acquired numeric information or character string information. The output function can acquire the output information of other functions in the on-chip code and output the output information of other functions. For example, on-chip code may be used for operation of a neural network. When the on-chip code is used for completing related calculation of the neural network, a plurality of output functions can be set in the on-chip code and used for outputting intermediate results in the calculation process of the neural network. The neural network may include a plurality of convolutional layers, the output data of each convolutional layer being an intermediate result in the calculation process of the neural network. The on-chip code may include a plurality of functions corresponding to the convolutional layers. In the execution process of the on-chip code, the function corresponding to each convolutional layer may output the output data of each convolutional layer to a preset memory address, and the output function may output the output data of each convolutional layer stored in the preset memory address. For example, the on-chip code may include a convolution operation function 1, a convolution operation function 2, and a convolution operation function 3, which are respectively used for convolution operations of the first to third layers of convolution layers. The on-chip code may store the calculation result of each convolution operation function to a preset storage address. The on-chip code may include an output function corresponding to each convolution operation function, and the output function may output data of each convolution operation function in a preset memory address.
Step S30, the on-chip processor stores the output information to an off-chip memory.
In a possible implementation manner, the on-chip processor may store the output information of the output function acquired in the RAM of the on-chip system to the off-chip memory in real time. The off-chip memory may include any off-chip storage device, such as a magnetic disk (non-volatile), network storage device, and the like.
In one possible implementation, the off-chip memory includes a DDR (Double Data Rate) memory.
In one possible implementation, the output information stored in the off-chip memory may be used to analyze the execution of the on-chip code. When the output information in the off-chip memory is the normal output information of each output function in the on-chip code, the on-chip code can be considered to be normally executed, otherwise, the on-chip code can be considered to be abnormally executed.
In one possible implementation, the on-chip processor may determine the execution of each output function based on the output information in the off-chip memory. The on-chip processor can obtain the execution condition of the on-chip code according to the execution condition of each output function, and the purpose of simultaneously printing a plurality of breakpoints in the on-chip code for debugging is achieved.
In this embodiment, the output function is set at a breakpoint of the on-chip code. When the on-chip processor starts to execute the on-chip code and executes the on-chip code to the output function, the on-chip processor stores the output information to the off-chip memory by acquiring the output information of the output function. According to the output information of the output function stored in the off-chip memory, the on-chip processor can acquire the execution condition of each breakpoint of the on-chip code in real time, the purpose of simultaneously printing a plurality of breakpoints in the on-chip code for debugging can be achieved, and the debugging efficiency of the on-chip code is improved.
Fig. 2 is a flowchart illustrating an on-chip code breakpoint debugging method according to an embodiment of the present disclosure, and as shown in fig. 2, the on-chip code breakpoint debugging method further includes:
and step S40, the on-chip processor determines the breakpoint debugging result of the on-chip code according to the output information in the off-chip memory.
In one possible implementation, the on-chip processor may determine the execution of each output function based on the output information in the off-chip memory. The on-chip processor can obtain the breakpoint debugging result of the on-chip code according to the output information of each output function and the mapping relation between the preset output information and the breakpoint debugging result. For example, the on-chip code includes three output functions, and when the on-chip code is normally executed, the output information of the three output functions is a preset number "0". The preset mapping relationship between the output information and the breakpoint debugging result may include: the output information '0, 0' in the off-chip memory corresponds to the breakpoint debugging result of the on-chip code to be 'normal'; the output information in the off-chip memory is '0, 1', the breakpoint debugging result of the corresponding on-chip code is 'execution exception at the third breakpoint', and the like. The mapping relation between the output information and the breakpoint debugging result can be determined according to the actual content of the on-chip code and the output function.
In this embodiment, the on-chip processor may determine the breakpoint modulation result of the on-chip code according to the output information in the off-chip memory. The debugging efficiency of the on-chip code can be improved by the breakpoint debugging result directly determined by the on-chip processor.
Fig. 3 is a flowchart illustrating an on-chip code breakpoint debugging method according to an embodiment of the present disclosure, and as shown in fig. 3, the on-chip code breakpoint debugging method further includes:
at step S50, the on-chip processor outputs the output information in the off-chip memory.
In one possible implementation, the on-chip processor may utilize a driver (driver) to output the output information in the off-chip memory. The on-chip processor can display the debugging result of the on-chip code by outputting the output information in the off-chip memory, so that a debugger can conveniently monitor the debugging process.
In one possible implementation, the output information in the off-chip memory may be output by way of display on a screen. The output information in the off-chip memory may be output by other means such as printing. The present disclosure does not limit the output mode of the output information in the off-chip memory.
In a possible implementation mode, the output information in the off-chip memory can be output in real time, and when a debugger judges that the on-chip code is abnormal according to the output information, the execution of the on-chip code can be stopped for debugging, so that the debugging efficiency of the on-chip code is improved.
In this embodiment, the output information of the off-chip memory can be output. The debugger can monitor the execution condition of the on-chip code in real time according to the output information, and therefore debugging efficiency of the on-chip code is improved.
Fig. 4 is a flowchart illustrating an on-chip code breakpoint debugging method according to an embodiment of the present disclosure, where, as shown in fig. 4, step S50 in the on-chip code breakpoint debugging method includes:
in step S51, when the output information in the off-chip memory is updated, the on-chip processor outputs the updated output information.
In one possible implementation, a plurality of output functions may be included in the on-chip code. The output information in the off-chip memory may be output information of a plurality of output functions. The updated output information may be output when there is an update of the output information in the off-chip memory, i.e., when there is output information of a new output function.
In this embodiment, output is performed when there is an update in the output information, and the output efficiency of the output information can be improved.
Fig. 5 is a flowchart illustrating step S51 in a method for debugging a breakpoint of code on chip according to an embodiment of the present disclosure, where, as shown in fig. 5, step S51 in the method for debugging a breakpoint of code on chip includes:
in step S511, the on-chip processor queries the output information in the off-chip memory using the first thread.
In one possible implementation, the on-chip processor may initiate the first thread to query the off-chip memory for updates to the output information. A driver may be utilized to launch a first thread to query the output information in the off-chip memory.
In one possible implementation, the on-chip processor may periodically query the output information in the off-chip memory with the first thread according to a first query cycle.
Step S512, when the output information is inquired to be updated, the first thread updates the state identifier of the off-chip memory.
In one possible implementation, a status flag may be set for the off-chip memory. The status indicator may comprise a number or a character. The status flag of the off-chip memory may include a read flag or an unread flag. For example, a read may be represented by a number "0" and an unread may be represented by a number "1".
In one possible implementation, when the first thread queries that the output information in the off-chip memory is updated, the first thread may update the status identifier of the off-chip memory. The first thread may update the status flag of the off-chip memory from a "read flag" to an "unread flag".
In step S513, the on-chip processor queries the state identifier of the off-chip memory by using a second thread.
In one possible implementation, the on-chip processor may initiate a second thread using the HOST program to query the off-chip memory for the status identification. The on-chip processor may query the state identification of the off-chip memory using the second thread according to a second query cycle. The cycle duration of the first query cycle and the second query cycle may be determined according to requirements.
Step S514, when the status flag is updated, the second thread outputs the updated output information in the off-chip memory.
In one possible implementation, when the second thread queries the status identifier of the off-chip memory for an update, for example, when the status identifier of the off-chip memory queried by the second thread is updated from a "read identifier" to an "unread identifier", the second thread may output the updated output information in the off-chip memory.
In one possible implementation, the second thread may update the status flag of the off-chip memory from "unread flag" to "read flag" after outputting the updated output information in the off-chip memory.
In one possible implementation, the driver and HOST programs may be used to cooperate with each other to output the output information in the off-chip memory timely and efficiently when the output information in the off-chip memory is updated.
Fig. 6 is a flowchart illustrating an on-chip code breakpoint debugging method according to an embodiment of the present disclosure, where, as shown in fig. 6, step S50 in the on-chip code breakpoint debugging method includes:
step S52, the on-chip processor queries a hardware state of the off-chip memory by using a third thread, where the hardware state includes a hardware interrupt state or a hardware non-interrupt state, and the hardware interrupt state of the off-chip memory is a hardware interrupt state that the off-chip memory triggers an interrupt function to enter according to the received output information.
In one possible implementation, when the off-chip memory is provided with a hardware interrupt function, an interrupt function may be set in the off-chip memory. When the off-chip memory receives the output information, the interrupt function may be triggered to enter a hardware interrupt state.
In one possible implementation, the on-chip processor may initiate a third thread with the driver to query the hardware state of the off-chip memory. When the state of the off-chip memory is in the interrupt state, the state indicates that the off-chip memory has new output information. When the state of the off-chip memory is in the non-interrupt state, it indicates that no new output information exists in the off-chip memory.
In step S53, when the state of the off-chip memory is found to be the hardware interrupt state, the third thread outputs the output information in the off-chip memory.
In one possible implementation, when the third thread queries that the state of the off-chip memory is a hardware interrupt state, the third thread may output the updated output information in the off-chip memory.
In this embodiment, the output information in the off-chip memory may be output using a hardware interrupt state of the off-chip memory. The hardware interrupt state of the off-chip memory can reflect that the off-chip memory receives the output information in time, so that the output information in the off-chip memory can be output in time.
Fig. 7 illustrates a block diagram of an on-chip processor according to an embodiment of the present disclosure, as illustrated in fig. 7, the on-chip processor including:
the starting module 10 is used for starting and executing the on-chip code, and an output function is arranged at a breakpoint of the on-chip code;
an output information obtaining module 20, configured to obtain output information of the output function, where the output information is output information of the output function when the on-chip code is executed to the output function;
and a storage module 30, configured to store the output information in an off-chip memory.
In one possible implementation, the on-chip processor further includes:
and the breakpoint debugging result determining module is used for determining the breakpoint debugging result of the on-chip code according to the output information in the off-chip memory.
In one possible implementation, the output function includes: a print number function or a print string function.
In one possible implementation, the outputting information includes: preset digital information or character string information, or output information of functions other than the output function in the on-chip code.
In a possible implementation manner, the output information obtaining module includes:
and the on-chip processor acquires the output information of the output function in the RAM of the on-chip system.
In one possible implementation, the on-chip processor further includes:
and the output module is used for outputting the output information in the off-chip memory.
In one possible implementation, the output module includes:
and the first output submodule is used for outputting the output information in the off-chip memory by using a driving program.
In one possible implementation, the output module includes:
and the second output submodule is used for outputting updated output information when the output information in the off-chip memory is updated.
In a possible implementation manner, the second output submodule is configured to:
querying output information in the off-chip memory using a first thread;
when the output information is inquired to be updated, the first thread updates the state identifier of the off-chip memory;
querying a state identifier of the off-chip memory with a second thread;
and when the state identifier is inquired to be updated, the second thread outputs the updated output information in the off-chip memory.
In one possible implementation, querying output information in the off-chip memory using a first thread includes:
starting the first thread by using a driving program to inquire the output information in the off-chip memory;
querying, with a second thread, a status identification of the off-chip memory, comprising:
initiating the second thread with a HOST program to query the state identification of the off-chip memory.
In one possible implementation, the state identification of the off-chip memory includes: read identification or unread identification.
In one possible implementation, the output module includes:
a third output sub-module, configured to query, by using a third thread, a hardware state of the off-chip memory, where the hardware state includes a hardware interrupt state or a hardware non-interrupt state, and the hardware interrupt state of the off-chip memory is a hardware interrupt state in which the off-chip memory triggers an interrupt function to enter according to received output information; and when the state of the off-chip memory is inquired to be a hardware interrupt state, the third thread outputs the output information in the off-chip memory.
Fig. 8 shows a block diagram of a chip breakpoint debugging system according to an embodiment of the present disclosure, and as shown in fig. 8, the chip breakpoint debugging system includes: the breakpoint debug chip 100 and the off-chip memory 200,
the breakpoint debugging chip 100 includes any one of the processors described above, and is configured to perform breakpoint debugging on a chip;
and the off-chip memory 200 is used for storing the output information of the breakpoint debugging chip.
It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art should also appreciate that the embodiments described in the specification are exemplary embodiments and that acts and modules referred to are not necessarily required by the disclosure.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may be implemented in the form of a software program module.
The integrated units, if implemented in the form of software program modules and sold or used as stand-alone products, may be stored in a computer readable memory. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a memory and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present disclosure. And the aforementioned memory comprises: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable memory, which may include: flash Memory disks, Read-Only memories (ROMs), Random Access Memories (RAMs), magnetic or optical disks, and the like.
The embodiments of the present disclosure are described in detail above, and the principles and embodiments of the present disclosure are explained herein by applying specific embodiments, and the descriptions of the embodiments are only used to help understanding the method and the core ideas of the present disclosure; meanwhile, for a person skilled in the art, based on the idea of the present disclosure, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present disclosure should not be construed as a limitation to the present disclosure.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (25)
1. A method for debugging breakpoints of on-chip codes is characterized by comprising the following steps:
the on-chip processor starts and executes the on-chip code, and an output function is arranged at the breakpoint of the on-chip code;
the on-chip processor acquires output information of the output function, wherein the output information is the output information of the output function when the on-chip code is executed to the output function;
the on-chip processor stores the output information to an off-chip memory.
2. The method of claim 1, further comprising:
and the on-chip processor determines a breakpoint debugging result of the on-chip code according to the output information in the off-chip memory.
3. The method of claim 1, wherein the output function comprises: a print number function or a print string function.
4. The method of claim 1, wherein outputting the information comprises: preset digital information or character string information, or output information of functions other than the output function in the on-chip code.
5. The method of claim 1, wherein the on-chip processor obtaining the output information of the output function comprises:
and the on-chip processor acquires the output information of the output function in the RAM of the on-chip system.
6. The method of claim 1, further comprising:
the on-chip processor outputs output information in the off-chip memory.
7. The method of claim 6, further comprising:
and the on-chip processor outputs the output information in the off-chip memory by using a driving program.
8. The method of claim 6, wherein the on-chip processor outputs the output information in the off-chip memory, comprising:
when the output information in the off-chip memory is updated, the on-chip processor outputs the updated output information.
9. The method of claim 8, wherein outputting, by the on-chip processor, the updated output information when there is an update in the output information in the off-chip memory comprises:
the on-chip processor queries output information in the off-chip memory by using a first thread;
when the output information is inquired to be updated, the first thread updates the state identifier of the off-chip memory;
the on-chip processor queries the state identifier of the off-chip memory by using a second thread;
and when the state identifier is inquired to be updated, the second thread outputs the updated output information in the off-chip memory.
10. The method of claim 9, wherein the on-chip processor queries the off-chip memory for output information using a first thread, comprising:
the on-chip processor starts the first thread to inquire the output information in the off-chip memory by using a driving program;
the on-chip processor querying the off-chip memory for the status identifier using a second thread, comprising:
the on-chip processor initiates the second thread to query the off-chip memory for the status identification using a HOST program.
11. The method of claim 9 or 10, wherein the status identification of the off-chip memory comprises: read identification or unread identification.
12. The method of claim 6, wherein the on-chip processor outputs the output information in the off-chip memory, comprising:
the on-chip processor queries a hardware state of the off-chip memory by using a third thread, wherein the hardware state comprises a hardware interrupt state or a hardware non-interrupt state, and the hardware interrupt state of the off-chip memory is a hardware interrupt state which is entered by triggering an interrupt function by the off-chip memory according to the received output information;
and when the state of the off-chip memory is inquired to be a hardware interrupt state, the third thread outputs the output information in the off-chip memory.
13. An on-chip processor, comprising:
the starting module is used for starting and executing the on-chip code, and an output function is arranged at the breakpoint of the on-chip code;
an output information obtaining module, configured to obtain output information of the output function, where the output information is output information of the output function when the on-chip code is executed to the output function;
and the storage module is used for storing the output information to an off-chip memory.
14. The chip of claim 13, wherein the on-chip processor comprises:
and the breakpoint debugging result determining module is used for determining the breakpoint debugging result of the on-chip code according to the output information in the off-chip memory.
15. The chip of claim 13, wherein the output function comprises: a print number function or a print string function.
16. The chip of claim 13, wherein the outputting information comprises: preset digital information or character string information, or output information of functions other than the output function in the on-chip code.
17. The chip of claim 13, wherein the output information obtaining module comprises:
and the on-chip processor acquires the output information of the output function in the RAM of the on-chip system.
18. The chip of claim 13, wherein the on-chip processor further comprises:
and the output module is used for outputting the output information in the off-chip memory.
19. The chip of claim 18, wherein the output module comprises:
and the first output submodule is used for outputting the output information in the off-chip memory by using a driving program.
20. The chip of claim 18, wherein the output module comprises:
and the second output submodule is used for outputting updated output information when the output information in the off-chip memory is updated.
21. The chip of claim 20, wherein the second output submodule is configured to:
querying output information in the off-chip memory using a first thread;
when the output information is inquired to be updated, the first thread updates the state identifier of the off-chip memory;
querying a state identifier of the off-chip memory with a second thread;
and when the state identifier is inquired to be updated, the second thread outputs the updated output information in the off-chip memory.
22. The chip of claim 21, wherein querying the output information in the off-chip memory using a first thread comprises:
starting the first thread by using a driving program to inquire the output information in the off-chip memory;
querying, with a second thread, a status identification of the off-chip memory, comprising:
initiating the second thread with a HOST program to query the state identification of the off-chip memory.
23. The chip according to claim 21 or 22, wherein the status identifier of the off-chip memory comprises: read identification or unread identification.
24. The chip of claim 18, wherein the output module comprises:
a third output sub-module, configured to query, by using a third thread, a hardware state of the off-chip memory, where the hardware state includes a hardware interrupt state or a hardware non-interrupt state, and the hardware interrupt state of the off-chip memory is a hardware interrupt state in which the off-chip memory triggers an interrupt function to enter according to received output information; and when the state of the off-chip memory is inquired to be a hardware interrupt state, the third thread outputs the output information in the off-chip memory.
25. A system for chip point debug, the system comprising: a breakpoint debug chip and an off-chip memory,
the breakpoint debugging chip comprises the on-chip processor as claimed in any one of claims 13 to 24, and is used for performing on-chip breakpoint debugging;
and the off-chip memory is used for storing the output information of the breakpoint debugging chip.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811045822.6A CN110888793A (en) | 2018-09-07 | 2018-09-07 | On-chip code breakpoint debugging method, on-chip processor and chip breakpoint debugging system |
| KR1020207036740A KR102470893B1 (en) | 2018-06-27 | 2019-06-25 | Debug method by breakpoint of on-chip code, chip debug system by on-chip processor and breakpoint |
| EP19824842.9A EP3798850A4 (en) | 2018-06-27 | 2019-06-25 | On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system |
| EP20217296.1A EP3825841A1 (en) | 2018-06-27 | 2019-06-25 | Method and device for parallel computation of a network model |
| PCT/CN2019/092805 WO2020001438A1 (en) | 2018-06-27 | 2019-06-25 | On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system |
| JP2020560786A JP7053891B2 (en) | 2018-06-27 | 2019-06-25 | On-chip code breakpoint debugging method, on-chip processor and breakpoint-based chip debugging system |
| US17/138,161 US11789847B2 (en) | 2018-06-27 | 2020-12-30 | On-chip code breakpoint debugging method, on-chip processor, and chip breakpoint debugging system |
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| CN201811045822.6A CN110888793A (en) | 2018-09-07 | 2018-09-07 | On-chip code breakpoint debugging method, on-chip processor and chip breakpoint debugging system |
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