CN100508396C - Phase-lock loop framework capable of avoiding frequency drift and jitter - Google Patents

Abstract

The invention is a phase-locked loop structure able to eliminate frequency drift and shake, composed of a first frequency eliminator, a second frequency eliminator, a phase comparer, a low-pass filter and a voltage controlled oscillator, assorted with a phase swallower in it, able to accurately obtain the needed frequency by an input reference frequency, where the voltage controlled oscillator generates an oscillation signal and at least a phase shifted oscillation signal at the same frequency as that of the oscillation signal, the phase shifted oscillation signal differs by one phase from the oscillation signal, the phase swallower selects some phase to output to generate a phase swallowed frequency eliminated signal, which is in at least one time pulse of the oscillation signal and increased by at least one phase, and then has the frequency eliminated by a third frequency eliminator, thus able to generate an output signal at the needed frequency.

Description

Produce method and the device and the phase-locked loop ring of output signal

Technical field

The present invention is the technical field of relevant phase-locked loop, refers to a kind of phase-locked loop ring stand structure of exempting frequency drift and shake especially.

Background technology

With the quick progress of work electronics technology, diversified application can be provided by various electronic product, for example, and the function that provides the PC line to surf the Net with Local Area Network Cards, or provide application such as multimedia function with image video signal card.And in the communications protocol of existing international network (Ethernet), be with the frequency of 125MHz as its conveyer (Transmitter) and receiver (Receiver) work, but in other many application, especially television image aspect, then be to use 14.318MHz as its operating frequency, therefore, if on a slice circuit board, to use this two kinds of application simultaneously, then will use two coccolith English oscillators to produce the frequency of 14.318MHz and 125MHz respectively inevitably.

Because electronic product is emphasized the characteristic that it is compact, based on the demand that reduces manufacturing cost, on an electronic product, use two coccolith English oscillators just to be difficult to realistic demand simultaneously again.So how in two coccolith English oscillators, save wherein one, just become the target on the circuit design.And because the quartz (controlled) oscillator of 14.318MHz is more cheap than the quartz (controlled) oscillator of 125MHz, so a kind of solution intuitively is to use a 14.318MHz quartz (controlled) oscillator on circuit board, with phase-locked loop ring (Phase-locked Loop is called for short PLL) frequency of 14.318MHz is amplified and the frequency of generation 125MHz in addition.

Yet, there is no simple multiplying power relation between two kinds of frequencies of aforementioned 14.318MHz and 125MHz, therefore, in fact can't obtain the frequency of 125MHz by directly 14.318MHz being amplified.A kind of feasible solution is divided by very big numeral (for example for hundreds of) with 14.318MHz, afterwards, again frequency is amplified hundreds of times near 125MHz, but this kind mode can cause two problems: one is bigger for the long-time frequency jitter (Long-term Jitter) of the phase-locked loop ring of hundreds of times of amplifications, another is not 125MHz accurately for resulting frequency, so have the shortcoming of frequency drift (Frequency Drift).Therefore, aforementionedly knownly come with the PLL circuit that the technology of amplification frequency is real to give improved necessity.

Summary of the invention

The object of the present invention is to provide a kind of phase-locked loop ring stand structure, it does not have frequency drift fully, and long-time frequency jitter can be controlled under the requirement of application specification.

Another object of the present invention is to provide a kind of phase-locked loop ring stand structure, it is suitable for and produces 125MHz frequency accurately by the 14.318MHz quartz (controlled) oscillator.

According to a characteristic of the present invention, proposition one can be exempted the phase-locked loop ring stand structure of frequency drift and shake, and it mainly comprises: one first frequency divider, and it carries out frequency division to an input reference signal; One second frequency divider carries out frequency division to an oscillator signal; One phase comparator, the output frequency division signal of the output frequency division signal of this first frequency divider and this second frequency divider relatively is to detect its phase difference; One low pass filter carries out low-pass filtering treatment to this phase difference; One voltage-controlled oscillator produces the phase shifted oscillations signal of this oscillator signal and at least one and this oscillator signal same frequency according to the phase difference after this low-pass filtering treatment, this phase shifted oscillations signal and this oscillator signal differ a phase place; One phase place phagocytic organ, in its oscillator signal and phase shifted oscillations signal by these outs of phase, by selecting some phase place output, engulf fractional frequency signal and produce a phase place, this phase place is engulfed fractional frequency signal in every X clock pulse of this oscillator signal, increase at least one phase place, wherein X is a positive integer; And a tri-frequency divider is engulfed fractional frequency signal with this phase place and is carried out frequency division, to produce an output signal.

According to another characteristic of the present invention, proposition one can be exempted the phase-locked loop ring stand structure of frequency drift and shake, and it mainly comprises: one first frequency divider, and it carries out frequency division to an input reference signal; One second frequency divider is engulfed fractional frequency signal to a phase place and is carried out frequency division; One phase comparator, the output frequency division signal of the output frequency division signal of this first frequency divider and this second frequency divider relatively is to detect its phase difference; One low pass filter carries out low-pass filtering treatment to this phase difference; One voltage-controlled oscillator produces the phase shifted oscillations signal of this oscillator signal and at least one and this oscillator signal same frequency according to the phase difference after this low-pass filtering treatment, this phase shifted oscillations signal and this oscillator signal differ a phase place; One phase place phagocytic organ, among its oscillator signal and phase shifted oscillations signal by these outs of phase, by selecting some phase place output, engulf fractional frequency signal and produce this phase place, this phase place is engulfed fractional frequency signal in every X clock pulse of this oscillator signal, increase at least one phase place, wherein, X is a positive integer; And a tri-frequency divider carries out frequency division with this oscillator signal, to produce an output signal.

Description of drawings

For further understanding structure of the present invention, feature and purpose thereof, with the detailed description of accompanying drawing and preferred embodiment as the back:

Fig. 1 is the calcspar of a preferred embodiment of the phase-locked loop ring stand structure of exempting frequency drift and shake of the present invention.

Fig. 2 is the sequential chart of Fig. 1 embodiment.

Fig. 3 is another sequential chart of Fig. 1 embodiment.

Fig. 4 is the calcspar of another preferred embodiment of the phase-locked loop ring stand structure of exempting frequency drift and shake of the present invention.

Embodiment

A relevant preferred embodiment of exempting the phase-locked loop ring stand structure of frequency drift and shake of the present invention, please be earlier with reference to shown in Figure 1, it comprises one first frequency divider 11, a phase comparator 12, a low pass filter 13, a voltage-controlled oscillator 14, one second frequency divider 15, a phase place phagocytic organ 16 and a tri-frequency divider 17.Wherein, by first frequency divider 11, phase comparator 12, low pass filter 13, voltage-controlled oscillator 14, and the circuit blocks that constituted of second frequency divider 15 be phase-locked loop ring.

In the ring of aforementioned phase-locked loop, this first frequency divider 11 carries out frequency division with divisor M (M is a positive integer) to an input reference signal CRX; This second frequency divider 15 carries out frequency division with divisor N (N is a positive integer) to an oscillator signal OSC; The output frequency division signal that this phase comparator 12 is relatively these first frequency dividers 11 and the output frequency division signal of this second frequency divider 15 are to detect its phase difference; 13 of this low pass filters carry out low-pass filtering treatment to remove high frequency noise to this phase difference; This voltage-controlled oscillator 14 after according to this low-pass filtering treatment phase difference and produce this oscillator signal OSC and phase shifted oscillations signal at least one and this oscillator signal OSC same frequency, this phase shifted oscillations signal and this oscillator signal differ a phase place, wherein, this voltage-controlled oscillator can be a ring oscillator, and as shown in the figure, form delay line by cooperating to be connected in series by P-1 delayer 141, voltage-controlled oscillator 14 just can produce this oscillator signal OSC with to P oscillator signal altogether such as P-1 phase shifted oscillations signal OSC_1～OSC_P-1, and only poor (the 1/fosc)/P of each adjacent phase chronomere, wherein, fosc is the frequency of oscillator signal OSC.

According to aforementioned phase-locked loop ring,, can obtain the frequency f of oscillator signal OSC frequency f osc and input reference signal CRX by the divisor M and the N of this first and second frequency divider 11 of control and 15 _CRXThe pass be fosc=(f _CRX/ M) * N.And this phase place phagocytic organ 16 carries out the processing that phase place is engulfed (phase swallow) with the oscillator signal of these P out of phase, promptly, under the control of its sequential and multiplex's control logic 161, in the oscillator signal of multiplex's selector 162 by these P out of phase, by selecting some phase place output, engulf fractional frequency signal FS and produce a phase place, make this phase place engulf fractional frequency signal (X is a positive integer) in every X the clock pulse of this oscillator signal OSC, increase Y phase place (Y is a nonzero integer), be so phase place is engulfed the frequency of fractional frequency signal FS

$f_{\mathrm{FS}}=f_{\mathrm{OSC}}\×\frac{X\×P}{(X\×P+Y)}=f_{\mathrm{OSC}}\×\frac{1}{(X\×P+Y)}.$

Owing to aforementioned phase place phagocytic organ 16 is to produce this phase place with Y phase place of increase in every X clock pulse to engulf fractional frequency signal FS, therefore, when X=1, the phase place of its output is engulfed the phenomenon that fractional frequency signal FS does not have dither cycle, but when X ≠ 1, if Y the phase difference that increases all concentrated in the clock pulse, then this clock pulse can be than the big Y of other a clock pulse phase place size, this moment, phase place was engulfed the dither cycle that fractional frequency signal FS has maximum, if and Y the phase place that increases is distributed in X the clock pulse dispersedly, it is the same with oscillator signal OSC that the phase place that then has is engulfed the clock cycle of fractional frequency signal FS, what have then has more a phase place, and in every X clock pulse, Y many phase places of clock pulse meeting are arranged, so the shake maximum in cycle is the size of a phase place.For exempting this dither cycle, the phase place that phase place phagocytic organ 16 is exported is engulfed fractional frequency signal FS must be again through the frequency division of tri-frequency divider 17, and wherein, the divisor S of tri-frequency divider 17 is same as X or is the integral multiple of X, so, the output signal TFO of generation does not just have dither cycle.

With the aforementioned phase-locked loop ring stand structure of exempting frequency drift and shake of the present invention, can suitably select parameter value and accurately produce a desired frequency signal, for example, when need produce the 125MHz signal by the 14.31818MHz signal, that is the input reference signal frequency f _CRXBe 14.31818MHz, and the output signal frequency f that will produce _TFOBe 125MHz.Consider in ntsc television signal specification, the scanning linear frequency is FH=(4.5/286) MHz=15734.27Hz, its (field) frequency is FV=FH/ (525/2)=59.94Hz, it is that chrominance signal (sub-carrier) frequency is FSC=((13*7*5)/2) * FH=(455/2) * FH=3.579545MHz, and in general TV signal is used, commonly used is the frequency of the quadruple rate 4*FSC of chrominance signal as video digital signal, 14.31818MHz just, therefore can extrapolate 14.31818MHz by top digital equation and 125MHz has following numerical value proportionate relationship:

125MHz＝14.31818MHz*550/63，

Produce 10 phase places as selected this voltage-controlled oscillator 14, that is P=10, then can derive output signal frequency f _TFOFor:

f _TFO＝125＝14.31818/M*N*10X/(10X+Y)/S

＝1431818*550/63

＝14.31818*55/3*10/21

＝14.31818*55/3*10/7/3

＝14.31818*55/3*20/21/2

Wherein, by f _TFO=14.31818/M*N*10X/ (10X+Y)/S=14.31818*55/3*10/7/3, can obtain one group of parameter is M=3, N=55, X=1, Y=-3, S=3, because M=3 and all non-sizable numerical value of N=55, so unlikely frequency drift that causes oscillator signal OSC, the sequential chart that oscillator signal OSC engulfs processing through phase place then as shown in Figure 2, wherein, because X=1 and Y=-3, represent each clock pulse all to reduce by 3 phase places, so not having shake produces, so the phase place in Fig. 2 engulf fractional frequency signal FS not shake produce, and phase place to engulf the cycle of fractional frequency signal FS be 0.7 times of former oscillator signal OSC clock pulse, that is f _FS=fosc/0.7=262.5MHz/0.7=375MHz, and phase place engulf fractional frequency signal FS through the 3rd frequency divider 17 divided by after 3, can get f _FFO=f _FS/ 3=375MHz/3=125MHz.

In addition by f _TFO=14.31818/M*N*10X/ (10X+Y)/S=14.31818*55/3*20/21/2, can obtain another group parameter is M=3, N=55, X=2, Y=1, S=2, similarly, the all non-sizable numerical value of M=3 and N=55, so unlikely frequency drift that causes oscillator signal OSC, the sequential chart that oscillator signal OSC engulfs processing through phase place then as shown in Figure 3, wherein X=2 and Y=1, represent per two clock pulse to add a phase place, this cycle that will cause phase place to engulf fractional frequency signal FS is respectively 1.1T0 and 1T0, be (1.1+1.0) T0/2 average period so phase place is engulfed fractional frequency signal FS, have shake and produce, and its average frequency be:

f _FS＝fosc/2.1*2＝262.5MHz/2.1*2＝250MHZ。

Phase place engulf fractional frequency signal FS signal through tri-frequency divider divided by after 2, can get f _TFO=f _FS/ 2=250MHz/2=125MHz, and because X=S=2, so output signal TFO does not shake generation.

Fig. 4 shows another preferred embodiment of exempting the phase-locked loop ring stand structure of frequency drift and shake of the present invention, it is in last embodiment different and engulfs in its phase place that to handle be to handle in the PLL loop, promptly, by first frequency divider 21, phase comparator 22, low pass filter 23, voltage-controlled oscillator 24, and in the phase-locked loop ring that constituted of second frequency divider 25, oscillator signal (the OSC of the P that produces out of phase of voltage-controlled oscillator 24, OSC_1-OSC_P-1) imports a phase place phagocytic organ 26 to carry out adding that in every X clock pulse the phase place of Y phase place engulfs processing with the oscillator signal with these P out of phase, the phase place of these phase place phagocytic organ 26 outputs is engulfed fractional frequency signal FS and is carried out frequency division via second frequency divider 25 of phase-locked loop ring again, and the frequency of oscillation OSC of phase-locked loop ring output also receives tri-frequency divider 27 to produce needed frequency signal TFO simultaneously.

With above-mentioned framework, the signal of input signal CRX after through first frequency divider, the 21 frequency divisions frequency of Fin frequently is $f_{\mathrm{Fin}}=f_{\mathrm{CRX}}/M=f_{\mathrm{OSC}}\×\frac{X\×P}{X\×P+Y}\×\frac{1}{N},$ So can get

$\mathrm{fosc}=f_{\mathrm{CRX}}\×\frac{X\×P+Y}{X\×P}\×\frac{N}{M},$

And output signal frequency is $f_{\mathrm{TCO}}=f_{\mathrm{CRX}}\×\frac{X\×P+Y}{X\×P}\×\frac{N}{M}\×\frac{1}{S},$ Similarly, if N equals X or the integral multiple of X, then the output of phase place phagocytic organ 26 is after second frequency divider 25 is divided by N, and its result does not just have long-time frequency jitter.

When producing the 125MHz signal by the 14.31818MHz signal with aforesaid framework, f as can be known _TFO=125=14.31818*550/63, because 63 are multiples of 7 and 3, thus 14 phase places of selected voltage-controlled oscillator 24 generations, that is P=14, then can derive output signal frequency f _TFOFor:

f _TFO＝125＝14.31818/M*N*(X+Y/14)/X/S

＝14.31818*N/M*(X+Y/14)*(1/X*S)

＝14.31818*550/63

＝14.31818*55/3*10/21

＝14.31818*55/3*10/7/3

＝14.31818*(78/3)[(39*14+4)/(39*14)](1/3)

＝14.31818*(78/3)[(78*14+8)/(78*14)](1/3)

＝14.31818*(79/3)[(79*14-6)/(79*14)](1/3)

Can obtain three groups of parameters as table 1 by last derivation, the N of each group is all the multiple of X, does not cause shake so can not engulf because of phase place.Thereby long-time frequency jitter eliminated, and N and all non-very big numerical value of M, therefore can obtain not shaking and frequency signal accurately.

Table 1

M	N	OSC	Fin	X	Y	S
							3	78	375MHz	4.773MHz	39	4	3
3	78	375MHz	4.773MHz	78	8	3
							3	79	375MHz	4.773MHz	79	-6	3

By above explanation as can be known, the present invention is by using phase place to engulf processing to reduce the multiplication factor of phase-locked loop ring medium frequency in the PLL circuit, so can eliminate the phenomenon of frequency shift (FS), and by the divisor of setting frequency divider, can exempt long-time frequency jitter fully, by the frequency relation of 125MHz=14.31818MHz*550/63,, can accurately obtain the signal of 125MHz in addition by the signal of 14.31818MHz by suitable setup parameter.

It should be noted that above-mentioned many embodiment give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.

Claims (9)

1, a kind of device of generation one output signal mainly comprises:

One signal generation device is in order to produce a plurality of leggy oscillator signals;

One phase place phagocytic organ, it receives these a plurality of leggy oscillator signals, and produces a phase place and engulf signal, and this phase place is engulfed signal in every X clock pulse of this leggy oscillator signal, increases or is reduced by at least a phase place, and wherein X is a positive integer; And

One output frequency frequency division device is engulfed the frequency division that signal carries out divisor S with this phase place, and to produce an output signal, the divisor S of this output frequency frequency division device is same as X or is the integral multiple of X.

2, device as claimed in claim 1 is characterized in that, wherein, this output signal frequency is $f_{\mathrm{OSC}}\×\frac{X\×P}{(X\×P+Y)}\×\frac{1}{S},$ In the middle of, fosc is the frequency of this leggy oscillator signal, the number of phases of Y in every X clock pulse of this leggy oscillator signal, being increased, and P is the number of phases of this leggy oscillator signal.

3, device as claimed in claim 1 is characterized in that, wherein, this signal generation device is a phase-locked loop ring, and the phase-locked loop ring comprises:

One phase comparator, receiving an input signal, and the phase difference of this input signal and a feedback signal relatively, according to this phase difference output one control voltage;

One voltage-controlled oscillator is according to these these a plurality of leggy oscillator signals of control voltage output;

One back coupling frequency divider, it receives a leggy oscillator signal in these a plurality of leggy oscillator signals, and carries out the frequency division of divisor N, to produce this feedback signal.

4, device as claimed in claim 3 is characterized in that, wherein also comprises an incoming frequency frequency divider, and it receives this input signal, and this input signal is carried out the frequency division of divisor M, to export this phase comparator to.

5, device as claimed in claim 4, it is characterized in that wherein the frequency of this input signal is 14.31818MHz, this output signal frequency is 125MHZ, wherein M=3, N=55, X=2, Y=1, P=10 and S=9, this output signal does not have jitter phenomenon.

6, phase-locked loop ring, it mainly comprises:

One phase comparator, receiving an input signal, and the phase difference of this input signal and a feedback signal relatively, according to this phase difference output one control voltage;

One voltage-controlled oscillator is exported a plurality of leggy oscillator signals according to this control voltage;

One phase place phagocytic organ receives this a plurality of leggy oscillator signals, engulfs signal and produce a phase place, and this phase place is engulfed signal in every X clock pulse of this leggy oscillator signal, increases or is reduced by at least a phase place, and wherein X is an integer; And

One back coupling frequency divider, it receives a leggy oscillator signal in these a plurality of leggy oscillator signals, and carries out the frequency division of divisor N, and to produce this feedback signal, this N is same as X or is the integral multiple of X.

7, phase-locked loop as claimed in claim 6 is encircled, and it is characterized in that wherein, the frequency of this feedback signal is $f_{\mathrm{OSC}}\×\frac{X\×P}{(X\×P+Y)}\×\frac{1}{N},$ In the middle of, fosc is the frequency of this leggy oscillator signal, the number of phases of Y in every X clock pulse of this leggy oscillator signal, being increased, and P is the number of phases of this leggy oscillator signal.

8, phase-locked loop as claimed in claim 6 ring is characterized in that wherein also comprise an incoming frequency frequency divider, it receives this input signal, and this input signal is carried out the frequency division of divisor M, to export this phase comparator to.

9, a kind of method that produces with proper phase output signal, this method comprises:

Produce a plurality of leggy oscillator signals;

Produce a phase place and engulf signal, according to these a plurality of leggy oscillator signals, produce a phase place and engulf signal, this phase place is engulfed signal in every X clock pulse of this leggy oscillator signal, increases or is reduced by at least a phase place, and wherein, X is a positive integer; And

The frequency division step receives this phase place and engulfs signal, carries out the frequency division that divisor is S, to produce this output signal; Wherein, this divisor S is same as X or is the integral multiple of X, produces to avoid shake.

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