CN100508071C - Memory having shielding effect - Google Patents
Memory having shielding effect Download PDFInfo
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- CN100508071C CN100508071C CNB031424457A CN03142445A CN100508071C CN 100508071 C CN100508071 C CN 100508071C CN B031424457 A CNB031424457 A CN B031424457A CN 03142445 A CN03142445 A CN 03142445A CN 100508071 C CN100508071 C CN 100508071C
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Abstract
It is a kind of semiconductor memory that has the screening effect. It consists of multiple character wires, grounding wire control unit and multiple storage units. The storage unit consists of master wire, grounding wire, the first equivalent switch and the second equivalent switch. The master wire is activated by a control signal. The grounding wire connects with the grounding wire control unit. The first equivalent switch connects with the master wire and grounding wire and is controlled by the control signal of the previous storage unit. The second equivalent switch connects with the master wire and the grounding line of the next storage unit and is controlled by the control signal of the next storage unit.
Description
Technical field
The present invention is relevant for a kind of storer, and particularly relevant for a kind of storer with shielding effect.
Background technology
Figure 1A is depicted as the equivalent circuit diagram of traditional ROM (read-only memory).Storer comprises a plurality of column of memory cells (memory cell column) C1-C12, is connected with adjacent sub-bit-line.Each column of memory cells C1-C12 comprises (m+1) individual storage unit (memory cell), and the activation according to word line WL0-WLm respectively, and wherein m is a positive integer.Each storage unit is promptly in order to store 0 or 1 data.Each storage unit can be a transistor, looks its data of storing and give different threshold voltage vts in manufacture process.Block word line BWL is by this memory block of gauge tap MB1-MB7 activation.Whether main bit line SB0, SB1 and SB2 are determined to be electrically connected to by switch MS0, MS1 and MS2 respectively to detect is amplified control module 130.Switch MS0, MS1 and MS and be controlled by control signal YS0, YS1 and YS2 respectively.Main bit line SB0, SB1 and SB2 are electrically connected with bit line control module 110 in addition, draw high or drag down by bit line control module 110.Ground wire GL0-GL3 is electrically connected with ground wire control module 120, draws high or drags down by ground wire control module 120.Promptly can determine the storage unit that read via word line WL0-WLm, ground wire G, main bit line SB and the control of selecting bit line BRT and BLT.
Be example for example with a storage unit among the reading cells row C5.Corresponding to word line WL, the control signal YS1 of this storage unit, select signal BRT to be enabled, and ground wire GL1 is discharged to earth level, then current path flow to ground wire GL1 by main bit line SB1.Amplify the electric current amplification of control module by detecting, can learn the value that this storage unit is stored main bit line SB1.
Be noted that this moment, main bit line SB0 was suspension joint (float), the electric charge on it also may flow to ground wire GL1, makes the electric current of main bit line SB1 diminish, and may cause situation about misreading.In addition, the electric current of main bit line SB1 also may flow to other ground wire, makes the electric current of main bit line SB1 diminish, and also can cause situation about misreading.Therefore need shielded measure to prevent.
Legacy memory can realize the effect of shielding with bit line control module 110 and ground wire control module 120.For example in the above-mentioned example that reads, main bit line SB0 is dragged down, can form shielding together, prevent the electric current of main bit line SB0 to ground wire GL1 on the ground wire GL1 left side by bit line control circuit 110; By ground wire control circuit 120 ground wire GL2, GL3 are drawn high in addition, and main bit line SB2 is drawn high, can form shielding together on the right of main bit line SB1, avoid electric current mistake stream by bit line control circuit.
Yet, realize that by bit line control module 110 and ground wire control module 120 measure of shielding will make the logic of circuit too complicated.And above-mentioned screen method still has small leakage current generating, and the correctness that influence is read, reason is as described later.
Please shine Figure 1B, it is depicted as the current diagram that reads the storer shown in Figure 1A.Each sub-bit-line is formed by burying diffusion layer, has electricresistance effect inevitably.During reading cells row C5, the electric current I of main bit line SB1 1 flow into bury diffusion layer direction for from top to bottom, be assumed to be V1 at the voltage of node N1; Ground wire GL2 is grounded the line traffic control unit and draws high with as shielding, and its electric current I 2 flows into the direction of burying diffusion layer and serves as reasons down supremely, is V2 at the voltage of node N2.Because electric current I 1 is different with flowing to of I2, when electric current I 2 flows to node N2, the need process to bury diffusion layer longer, and electric current I 1 flow to node N1 process to bury diffusion layer shorter, so the voltage V2 of node N2 can be littler than the voltage V1 of node N1.Owing between node N1 and the N2 voltage difference is arranged, therefore leakage current generating, the correctness that influence is read is arranged.
Summary of the invention
In view of this, purpose of the present invention is exactly that a kind of semiconductor memory with shielding effect of simplifying circuit is being provided.
According to purpose of the present invention, a kind of semiconductor memory with shielding effect is proposed, comprise many word lines, ground wire control module and a plurality of storage cell at least.Each storage cell comprises main bit line, ground wire, first equivalent switch and second equivalent switch.Main bit line activation by a control signal.Ground wire is electrically connected with the ground wire control module, and is arranged in parallel with main bit line.First equivalent switch of the n storage cell in these storage cells is connected with the main bit line of n storage cell and the ground wire of n storage cell, and is controlled by the control signal of (n-1) storage cell.Second equivalent switch of n storage cell is connected with the main bit line of n storage cell and the ground wire of (n+1) storage cell, and is controlled by the control signal of (n+1) storage cell.
According to purpose of the present invention, a kind of semiconductor memory with shielding effect is also proposed, comprise at least: many word lines, respectively this word line is arranged in parallel; One ground wire control module; A plurality of storage cells, respectively this storage cell comprises: a main bit line, with the staggered homeotropic alignment of these word lines, activation by a control signal; One ground wire is electrically connected with this ground wire control module, and is arranged in parallel with this main bit line; One first sub-bit-line, one second sub-bit-line, one the 3rd sub-bit-line, one the 4th sub-bit-line and one the 5th sub-bit-line are arranged in parallel with this main bit line, and this first sub-bit-line is connected with this ground wire, and the 3rd sub-bit-line is connected with this main bit line; Four column of memory cells respectively comprise a plurality of storage unit, parallel respectively being connected between this adjacent first sub-bit-line, this second sub-bit-line, the 3rd sub-bit-line, the 4th sub-bit-line and the 5th sub-bit-line; One first equivalent switch; And one second equivalent switch; And one detect to amplify control module, is connected with these main bit lines of these storage cells, in order to amplification and detect the electric current of these main bit lines; Wherein, this first equivalent switch of this n storage cell in these storage cells is connected with this main bit line of this n storage cell and this ground wire of this n storage cell, and is controlled by this control signal of this (n-1) storage cell; Wherein, this second equivalent switch of this n storage cell in these storage cells is connected with this main bit line of this n storage cell and this ground wire of this (n+1) storage cell, and is controlled by this control signal of this (n+1) storage cell; Wherein, the 5th sub-bit-line of this n storage cell is this first sub-bit-line of this (n+1) storage cell; Wherein, n is a positive integer.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A represents the equivalent circuit diagram of traditional ROM (read-only memory).
Figure 1B represents to read the current diagram of the storer shown in Figure 1A.
Fig. 2 A represents a kind of equivalent circuit diagram with semiconductor memory of shielding effect according to one embodiment of the present invention.
The current diagram of the storer shown in Fig. 2 A is read in 2B figure expression.
The drawing reference numeral explanation
110: the bit line control module
120,220: the ground wire control module
130,230: detect and amplify control module
Embodiment
Please refer to Fig. 2 A, its expression is according to a kind of equivalent circuit diagram with semiconductor memory of shielding effect of one embodiment of the present invention.Storer comprises a plurality of column of memory cells (memory cellcolumn) C1-C12, is connected with adjacent sub-bit-line.Each column of memory cells C1-C12 comprises (m+1) individual storage unit (memory cell), and the activation according to word line WL0-WLm respectively, and wherein m is a positive integer.Each storage unit is in order to store 0 or 1 data.Each storage unit can be a transistor, looks its data of storing and give different threshold voltage vts in manufacture process.Block word line BWL passes through gauge tap MB1-MB7 with this memory block of activation.Whether main bit line SB0, SB1 and SB2 are determined to be electrically connected to by switch MS0, MS1 and MS2 respectively to detect is amplified control module 130.Switch MS0, MS1 and MS2 and be controlled by control signal YS0, YS1 and YS2 respectively.Ground wire GL0-GL3 is electrically connected with ground wire control module 220, draws high or drags down by ground wire control module 220.Can determine the storage unit that read via word line WL0-WLm, ground wire GL0-GL3, main bit line SB0-SB2 and the control of selecting bit line BRT and BLT.
Main bit line and ground wire are that metal level constitutes, and sub-bit-line constitutes for burying diffusion layer (Buried Diffusion).Main bit line and ground wire connect with corresponding sub-bit-line by contact hole (contact hole).
Feature of the present invention is at equivalent switch ME1-ME6, realizes the effect that shields by control equivalent switch ME1-ME6.Equivalent switch ME1-ME6 is connected between ground wire GL0, main bit line SB0, ground wire GL1, main bit line SB1, ground wire GL2, main bit line SB2 and the ground wire GL3, and is controlled by control signal YS ', YS1, YS0, YS2, YS1 and YS3 respectively.In the present embodiment, equivalent switch is a transistor.
With a storage unit among the reading cells row C5 is example.Word line WL, selection signal BRT corresponding to this storage unit need be enabled, and ground wire GL1 is discharged to earth level, control signal YS1 activation main bit line SB1.Then current path flow to ground wire GL1 by main bit line SB1.Amplify the electric current amplification of control module by detecting, can learn the value that this storage unit is stored main bit line SB1.Simultaneously, control signal YS1 activation equivalent switch ME2 makes main bit line SB0 and ground wire GL1 equipotential also to be electronegative potential, to form shielding on the ground wire GL1 left side.Control signal YS1 is activation equivalent switch ME5 also, make main bit line SB2 and ground wire GL2 equipotential, ground wire GL2 and GL3 all were grounded line traffic control unit 220 and drew high this moment, made the current potential of main bit line also draw high via equivalent switch ME5, shielded to form on main bit line SB1 the right.
The current diagram of the storer shown in Fig. 2 A is read in 2B figure expression.Each sub-bit-line is formed by burying diffusion layer, has electricresistance effect inevitably.During reading cells row C5, the electric current I of main bit line SB1 1 flow into bury diffusion layer direction for from top to bottom, be assumed to be V1 at the voltage of node N1; Ground wire GL2 is grounded the line traffic control unit and draws high with as shielding, via the conducting of equivalent switch ME4 main bit line SB2 is also drawn high, its electric current I 2 flow into bury diffusion layer direction also for from top to bottom, be V2 at the voltage of node N2.Because electric current I 1 is identical with flowing to of I2, process to bury diffusion layer phase same, so the voltage V2 of node N2 is identical with the voltage V1 of node N1.Owing to do not have voltage difference between node N1 and the N2, therefore provide better shielding, the correctness that reads with enhancement than traditional storer.
The disclosed semiconductor memory with shielding effect of the above embodiment of the present invention has the following advantages:
One, simplifies the circuit of shielding effect, can realize shielding effect, the correctness that reads with raising with the equivalent switch that is connected between main bit line and ground wire.
Two, provide better shield effectiveness, reduce the influence of the electricresistance effect bury diffusion layer, the correctness that reads with raising.
Three, avoid the surge voltage of main bit line.Sometimes main bit line has the surge voltage that can not expect, for example is electric charge coupling etc., and makes the electric charge of main bit line too high, causes read error.By the discharge measure of equivalent switch of the present invention and ground wire, can make main bit line be discharged to appropriate voltage, the correctness that reads with enhancement.
In sum; though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can carry out various changes and modification, so the claim restricted portion that protection scope of the present invention proposed is as the criterion.
Claims (7)
1. semiconductor memory with shielding effect comprises at least:
Many word lines, respectively this word line is arranged in parallel;
One ground wire control module; And
A plurality of storage cells, respectively this storage cell comprises:
One main bit line is with the staggered homeotropic alignment of these word lines, the activation by a control signal;
One ground wire is electrically connected with this ground wire control module, and is arranged in parallel with this main bit line;
One first equivalent switch; And
One second equivalent switch;
Wherein, this first equivalent switch of this n storage cell in these storage cells is connected with this main bit line of this n storage cell and this ground wire of this n storage cell, and is controlled by this control signal of this (n-1) storage cell;
Wherein, this second equivalent switch of this n storage cell in these storage cells is connected with this main bit line of this n storage cell and this ground wire of this (n+1) storage cell, and is controlled by this control signal of this (n+1) storage cell;
Wherein, n is a positive integer.
2. the semiconductor memory with shielding effect as claimed in claim 1, wherein this storer also comprises:
One detects the amplification control module, is connected with these main bit lines of these storage cells, in order to amplify and to detect the electric current of these main bit lines.
3. the semiconductor memory with shielding effect as claimed in claim 1, wherein this storage cell also comprises:
One first sub-bit-line, one second sub-bit-line, one the 3rd sub-bit-line, one the 4th sub-bit-line and one the 5th sub-bit-line are arranged in parallel with this main bit line, and this first sub-bit-line is connected with this ground wire, and the 3rd sub-bit-line is connected with this main bit line;
Wherein, the 5th sub-bit-line of this n storage cell is this first sub-bit-line of this (n+1) storage cell.
4. the semiconductor memory with shielding effect as claimed in claim 3, wherein this storage cell also comprises:
Four column of memory cells respectively comprise a plurality of storage unit, parallel respectively being connected between this adjacent first sub-bit-line, this second sub-bit-line, the 3rd sub-bit-line, the 4th sub-bit-line and the 5th sub-bit-line.
5. the semiconductor memory with shielding effect as claimed in claim 1, wherein this first equivalent switch and this second equivalent switch are transistor.
6. semiconductor memory with shielding effect comprises at least:
Many word lines, respectively this word line is arranged in parallel;
One ground wire control module;
A plurality of storage cells, respectively this storage cell comprises:
One main bit line is with the staggered homeotropic alignment of these word lines, the activation by a control signal;
One ground wire is electrically connected with this ground wire control module, and is arranged in parallel with this main bit line;
One first sub-bit-line, one second sub-bit-line, one the 3rd sub-bit-line, one the 4th sub-bit-line and one the 5th sub-bit-line are arranged in parallel with this main bit line, and this first sub-bit-line is connected with this ground wire, and the 3rd sub-bit-line is connected with this main bit line;
Four column of memory cells respectively comprise a plurality of storage unit, parallel respectively being connected between this adjacent first sub-bit-line, this second sub-bit-line, the 3rd sub-bit-line, the 4th sub-bit-line and the 5th sub-bit-line;
One first equivalent switch; And
One second equivalent switch; And
One detects the amplification control module, is connected with these main bit lines of these storage cells, in order to amplify and to detect the electric current of these main bit lines;
Wherein, this first equivalent switch of this n storage cell in these storage cells is connected with this main bit line of this n storage cell and this ground wire of this n storage cell, and is controlled by this control signal of this (n-1) storage cell;
Wherein, this second equivalent switch of this n storage cell in these storage cells is connected with this main bit line of this n storage cell and this ground wire of this (n+1) storage cell, and is controlled by this control signal of this (n+1) storage cell;
Wherein, the 5th sub-bit-line of this n storage cell is this first sub-bit-line of this (n+1) storage cell;
Wherein, n is a positive integer.
7. the semiconductor memory with shielding effect as claimed in claim 6, wherein this first equivalent switch and this second equivalent switch are transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031424457A CN100508071C (en) | 2003-06-12 | 2003-06-12 | Memory having shielding effect |
| US10/658,324 US6862203B2 (en) | 2003-05-27 | 2003-09-10 | Memory with shielding effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031424457A CN100508071C (en) | 2003-06-12 | 2003-06-12 | Memory having shielding effect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1567480A CN1567480A (en) | 2005-01-19 |
| CN100508071C true CN100508071C (en) | 2009-07-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031424457A Expired - Lifetime CN100508071C (en) | 2003-05-27 | 2003-06-12 | Memory having shielding effect |
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| Country | Link |
|---|---|
| CN (1) | CN100508071C (en) |
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2003
- 2003-06-12 CN CNB031424457A patent/CN100508071C/en not_active Expired - Lifetime
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| Publication number | Publication date |
|---|---|
| CN1567480A (en) | 2005-01-19 |
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Granted publication date: 20090701 |