CN100507686C - LCD array and LCD panel - Google Patents
LCD array and LCD panel Download PDFInfo
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- CN100507686C CN100507686C CNB2004100318595A CN200410031859A CN100507686C CN 100507686 C CN100507686 C CN 100507686C CN B2004100318595 A CNB2004100318595 A CN B2004100318595A CN 200410031859 A CN200410031859 A CN 200410031859A CN 100507686 C CN100507686 C CN 100507686C
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- 239000003990 capacitor Substances 0.000 claims abstract description 40
- 239000004973 liquid crystal related substance Substances 0.000 claims abstract description 30
- 230000009021 linear effect Effects 0.000 claims description 77
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000010409 thin film Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 3
- 101100392772 Caenorhabditis elegans gln-2 gene Proteins 0.000 description 2
- 101100068676 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) gln-1 gene Proteins 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
Liquid crystal display array includes multiple scanning lines, data lines and pixel units. Each scanning line includes first part and second part extended from first part. Multiple pixel units are setup at intersecting places between scanning line and data line, and each pixel unit includes a memory capacitor. One end of first memory capacitor corresponding to first scanning line is coupled to first or second segment of a scanning line except the first scanning line.
Description
Technical field
The present invention is applicable to LCD relevant for a kind of LCD array.In this LCD array and an end of the memory capacitance of each pixel cell couple scanning linear first partly or second portion, and then reduce the time delay of scanning linear drive thin film transistors.
Background technology
Thin Film Transistor-LCD (thin film transistor liquid crystaldisplay, to call TFT-LCD in the following text) the array of display type, along with memory capacitance (storagecapacitor, the Cs) difference of structure, and form different array type.General common storage capacitor construction can be divided into two kinds, is respectively that memory capacitance is utilized last scanning linear (Cs on gate) and the structure that forms is utilized common electrode line (Cs on common) and the structure of formation with memory capacitance.Two kinds of main difference of structure are memory capacitance between show electrode and last scanning linear, or use together between the electrode wires between show electrode, and promptly the reference potential of memory capacitance is the current potential of last scanning linear, or the current potential of common electrode line.
Fig. 1 represents the formed LCD array of capacitance structure of known Cs on common.LCD array 1 is by crisscross scanning linear Gln, Gln-1 and Gln-2, and data line Dlm and Dlm-1 constitute.Scanning linear that each is staggered and data line form a pixel cell.Each pixel cell has oxide-semiconductor control transistors, liquid crystal capacitance and memory capacitance, and memory capacitance is coupled to show electrode and uses between the electrode wires together.For example, scanning linear Dln-1 and data line Glm-1 form a pixel cell 100, and pixel cell 100 has thin film transistor (TFT) (TFT) 10, liquid crystal capacitance Clc10 and memory capacitance Cs10.As shown in Figure 1, the grid of oxide-semiconductor control transistors 10 couple in scanning linear Dln-1, and memory capacitance Csl0 couples show electrode 11 and uses together between the electrode wires Vcoml0.The memory capacitance of pixel cell on colleague mutually is coupled between show electrode and the identical common electrode line separately.
Fig. 2 represents the formed LCD array of capacitance structure of known Cs on gate.LCD array 2 is by crisscross scanning linear G2n, G2n-1 and G2n-2, and data line D2m and D2m-1 constitute.Scanning linear that each is staggered and data line form a pixel cell.Each pixel cell has oxide-semiconductor control transistors, liquid crystal capacitance and memory capacitance, and memory capacitance is coupled between show electrode and last the scanning linear.For example, scanning linear G2n-1 and data line D2m-1 form a pixel cell 200, and pixel cell 200 has thin film transistor (TFT) (TFT) 20, liquid crystal capacitance Clc20 and memory capacitance Cs20.As shown in Figure 2, the grid of TFT20 is coupled to scanning linear G2n-1, and memory capacitance Cs20 is coupled between show electrode 21 and the scanning linear G2n-2.Be arranged in the pixel cell with delegation, oxide-semiconductor control transistors is coupled to identical scanning linear, and memory capacitance all is coupled between separately the show electrode and last scanning linear.
As mentioned above, the capacitance structure of Cs on common must increase the common electrode line, causes aperture opening ratio (ApeRture ratio) less.Because the size of aperture opening ratio influences the key factor of the brightness and the design of liquid crystal panel, so the capacitance structure of Cs on common does not more adopt, adopts the capacitance structure of Cs on gate mostly.And in the capacitance structure of Cs on gate,,, cause increase the time delay of scanning linear by the RC circuit effects that scanning linear and memory capacitance are produced because each scanning linear all couples many memory capacitance.Relatively, after control TFT conducting, TFT also reduces with the ability that the show electrode end is discharged and recharged according to the vision signal of online data.
Summary of the invention
In view of this, in order to address the above problem, fundamental purpose of the present invention is to provide a kind of LCD array, and it has many scanning linears, and each scanning linear has first part and second partly.Utilize an end of the memory capacitance of pixel cell couple scanning linear first partly or second portion, to reduce the time delay of scanning linear.
For realizing above-mentioned purpose, the present invention proposes a kind of LCD array, comprises multi-strip scanning line, many data lines and a plurality of pixel cell.Each sweep trace comprises first and the second portion that is extended by first.A plurality of pixel cells are provided with corresponding to each staggered place of sweep trace and data line, and each pixel cell comprises first holding capacitor.Wherein, an end of first holding capacitor of first sweep trace in the corresponding sweep trace couples the second portion of the one scan line except first sweep trace.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail as follows:
Fig. 1 represents the formed LCD array of capacitance structure of known Cs on common.
Fig. 2 represents the formed LCD array of capacitance structure of known Cs on gate.
Fig. 3 represents a LCD array of the embodiment of the invention.
Fig. 4 represents another LCD array of the embodiment of the invention.
Fig. 5 represents the time sequential routine figure of the LCD array of known LCD array and present embodiment.
Symbol description:
1～LCD array; Gln, Gln-1, Gln-2～scanning linear; Dlm, Dlm-1～data line; 100～pixel cell; 10～thin film transistor (TFT); 11～show electrode; Clc10～liquid crystal capacitance; Cs10～memory capacitance; Vcoml0～common electrode line;
2～LCD array; G2n, G2n-1, G2n-2～scanning linear; D2m, D2m-1～data line; 200～pixel cell; 20～thin film transistor (TFT); 21～show electrode; Clc20～liquid crystal capacitance; Cs20～memory capacitance;
3～LCD array; G3n, G3n-1, G3n-2～scanning linear; D3m, D3m-1～data line; G3 ' n, G3 ' n-1, G3 ' n-2～sub-scanning linear; 300～pixel cell; 30～oxide-semiconductor control transistors; 31～show electrode; Clc30～liquid crystal capacitance; Cs30～memory capacitance;
4～LCD array; G4n, G4n-1, G4n-2～scanning linear; D4m, D4m-1～data line; G4 ' n, G4 ' n-1, G4 ' n-2～sub-scanning linear; 400～pixel cell; 40～oxide-semiconductor control transistors; 41～show electrode; Clc40～liquid crystal capacitance; Cs40, Cs41～memory capacitance.
Embodiment
Fig. 3 represents a LCD array of the embodiment of the invention.LCD array 3 is by crisscross scanning linear G3n, G3n-1 and G3n-2, and data line D3m and D3m-1 constitute.Each staggered scanning linear and data line forms a pixel cell, and each pixel cell has thin film transistor (TFT) (TFT) and liquid crystal capacitor and holding capacitor.In addition, scanning linear G3n, G3n-1 and G3n-2 have sub-scanning linear G3 ' n, G3 ' n-1 and G3 ' n-2, and sub-scanning linear G3 ' n, G3 ' n-1 and G3 ' n-2 are extended by scanning linear G3n, G3n-1 and G3n-2 respectively.Each scanning linear and corresponding sub-scanning linear thereof are loaded with identical signal.
As shown in the figure, scanning linear G3n and data line D3m-1 form a pixel cell 300, and pixel cell 300 has TFT30, liquid crystal capacitance Clc30 and memory capacitance Cs30.The grid of TFT30 couples scanning linear G3n-1, and the source electrode of TFT30 couples data line D3m-1.The electrode of the drain electrode of TFT30, liquid crystal capacitance Clc30 and the electrode of memory capacitance Cs30 all couple show electrode 31.Another electrode of liquid crystal capacitance Clc30 is coupled to common electrode line Vcom30.Another electrode of memory capacitance Cs30 couples sub-scanning linear G3 ' n-2.
This embodiment of the present invention, each scanning linear have a sub-scanning linear.One utmost point of the memory capacitance in arbitrary pixel cell is coupled to pixel electrode, and the other end of memory capacitance is coupled to the sub-scanning linear of the arbitrary sweep trace except the corresponding scanning line.Be the grid that each scanning linear only couples the TFT of corresponding one-row pixels unit, and each sub-scanning linear only couple another utmost point of the memory capacitance of arbitrary capable pixel cell.Because the scanning linear of drive TFT does not have the memory capacitance of coupling, thus the RC circuit effects disappearance that produced of scanning linear and memory capacitance, reduce the time delay of scanning linear relatively, and TFT also improves the ability that the show electrode end discharges and recharges.
Fig. 4 represents another LCD array of the embodiment of the invention.LCD array 4 is by crisscross scanning linear G4n, G4n-1 and G4n-2, and data line D4m and D4m-1 constitute.Each staggered scanning linear and data line forms a pixel cell, and each pixel cell has thin film transistor (TFT) (TFT) and liquid crystal capacitor.Each pixel cell of present embodiment has two memory capacitance.In addition, scanning linear G4n, G4n-1 and G4n-2 have sub-scanning linear G4 ' n, G4 ' n-1 and G4 ' n-2, and sub-scanning linear G4 ' n, G4 ' n-1 and G4 ' n-2 are extended by scanning linear G4n, G4n-1 and G4n-2 respectively.Each scanning linear and corresponding sub-scanning linear thereof are loaded with identical signal.
As shown in the figure, scanning linear G4n and data line D4m-1 form a pixel cell 400, and pixel cell 400 has TFT40, liquid crystal capacitance Clc40 and memory capacitance Cs40 and Cs41.The grid of TFT40 couples scanning linear G4n-1, and the source electrode of TFT40 couples data line D4m-1.The electrode of the drain electrode of TFT40, liquid crystal capacitance Clc40 and the electrode of memory capacitance Cs40 and Cs41 all couple show electrode 41.Another electrode of liquid crystal capacitance Clc40 is coupled to common electrode line Vcom40.Another electrode of memory capacitance Cs40 couples sub-scanning linear G4 ' n-2, and another electrode of memory capacitance Cs41 couples scanning linear G4n-1.
In this LCD array 4, another electrode of memory capacitance Cs40 couples sub-scanning linear G4 ' n-2.As previously mentioned, the RC circuit effects that this coupling mode can make scanning linear and memory capacitance be produced disappears, and reduce the time delay of scanning linear, and TFT also improves the ability that the show electrode end discharges and recharges.In addition, all TFT are identical in the LCD array 4 of known LCD array 2 and present embodiment, and LCD array 2 and 4 operates under identical operating voltage, and the capacitance of memory capacitance Cs40 and Cs41 is littler than memory capacitance Cs30.Therefore, though another electrode of memory capacitance Cs41 couples scanning linear G4n-1, because the minimizing of the capacitance in the RC circuit, so also reduce relatively the time delay of scanning linear.
Fig. 5 represents time sequential routine figure in the LCD array 4 of known LCD array 2 and present embodiment.As shown in the figure, suppose that all TFT are identical in LCD array 2 and 4, and total capacitance and resistance value are also identical.It is fast than level V (5) rise time of the last signal of scanning linear G2n that scanning linear G4n goes up level V (5) rise time of signal, and relatively, TFT40 also improves the ability that show electrode 41 ends discharge and recharge.The rise time of voltage level V (8) that is show electrode 41 is faster than the rise time of the voltage level V (6) of show electrode 21.
Embodiments of the invention are example with one and two memory capacitance, and in the practical operation, the memory capacitance in each pixel cell is not as limit.In addition, the memory capacitance of each pixel cell can couple scanning linear arbitrary scanning linear and the arbitrary sub-scanning linear in addition that drives this pixel cell.
In sum; though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can carry out various changes and modification, so protection scope of the present invention is as the criterion when looking the claim restricted portion that is proposed.
Claims (14)
1. LCD array comprises:
Multi-strip scanning line, each sweep trace comprise a first and a second portion that is extended by this first;
Many data lines;
A plurality of pixel cells are provided with corresponding to each staggered place of this multi-strip scanning line and these many data lines, and each pixel cell comprises one first holding capacitor;
Wherein, to an end of this first holding capacitor of one first sweep trace in should the multi-strip scanning line, couple this second portion of one in this multi-strip scanning line except this first sweep trace.
2. LCD array as claimed in claim 1, wherein each pixel cell also comprises an oxide-semiconductor control transistors and a liquid crystal capacitor, the control utmost point of this oxide-semiconductor control transistors couples this first part of this corresponding scanning linear, first utmost point of this oxide-semiconductor control transistors is coupled to this corresponding data line, one end of this liquid crystal capacitor couples uses electrode altogether, and the other end of this first holding capacitor and the other end of this liquid crystal capacitor couple second utmost point of this oxide-semiconductor control transistors.
3. LCD array as claimed in claim 1, wherein each pixel cell also comprises one second holding capacitor, and, couple this first of one in this multi-strip scanning line except this first sweep trace to an end of this second holding capacitor that should first sweep trace.
4. LCD array as claimed in claim 3, wherein, an end of this first holding capacitor and an end of this second holding capacitor couple this first or this second portion of two different these multi-strip scanning lines respectively.
5. LCD array as claimed in claim 3, wherein, an end of this first holding capacitor couples this second portion of one second sweep trace adjacent with this first sweep trace,
6. LCD array as claimed in claim 5, wherein, an end of this second holding capacitor couples this first of one three scanning linear adjacent with this first sweep trace.
7. LCD array as claimed in claim 3, wherein each pixel cell also comprises an oxide-semiconductor control transistors and a liquid crystal capacitor, the control utmost point of this oxide-semiconductor control transistors couples this first part of this corresponding scanning linear, first utmost point of this oxide-semiconductor control transistors is coupled to this corresponding data line, one end of this liquid crystal capacitor couples uses electrode altogether, and the other end of this first holding capacitor and the other end of this liquid crystal capacitor couple second utmost point of this oxide-semiconductor control transistors.
8. display panels comprises:
One scans driver;
One data driver;
Multi-strip scanning line, each sweep trace comprise a first and a second portion that is extended by this first;
Many data lines;
A plurality of pixel cells are provided with corresponding to each staggered place of this multi-strip scanning line and these many data lines, and each pixel cell comprises one first holding capacitor;
Wherein, to an end of this first holding capacitor of one first sweep trace in should the multi-strip scanning line, couple this second portion of one in this multi-strip scanning line except this first sweep trace.
9. display panels as claimed in claim 8, wherein each pixel cell also comprises an oxide-semiconductor control transistors and a liquid crystal capacitor, the control utmost point of this oxide-semiconductor control transistors couples this first part of this corresponding scanning linear, first utmost point of this oxide-semiconductor control transistors is coupled to this corresponding data line, one end of this liquid crystal capacitor couples uses electrode altogether, and the other end of this first holding capacitor and the other end of this liquid crystal capacitor couple second utmost point of this oxide-semiconductor control transistors.
10. display panels as claimed in claim 8, wherein each pixel cell also comprises one second holding capacitor, and, couple this first of one in this multi-strip scanning line except this first sweep trace to an end of this second holding capacitor that should first sweep trace.
11. display panels as claimed in claim 10, wherein, an end of this first holding capacitor and an end of this second holding capacitor couple this first or this second portion of two different these multi-strip scanning lines respectively.
12. display panels as claimed in claim 10, wherein, an end of this first holding capacitor couples this second portion of one second sweep trace adjacent with this first sweep trace two.
13. display panels as claimed in claim 12, wherein, an end of this second holding capacitor couples this first of one three scanning linear adjacent with this first sweep trace.
14. display panels as claimed in claim 10, wherein each pixel cell also comprises an oxide-semiconductor control transistors and a liquid crystal capacitor, the control utmost point of this oxide-semiconductor control transistors couples this first part of this corresponding scanning linear, first utmost point of this oxide-semiconductor control transistors is coupled to this corresponding data line, one end of this liquid crystal capacitor couples uses electrode altogether, and the other end of this first holding capacitor and the other end of this liquid crystal capacitor couple second utmost point of this oxide-semiconductor control transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100318595A CN100507686C (en) | 2004-03-30 | 2004-03-30 | LCD array and LCD panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100318595A CN100507686C (en) | 2004-03-30 | 2004-03-30 | LCD array and LCD panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1564073A CN1564073A (en) | 2005-01-12 |
| CN100507686C true CN100507686C (en) | 2009-07-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100318595A Expired - Fee Related CN100507686C (en) | 2004-03-30 | 2004-03-30 | LCD array and LCD panel |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100381930C (en) * | 2005-08-05 | 2008-04-16 | 友达光电股份有限公司 | Liquid crystal display device |
| CN100405144C (en) * | 2006-01-19 | 2008-07-23 | 友达光电股份有限公司 | Display device and panel module |
| CN102289121B (en) * | 2009-01-08 | 2013-06-19 | 胜华科技股份有限公司 | Liquid crystal display and pixel unit thereof |
| CN104777689B (en) * | 2015-04-17 | 2017-07-18 | 京东方科技集团股份有限公司 | Array base palte and display device |
| CN107479289B (en) * | 2017-09-13 | 2020-06-05 | 深圳市华星光电技术有限公司 | Pixel structure and array substrate |
| CN110310608B (en) * | 2018-03-27 | 2021-01-05 | 京东方科技集团股份有限公司 | Control circuit, test equipment and test method of liquid crystal display panel |
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- 2004-03-30 CN CNB2004100318595A patent/CN100507686C/en not_active Expired - Fee Related
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| CN1564073A (en) | 2005-01-12 |
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Granted publication date: 20090701 |