CN100505516C - Digital baseband receiver including a high pass filter compensation module for suppressing group delay variation distortion due to deficiencies of analog high pass filter - Google Patents
Digital baseband receiver including a high pass filter compensation module for suppressing group delay variation distortion due to deficiencies of analog high pass filter Download PDFInfo
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Abstract
A digital baseband (DBB) radio frequency (RF) receiver includes a digital high pass filter compensation (HPFC) module used to suppress group delay variation distortion caused by using low cost analog high pass filters (HPFs) in the receiver. The digital HPFC module reduces a cutoff frequency, established by the HPFs for the real and imaginary signal component frequency domain responses by providing a first compensation signal having a first predetermined value (K1). The digital HPFC module adjusts the gain of the high pass response of the real and imaginary signal component frequency domains by providing a second compensation signal having a second predetermined value (K2).
Description
Technical field
The present invention is relevant for the receiver design of wireless telecommunication system.Especially, the present invention handles (DSP) technology relevant for the digital signal of using in order to the group delay variation that produces in the compensating analog wireless receiver.
Background technology
Existing wireless system architecture design awards the restriction of designer's strictness aspect the reception communication signal.In addition, this kind framework provides low communication link usually, high running cost, and the integration of the low water-mark of do not behave desirable and other system component.
As shown in Figure 1, known radio frequency (RF) receiver 100 comprises an artificial antenna receiver 105, at least one analog-digital converter (ADC) 110, one controllers 115 and a modulator-demodulator 120.Artificial antenna receiver 105 is direct receivers, it comprises that an antenna 125 is in order to receive wireless communication signal, one band pass filter 130, one low noise amplifier (LNA) 135, one second filter (as band pass filter) 140 optionally, one demodulator 145 has two outputs 150,155, one phase-lock loop (PLL) 160, one analog real signal path low pass filter (LPF) 165A, one analog imaginary signal path LPF 165B, first order real part signal path amplifier 170A, first and imaginary signal path amplifier 170B, first order analog real signal path high pass filter (HPF) 175A, first order analog imaginary signal path HPF 175B, real part signal path, second level amplifier 180A, imaginary signal path, second level amplifier 180B, analog real signal path, second level HPF 185A, and analog imaginary signal path, second level HPF 185B.Amplifier 170A, 170B, 180A, each comprises the interior high-gain stage of analog domain of RF receiver 100 180B.
The switching of modulator-demodulator 120 control LNA 135.PLL 160 produces two outputs 150,155 of area oscillation (LO) signal with control demodulator 145.Export homophase (in-phase (the I)) output of 150 demodulators 145, in order to a real part signal composition of output wireless communication signal.Export 1/4th of 155 demodulators 145 and differ (quadrature (Q)) output, in order to an imaginary signal of output wireless communication system.Simulation LPFs 165A, 165B controls the frequency range selectivity of I and Q output 150 and 155 respectively. Simulation LPFs 165A, 165B be subsequently respectively by first and second grade amplifier 170A, 170B, and 180A, 180B amplifies.
Because high gain requirements, first and second level simulation HPFs 175A, 175B, 185A, 185B is contained in the artificial antenna receiver 105 with respectively at first and second grade amplifier 170A, 170B, 180A, provide electric capacity, the direct current (DC) that first and second gain stage is coupled by AC and other is remaining by this to be removed after the 180B to prevent the DC skew.Simulation HPFs175A, 175B, 185A, each of 185B has signal input, signal output, at least one electric capacity (C) connects signal and inputs to signal output, and at least one resistance (R) connects the ground that exports to of electric capacity, so forms the R-C filter.Simulation HPFs175A, 175B, 185A, the lower part of the frequency domain response that the 185B change is relevant with real part and imaginary signal composition (for example is lower than the spectral shape (that is reducing energy) of 50kHz.
In the known RF receiver 100 of Fig. 1, ADC 110 is connected to second level simulation HPFs 185A, the output of 185B.The I of ADC 110 output numerals and Q output 190,195.Controller 115 is kept all driving components of artificial antenna receiver 105 and ADC 110.
In artificial antenna receiver 105, simulation HPFs 175A, 175B, 185A, 185B are used to guarantee the spectral shape in the preceding wireless communication signal that receives via antenna 125 of ADC 110 samplings.Usually, simulation HPFs175A, 175B, 185A, the specification of 185B is very strict so need higher order filter when implementing.Especially, it is error vector magnitude (error vector magnitude) that a kind of specification is arranged, and it is mean-square value error (the means square error) measurement of normalization (normalized). Implement simulation HPFs 175A, 175B, 185A, the higher order filter design of 185B may be complicated and expensive.Therefore, simulation HPFs 175A, 175B, 185A, the error on the 185B may cause unacceptable output.Simulation HPFs 175A, 175B, 185A, the reduction of the design complexities of 185B can be reached by use has the lower-order Design of Filter of stricter specification.But, at simulation HPFs 175A, 175B, 185A, if the generation of using this kind Design of Filter will produce group delay variation distortion among the 185B is not at simulation HPFs 175A, 175B, import compensation after the 185A, 185B, therefore reduce the performance of RF receiver 100.
Because the cost of the HPFs of processing RF analog signal is than using the DSP height, be desirable to provide a kind of digital baseband (digital baseband, DBB) system, it comprises the low-cost receiver with low noise and minimal power requirements, and the group delay variation distortion that uses the DSP technology to be caused with compensating analog HPFs.
Summary of the invention
The present invention is a kind of DBB receiver in order at least one frequency domain response of the real part of adjusting wireless communication signal and imaginary signal composition to suppress because of being used low cost to simulate the group delay variation distortion that HPFs was caused in the receiver.This receiver comprises a demodulator, digital high-pass filter compensation (HPFC) module, at least one analog real signal path HPF, and at least one analog imaginary HPF.This digital HPFC module has the first predetermined value K by providing
1First compensating signature reduce the cut-off frequency (that is corner frequency (corner frequency)) that simulation HPFs that real part and imaginary signal component frequency domain use is set up.This digital HPFC module has the second predetermined value K by providing
2Second compensating signature of signal is adjusted the gain of real part and imaginary signal composition frequency domain high pass response.
The present invention can be incorporated into a DBB receiver, a wireless transmission/receive unit (WTRU), an integrated circuit (IC), a wireless telecommunication system and method, or any communication means of wanting.
This demodulator has real part and imaginary signal output.This demodulator receives communication signal and in the real part and the imaginary signal composition of real part and imaginary signal output outputting communication signal.Numeral HFPC module has real part and imaginary signal path.The real part signal output of analog real HPF and modulator and the real part signal path communication of digital HPFC module.The group delay variation distortion that the inhibition of numeral HPFC module is caused by at least one analog real and imaginary part HPFs.This digital module can be enabled or forbidden energy selectively.
Numeral HPFC can comprise real part signal input in order to receiving a real part signal composition, and real compensated signal output is in order to export real part compensation output signal.This digital HPFC module can also comprise first and second multiplier, the first, and second and third adder and first sample delay unit.First multiplier can have first and second input and an output.First multiplier can receive tool one first predetermined value (K
1) one first compensating signature.First adder can have first and second input and an output.First input of first adder can be connected to the real part signal input of digital HPFC module, and the output of first adder can be connected to second input of first multiplier.Second adder can have first and second input and an output.First input of second adder can be connected to the output of first multiplier.First sample delay unit can have an input and an output.The input of first sample delay unit can be connected to the output of second adder.Second multiplier can have first and second input and an output.First input of second multiplier can receive has the second predetermined value (K
2) second compensating signature.Second input of second multiplier can be connected to the output of first sample delay unit, second input of second adder, and second input of first adder.First input of the 3rd adder can be connected to first input of first adder.The 3rd adder can have first and second input and an output.Second input of the 3rd adder can be connected to the output of second multiplier.The output of the 3rd adder can be connected to the real compensated signal output of digital HPFC module.
The output of second multiplier can be deducted from real part signal composition via the 3rd adder.First sample delay unit can be deducted from real part signal composition via first adder.
This digital HPFC module can also comprise imaginary signal input in order to reception imaginary signal composition, and imaginary compensated signal output is in order to export imaginary part compensation output signal.This digital HPFC module can also comprise the 3rd and the 4th multiplier, the the four, the five and the 6th adder, and one second sample delay unit.The 3rd multiplier can have first and second input and an output.First input of the 3rd multiplier can receive has the first predetermined value (K
1) first compensating signature.The 4th adder can have first and second input and an output.First input of the 4th adder can be connected to the imaginary signal input of digital HPFC module, and the output of the 4th adder can be connected to second input of the 3rd multiplier.The slender acanthopanax musical instruments used in a Buddhist or Taoist mass can have first and second input and an output.First input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass can be connected to the output of the 3rd multiplier.The input of second sample delay unit can have an input and an output.The input of second sample delay unit can be connected to the output of slender acanthopanax musical instruments used in a Buddhist or Taoist mass.The 4th multiplier can have first and second input and an output.First input of the 4th multiplier can receive has the second offset (K
2) second compensating signature.Second input of the 4th multiplier can be connected to the output of second sample delay unit, second input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass, and second input of the 4th adder.The 6th adder can have first and second input and an output.Second input of the 6th adder can be connected to the output of the 4th multiplier.The output of the 6th adder can be connected to the imaginary compensated signal output of digital HPFC module.
The output of the 4th multiplier can be reduced from the imaginary signal composition via the 6th adder.The output of second sample delay unit can be reduced from the imaginary signal composition via the 4th adder.
Description of drawings
More detailed understanding of the present invention can obtain in conjunction with the accompanying drawings from the description of following preferred embodiment, wherein:
Fig. 1 is the known calcspar that comprises the RF receiver of artificial antenna receiver;
Fig. 2 has the calcspar of DBB RF receiver of the Digital High Pass Filter compensating module of preferred embodiment of the present invention;
The illustration structure of the digital high pass filter compensation module in Fig. 3 presentation graphs 2DBB RF receiver; And
Fig. 4 is the interior employed offset K of high pass filter compensation module of the DBB RF receiver of Fig. 2
1And K
2How to influence the frequency domain response of real part and imaginary signal composition.
Embodiment
Fig. 2 is the calcspar according to the DBB RF receiver 200 of preferred embodiment of the present invention.Though the invention relates to the enforcement on the receiver 200, be familiar with present technique field person and should be appreciated that the present invention is suitable for biography and connects device (transceiver).
The preferably, the method and system that disclose in this place are incorporated in the wireless transmission/receive unit (WTRU).Below, WTRU includes but not limited to user's equipment, mobile radio station, fixing or moving user unit, calling set, or the device that can operate in wireless environment of other any kenel.Feature of the present invention can be incorporated in the integrated circuit (IC) or be designed to comprise in the circuit that is connected to each other assembly in a large number.
The present invention is applicable to and uses time division duplex (TDD), time division multiple access (TDMA), and Frequency Division Duplexing (FDD) (FDD), code division multiple access (CDMA), CDMA 2000, time-division synchronization CDMA (TDSCDMA), and orthogonal frequency division multitask (OFDM) communication system.Yet the present invention is predetermined to be also the communication system applicable to other kenel.
As shown in Figure 2, DBB RF receiver 200 comprises digital high-pass filter compensation (HPFC) module 205, has real part (I) and imaginary part (Q) signal path and is connected to digital I and Q signal output 190,195.Digital module 205 more comprises the output 280,290 and 115 controls of may command device of compensation.
Fig. 3 represents the illustration structure of the digital HPFC module 205 in the DBB RF receiver 200.Numeral HPFC module 205 comprises a digital circuit, in order to the expansion low-frequency composition (for example 5 and 50kHz between) and reduce 175A by simulation HPFs, 175B, 185A, the cut-off frequency that 185B set up (that is corner frequency), so restoration simulation HPFs 175A, 175B, 185A, the spectral shape of the frequency domain response that 185B changed.Therefore, by simulation HPFs175A, 175B, 185A, the distortion that 185B produced obtains to suppress.One or more HPFC modules 205 can be contacted so that the 175A by simulation HPFs, 175B, 185A, the extra compensation of the distortion that 185B caused to be provided with digital HPFC module 205.
This digital HPFC module 205 comprises real part (I) and imaginary part (Q) signal path, passes through real part and imaginary signal composition from the numeral output of ADC 110 thereon respectively.Numeral HPFC module 205 is that a digital filter has the characteristic of selecting, and therefore the frequency domain response of digital HPFC module 205 will recover by the simulation HPFs 175A in the artificial antenna receiver 105,175B, 185A, the frequency characteristic of 185B institute distortion.When the frequency response of digital HPFC module 205 with simulation HPFs 175A, 175B, 185A, the frequency rule of 185B and response when revolving (convolve), by simulation HPFs 175A, 175B, 185A, the distortion that 185B caused is suppressed.In addition, by simulation HPFs175A, 175B, the low frequency composition that 185A, 185B filter out is added to simulation HPFs 175A by providing, 175B, 185A, the digital filter with low pass frequency response of the high-pass equipment response of 185B and by construction again.The real part of numeral HPFC module 205 and imaginary signal path have and remove on each I and Q signal path by simulating HPFs175A, the identical frequency characteristic that the frequency characteristic of the distortion that group delay variation produced due to the 175B, 185A, 185B is used.Therefore, do not comprise distortion by the real part of digital HPFC module 205 and imaginary part compensation output 280,290 real parts of being exported and imaginary compensated signal.Numeral HPFC module can be enabled or forbidden energy selectively, is determined by controller 115.
As shown in Figure 3, digital HPFC module 205 comprises adder 210A, 210B, 230A, 230B, accumulator circuit 215A, 215B and multiplier 220A, 220B, 225A, 225B.Adder 230A, 230B deduct real part and imaginary part HPF compensating signature 245A from real part and imaginary signal composition respectively, and 245B is so that provide the real part and the imaginary part compensation output 280,290 of the high-pass equipment response with expansion.
Accumulator 215A comprises a sample delay unit 235A and an adder 240A.The output of adder 240A is connected to the input of sample delay unit 235A.The output of sample delay unit 235A is connected to first input of adder 240A.The accumulator output signal 250A that accumulator circuit 215A output is reduced from real part signal composition via adder 210A is to produce an accumulator feedback signal 255A.Has the first value K
1And be multiplied by accumulator feedback signal 255A is transfused to second compensation of importing of adder 240A with generation accumulator feedback signal 265A in received first compensating signature of the input 260A of multiplier 220A.Therefore, adder 240A provides a sample signal 270A input to sample delay unit 235A.Signal sample 270A is made up of the accumulator feedback signal 265A and the accumulator output signal 250A of compensation.Has numerical value K
2And be multiplied by accumulator output signal 250A to produce real part HPF compensating signature 245A by second compensating signature that the input 275A of multiplier 225A receives.
Still with reference to Fig. 3, accumulator circuit 215B comprises a sample delay unit 235B and an adder 240B.The output of adder 240B is connected to the input of sample delay unit 235B.The output of sample delay unit 235B is connected to first input of adder 240B.The accumulator output signal 250B that accumulator circuit 215B output is reduced from the imaginary signal composition via adder 210B is to produce an accumulator feedback signal 255B.Has the first value K
1And be multiplied by accumulator feedback signal 255B is transfused to second compensation of importing of adder 240B with generation accumulator feedback signal 265B in received first compensating signature of the input 260B of multiplier 220B.Therefore, adder 240B provides a sample signal 270B input to sample delay unit 235B.Signal sample 270B is made up of the accumulator feedback signal 265B and the accumulator output signal 250B of compensation.Has numerical value K
2And be multiplied by accumulator output signal 250B to produce imaginary part HPF compensating signature 245B by second compensating signature that the input 275B of multiplier 225B receives.
Comprehensive speech, digital HPFC module 205 comprises real part input (output 190 of ADC 110) in order to reception real part signal composition (I), and real compensated signal output 280 is in order to export real part compensation output signal.Numeral HPFC module 205 also comprises first and second multiplier 220A, 225A, the first, second and third adder 210A, 240A, 230A, and one first sample delay unit 235A.The first multiplier 220A has first and second input and an output.The first multiplier 220A has first and second input and an output.The first multiplier 220A receives tool one first predetermined value (K
1) first compensating signature.First adder 210A has first and second input and an output.First input of first adder 210A is connected to the real part signal input (output 190 of ADC 110) of digital HPFC module 205, and the output of first adder 210A can be connected to second input of the first multiplier 220A.Second adder 240A has first and second input and an output.First input of second adder 240A is connected to the output of first multiplier.The first sample delay unit 235A has an input and an output.The input of the first sample delay unit 235A is connected to the output of second adder 240A.The second multiplier 225A has first and second input and an output.The first input 275A of the second multiplier 225A receives has the second predetermined value (K
2) second compensating signature.Second input of the second multiplier 225A is connected to the output of the first sample delay unit 235A, second input of second adder 240A, and second input of first adder 210A.The 3rd adder 230A has first and second input and an output.First input of the 3rd adder 230A can be connected to first input of first adder 210A.Second input of the 3rd adder 230A can be connected to the output of the second multiplier 225A.The output of the 3rd adder 230A can be connected to the real compensated signal output 280 of digital HPFC module 205.
The output of the second multiplier 225A is deducted from real part signal composition via the 3rd adder 230A.The first sample delay unit 235A can be deducted from real part signal composition via first adder 210A.
In addition, this digital HPFC module 205 comprises imaginary signal input (output 195 of ADC 110) in order to reception imaginary signal composition (Q), and imaginary compensated signal output 290 is in order to export imaginary part compensation output signal.This digital HPFC module 205 also comprises the 3rd and the 4th multiplier 220B, 225B, the the four, the five and the 6th adder, 210B, 240B, 230B and the second sample delay unit 235B.The 3rd multiplier 220B has first and second input and an output.The first input 260B of the 3rd multiplier 220B can receive has the first predetermined value (K
1) first compensating signature.The 4th adder 210B has first and second input and an output.First input of the 4th adder 210B is connected to the imaginary signal input (output 195 of ADC 110) of digital HPFC module 205, and the output of the 4th adder 210B is connected to second input of the 3rd multiplier 220B.Slender acanthopanax musical instruments used in a Buddhist or Taoist mass 240B has first and second input and an output.First input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass 240B is connected to the output of the 3rd multiplier 220B.The input of the second sample delay unit 235B has an input and an output.The input of the second sample delay unit 235B is connected to the output of slender acanthopanax musical instruments used in a Buddhist or Taoist mass 240B.The 4th multiplier 225B has first and second input and an output.The first input 275B of the 4th multiplier 225B receives has the second offset (K
2) second compensating signature.Second input of the 4th multiplier 225B is connected to the output of the second sample delay unit 235B, second input of slender acanthopanax musical instruments used in a Buddhist or Taoist mass 240B, and second input of the 4th adder 210B.The 6th adder 230B has first and second input and an output.First input of the 6th adder 230B is connected to first input of the 4th adder 210B.Second input of the 6th adder 230B can be connected to the output of the 4th multiplier 225B.The output of the 6th adder 230B can be connected to the imaginary compensated signal output 290 of digital HPFC module 205.
The output of the 4th multiplier 225B can be reduced from the imaginary signal composition via the 6th adder 230B.The output of the second sample delay unit 235B can be reduced from the imaginary signal composition via the 4th adder 210B.
The cut-off frequency system response of real part and imaginary signal component frequency domain is respectively at the first and the 3rd multiplier 220A, and first of 220B imports 260A, the first predetermined value (K of first compensating signature that 260B receives
1) adjustment and be lowered.The gain response of the high pass response of real part and imaginary part composition frequency domain is respectively at the second and the 4th multiplier 225A, and first of 225B imports 275A, the second predetermined value (K of second compensating signature of 275B
2) reception and be adjusted.
The performance of numeral HPFC module 205 is with numerical value K
1And K
2Be the basis.Fig. 4 represents numerical value K
1And K
2How to influence the spectral shape of the frequency domain response of real part and imaginary signal composition.K
1The adjustment of value changes the cut-off frequency of I and Q from Fc1 to Fc2.Numerical value K
2Adjustment change the gain of high pass response of the frequency domain that digital HPFC module 205 provides by removing accumulator output signal 250A, 250B with 1-k2.
The compensation that is appreciated that I and Q signal composition should be by implementing in substantially high than the chip rate sampling rate of HPFC module 205 (as 10 times sampling rate).
Though the present invention is shown and describes with reference to preferred embodiment especially, is familiar with present technique field person and should be appreciated that in the various changes that can have under the situation that does not break away from the above-described scope of the invention on form and the details.
Claims (31)
1. digital baseband receiver, in order at least one real part of adjusting a wireless communication signal and the frequency domain response of imaginary signal composition, this digital baseband receiver comprises:
One demodulator has real part and imaginary signal output, and this demodulator is in order to receive this communication signal and to export the real part and the imaginary signal composition of this communication signal in this real part and imaginary signal output;
One analog-digital converter has real part and imaginary signal path;
One digital high pass filter compensation module, have real part and imaginary signal path, this real part of this digital high pass filter compensation module and imaginary signal path respectively with this real part of this analog-digital converter and the coupling of imaginary part path, this digital high pass filter compensation module comprises:
The input of one real part signal is in order to receive this real part signal composition;
The output of one real compensated signal is in order to export real part compensation output signal;
First multiplier has first input and second input and the output, one first compensating signature that this first input of this first multiplier has first predetermined value in order to reception;
First adder, has first input and second input and the output, this of this first adder first input is connected to this real part signal input of this digital high pass filter compensation module, and this output of this first adder is connected to this second input of this first multiplier;
Second adder has first input and second input and the output, and this of this second adder first input is connected to this output of this first multiplier;
First sample delay unit has an input and an output, and this input of this first sample delay unit is connected to this output of this second adder;
Second multiplier, has first input and second input and the output, second compensating signature that this first input of this second multiplier has second predetermined value in order to reception, this second input of this second multiplier are connected to the output of this first sample delay unit, this second input of this second adder and this second input of this first adder;
The 3rd adder, has first input and second input and the output, this first input of the 3rd adder is connected to this first input of this first adder, second input of the 3rd adder is connected to this output of this second multiplier, and this output of the 3rd adder is connected to this real compensated signal output of this digital high pass filter compensation module;
The input of one imaginary signal is in order to receive this imaginary signal composition;
The output of one imaginary compensated signal is in order to export imaginary part compensation output signal;
The 3rd multiplier has first input and second input and the output, and this first input of the 3rd multiplier is in order to receive this first compensating signature;
The 4th adder, has first input and second input and the output, this first input of the 4th adder is connected to this imaginary signal input of this digital high pass filter compensation module, and this output of the 4th adder is connected to this second input of the 3rd multiplier;
The slender acanthopanax musical instruments used in a Buddhist or Taoist mass has first input and second input and the output, and this first input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass is connected to this output of the 3rd multiplier;
Second sample delay unit has an input and an output, and this input of this second sample delay unit is connected to this output of this second adder;
The 4th multiplier, has first input and second input and the output, this first input of the 4th multiplier is in order to receive this second compensating signature, and this second input of the 4th multiplier is connected to this output of this second sample delay unit, this second input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass and this second input of the 4th adder; And
The 6th adder, has first input and second input and the output, this first input of the 6th adder is connected to this first input of the 4th adder, this second input of the 6th adder is connected to this output of the 4th multiplier, and this output of the 6th adder is connected to this imaginary compensated signal output of this digital high pass filter compensation module;
At least one analog real signal path high pass filter is with this real part signal path of this this analog-digital converter of real part signal output end of this demodulator and the real part signal path communication of this digital high pass filter compensation module; And
At least one analog imaginary signal path high pass filter, with this imaginary signal output of this demodulator, this imaginary signal path of this analog-digital converter and the imaginary signal path communication of this digital high pass filter compensation module, wherein this digital high pass filter compensation module suppresses the group delay variation distortion that caused by at least one this analog real and imaginary part high pass filter.
2. digital baseband receiver as claimed in claim 1, it is characterized in that, a cut-off frequency of being set up by the analog real signal path high pass filter of this real part signal component frequency domain respond this first compensating signature this first predetermined value adjustment and be lowered.
3. digital baseband receiver as claimed in claim 1 is characterized in that, the high pass response gain of this real part signal composition frequency domain is controlled by this second predetermined value of adjusting this second compensating signature.
4. digital baseband receiver as claimed in claim 1 is characterized in that, this output of this second multiplier is reduced from this real part signal composition via the 3rd adder.
5. digital baseband receiver as claimed in claim 1 is characterized in that, this output of this sample delay unit is reduced from this real part signal composition via this first adder.
6. digital baseband receiver as claimed in claim 1, it is characterized in that, a cut-off frequency of being set up by the analog imaginary signal path high pass filter of this imaginary signal component frequency domain respond this first compensating signature this first predetermined value adjustment and be lowered.
7. digital baseband receiver as claimed in claim 1 is characterized in that, the high pass response gain of this imaginary signal composition frequency domain is controlled by this second predetermined value of adjusting this second compensating signature.
8. the described digital baseband receiver of claim 1 is characterized in that, this output of the 4th multiplier is reduced from this imaginary signal composition via the 6th adder.
9. digital baseband receiver as claimed in claim 1 is characterized in that, this output of this second sample delay unit is reduced from this imaginary signal composition via the 4th adder.
10. digital baseband receiver as claimed in claim 1 is characterized in that this digital high pass filter compensation module is enabled or forbidden energy selectively.
11. a wireless transmission/receive unit, in order at least one real part of adjusting a wireless communication signal and the frequency domain response of imaginary signal composition, this wireless transmission/receive unit comprises:
One demodulator has real part and imaginary signal output, and this demodulator is in order to receive this communication signal and to export the real part and the imaginary signal composition of this communication signal in this real part and imaginary signal output;
One analog-digital converter has real part and imaginary signal path;
One digital high pass filter compensation module, have real part and imaginary signal path, the real part of the real part of The digital high pass filter compensation module and this analog-digital converter of imaginary signal Lu Jing Fen Do With and the coupling of imaginary part path, this digital high pass filter compensation module comprises:
The input of one real part signal is in order to receive this real part signal composition;
The output of one real compensated signal is in order to export real part compensation output signal;
First multiplier has first input and second input and the output, one first compensating signature that this first input of this first multiplier has first predetermined value in order to reception;
First adder, has first input and second input and the output, this of this first adder first input is connected to this real part signal input of this digital high pass filter compensation module, and this output of this first adder is connected to this second input of this first multiplier;
Second adder has first input and second input and the output, and this of this second adder first input is connected to this output of this first multiplier;
First sample delay unit has an input and an output, and this input of this first sample delay unit is connected to this output of this second adder;
Second multiplier, has first input and second input and the output, second compensating signature that this first input of this second multiplier has second predetermined value in order to reception, this second input of this second multiplier are connected to the output of this first sample delay unit, this second input of this second adder and this second input of this first adder;
The 3rd adder, has first input and second input and the output, this first input of the 3rd adder is connected to this first input of this first adder, second input of the 3rd adder is connected to this output of this second multiplier, and this output of the 3rd adder is connected to this real compensated signal output of this digital high pass filter compensation module;
The input of one imaginary signal is in order to receive this imaginary signal composition;
The output of one imaginary compensated signal is in order to export imaginary part compensation output signal;
The 3rd multiplier has first input and second input and the output, and this first input of the 3rd multiplier is in order to receive this first compensating signature;
The 4th adder, has first input and second input and the output, this first input of the 4th adder is connected to this imaginary signal input of this digital high pass filter compensation module, and this output of the 4th adder is connected to this second input of the 3rd multiplier;
The slender acanthopanax musical instruments used in a Buddhist or Taoist mass has first input and second input and the output, and this first input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass is connected to this output of the 3rd multiplier;
Second sample delay unit has an input and an output, and this input of this second sample delay unit is connected to this output of this second adder;
The 4th multiplier, has first input and second input and the output, this first input of the 4th multiplier is in order to receive this second compensating signature, and this second input of the 4th multiplier is connected to this output of this second sample delay unit, this second input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass and this second input of the 4th adder; And
The 6th adder, has first input and second input and the output, this first input of the 6th adder is connected to this first input of the 4th adder, this second input of the 6th adder is connected to this output of the 4th multiplier, and this output of the 6th adder is connected to this imaginary compensated signal output of this digital high pass filter compensation module;
At least one analog real signal path high pass filter is with this real part signal output end of this demodulator, this real part signal path of this analog-digital converter and the real part signal path communication of this digital high pass filter compensation module; And
At least one analog imaginary signal path high pass filter, with this imaginary signal output of this demodulator, this imaginary signal path of this analog-digital converter and the imaginary signal path communication of this digital high pass filter compensation module, wherein this digital high pass filter compensation module suppresses the group delay variation distortion that caused by at least one this analog real and imaginary part high pass filter.
12. wireless transmission/receive unit as claimed in claim 11, it is characterized in that, a cut-off frequency of being set up by the analog real signal path high pass filter of this real part signal component frequency domain respond this first compensating signature this first predetermined value adjustment and be lowered.
13. wireless transmission/receive unit as claimed in claim 11 is characterized in that, the high pass response gain of this real part signal composition frequency domain is controlled by this second predetermined value of adjusting this second compensating signature.
14. wireless transmission/receive unit as claimed in claim 11 is characterized in that, this output of this second multiplier is reduced from this real part signal composition via the 3rd adder.
15. wireless transmission/receive unit as claimed in claim 11 is characterized in that, the output of this sample delay unit is reduced from this real part signal composition via this first adder.
16. wireless transmission/receive unit as claimed in claim 11, it is characterized in that, a cut-off frequency of being set up by the analog imaginary signal path high pass filter of this imaginary signal component frequency domain respond this first compensating signature this first predetermined value adjustment and be lowered.
17. wireless transmission/receive unit as claimed in claim 11 is characterized in that, the high pass response gain of this imaginary signal composition frequency domain is controlled by this second predetermined value of adjusting this second compensating signature.
18. the described wireless transmission/receive unit of claim 11 is characterized in that, this output of this second multiplier is reduced from this imaginary signal composition via the 3rd adder.
19. wireless transmission/receive unit as claimed in claim 11 is characterized in that, this output of this sample delay unit is reduced from this imaginary signal composition via this first adder.
20. wireless transmission/receive unit as claimed in claim 11 is characterized in that, this digital high pass filter compensation module is enabled or forbidden energy selectively.
21. an integrated circuit, in order at least one real part of adjusting a wireless communication signal and the frequency domain response of imaginary signal composition, this integrated circuit comprises:
One demodulator has real part and imaginary signal output, and this demodulator is in order to receive this communication signal and to export the real part and the imaginary signal composition of this communication signal in this real part and imaginary signal output;
One analog-digital converter has real part and imaginary signal path;
One digital high pass filter compensation module, have real part and imaginary signal path, the real part of this digital high pass filter compensation module and imaginary signal path respectively with the real part of this analog-digital converter and the coupling of imaginary part path, this digital high pass filter compensation module comprises:
The input of one real part signal is in order to receive this real part signal composition;
The output of one real compensated signal is in order to export real part compensation output signal;
First multiplier has first input and second input and the output, one first compensating signature that this first input of this first multiplier has first predetermined value in order to reception;
First adder, has first input and second input and the output, this of this first adder first input is connected to this real part signal input of this digital high pass filter compensation module, and this output of this first adder is connected to this second input of this first multiplier;
Second adder has first input and second input and the output, and this of this second adder first input is connected to this output of this first multiplier;
First sample delay unit has an input and an output, and this input of this first sample delay unit is connected to this output of this second adder;
Second multiplier, has first input and second input and the output, second compensating signature that this first input of this second multiplier has second predetermined value in order to reception, this second input of this second multiplier are connected to the output of this first sample delay unit, this second input of this second adder and this second input of this first adder;
The 3rd adder, has first input and second input and the output, this first input of the 3rd adder is connected to this first input of this first adder, second input of the 3rd adder is connected to this output of this second multiplier, and this output of the 3rd adder is connected to this real compensated signal output of this digital high pass filter compensation module;
The input of one imaginary signal is in order to receive this imaginary signal composition;
The output of one imaginary compensated signal is in order to export imaginary part compensation output signal;
The 3rd multiplier has first input and second input and the output, and this first input of the 3rd multiplier is in order to receive this first compensating signature;
The 4th adder, has first input and second input and the output, this first input of the 4th adder is connected to this imaginary signal input of this digital high pass filter compensation module, and this output of the 4th adder is connected to this second input of the 3rd multiplier;
The slender acanthopanax musical instruments used in a Buddhist or Taoist mass has first input and second input and the output, and this first input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass is connected to this output of the 3rd multiplier;
Second sample delay unit has an input and an output, and this input of this second sample delay unit is connected to this output of this second adder;
The 4th multiplier, has first input and second input and the output, this first input of the 4th multiplier is in order to receive this second compensating signature, and this second input of the 4th multiplier is connected to this output of this second sample delay unit, this second input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass and this second input of the 4th adder; And
The 6th adder, has first input and second input and the output, this first input of the 6th adder is connected to this first input of the 4th adder, this second input of the 6th adder is connected to this output of the 4th multiplier, and this output of the 6th adder is connected to this imaginary compensated signal output of this digital high pass filter compensation module;
At least one analog real signal path high pass filter is with this real part signal output end of this demodulator, this real part signal path of this analog-digital converter and the real part signal path communication of this digital high pass filter compensation module; And
At least one analog imaginary signal path high pass filter, with this imaginary signal output of this demodulator, this imaginary signal path of this analog-digital converter and the imaginary signal path communication of this digital high pass filter compensation module, wherein this digital high pass filter compensation module suppresses the group delay variation distortion that caused by at least one this analog real and imaginary part high pass filter.
22. integrated circuit as claimed in claim 21, it is characterized in that the adjustment of this first predetermined value of cut-off frequency system this first compensating signature of response of being set up by the analog real signal path high pass filter of this real part signal component frequency domain and being lowered.
23. integrated circuit as claimed in claim 21 is characterized in that, the high pass response gain of this real part signal composition frequency domain is controlled by this second predetermined value of adjusting this second compensating signature.
24. integrated circuit as claimed in claim 21 is characterized in that, this output of this second multiplier is reduced from this real part signal composition via the 3rd adder.
25. integrated circuit as claimed in claim 21 is characterized in that, this output of this first sample delay unit is reduced from this real part signal composition via this first adder.
26. integrated circuit as claimed in claim 21 is characterized in that, a cut-off frequency of being set up by the analog imaginary signal path high pass filter of this imaginary signal component frequency domain respond this first compensating signature this first predetermined value adjustment and be lowered.
27. integrated circuit as claimed in claim 21 is characterized in that, the high pass response gain of this imaginary signal composition frequency domain is controlled by this second predetermined value of adjusting this second compensating signature.
28. the described integrated circuit of claim 21 is characterized in that, this output of the 4th multiplier is reduced from this imaginary signal composition via the 6th adder.
29. integrated circuit as claimed in claim 21 is characterized in that, this output of this second sample delay unit is reduced from this imaginary signal composition via the 4th adder.
30. integrated circuit as claimed in claim 21 is characterized in that, this digital high pass filter compensation module is enabled or forbidden energy selectively.
31. the digital high pass filter compensation module with real part and imaginary signal path, this digital high pass filter compensation module comprises:
The input of one real part signal is in order to receive the real part signal composition of wireless telecommunication system;
The output of one real compensated signal is in order to export real part compensation output signal;
First multiplier has first input and second input and the output, one first compensating signature that this first input of this first multiplier has first predetermined value in order to reception;
First adder, has first input and second input and the output, this of this first adder first input is connected to this real part signal input of this digital high pass filter compensation module, and this output of this first adder is connected to this second input of this first multiplier;
Second adder has first input and second input and the output, and this of this second adder first input is connected to this output of this first multiplier;
First sample delay unit has an input and an output, and this input of this first sample delay unit is connected to this output of this second adder;
Second multiplier, has first input and second input and the output, second compensating signature that this first input of this second multiplier has second predetermined value in order to reception, this second input of this second multiplier are connected to the output of this first sample delay unit, this second input of this second adder and this second input of this first adder;
The 3rd adder, has first input and second input and the output, this first input of the 3rd adder is connected to this first input of this first adder, second input of the 3rd adder is connected to this output of this second multiplier, and this output of the 3rd adder is connected to this real compensated signal output of this digital high pass filter compensation module;
The input of one imaginary signal is in order to receive the imaginary signal composition of this wireless telecommunication system;
The output of one imaginary compensated signal is in order to export imaginary part compensation output signal;
The 3rd multiplier has first input and second input and the output, and this first input of the 3rd multiplier is in order to receive this first compensating signature;
The 4th adder, has first input and second input and the output, this first input of the 4th adder is connected to this imaginary signal input of this digital high pass filter compensation module, and this output of the 4th adder is connected to this second input of the 3rd multiplier;
The slender acanthopanax musical instruments used in a Buddhist or Taoist mass has first input and second input and the output, and this first input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass is connected to this output of the 3rd multiplier;
Second sample delay unit has an input and an output, and this input of this second sample delay unit is connected to this output of this second adder;
The 4th multiplier, has first input and second input and the output, this first input of the 4th multiplier is in order to receive this second compensating signature, and this second input of the 4th multiplier is connected to this output of this second sample delay unit, this second input of this slender acanthopanax musical instruments used in a Buddhist or Taoist mass and this second input of the 4th adder; And
The 6th adder, has first input and second input and the output, this first input of the 6th adder is connected to this first input of the 4th adder, this second input of the 6th adder is connected to this output of the 4th multiplier, and this output of the 6th adder is connected to this imaginary compensated signal output of this digital high pass filter compensation module.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US48283403P | 2003-06-25 | 2003-06-25 | |
| US60/482,834 | 2003-06-25 | ||
| US10/747,644 | 2003-12-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910139420A Division CN101621285A (en) | 2003-06-25 | 2004-05-20 | Digital high pass filter compensation module and wireless transmission/reception unit |
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| CN1813398A CN1813398A (en) | 2006-08-02 |
| CN100505516C true CN100505516C (en) | 2009-06-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910139420A Pending CN101621285A (en) | 2003-06-25 | 2004-05-20 | Digital high pass filter compensation module and wireless transmission/reception unit |
| CNB2004800180812A Expired - Fee Related CN100505516C (en) | 2003-06-25 | 2004-05-20 | Digital baseband receiver including a high pass filter compensation module for suppressing group delay variation distortion due to deficiencies of analog high pass filter |
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| Application Number | Title | Priority Date | Filing Date |
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| CN200910139420A Pending CN101621285A (en) | 2003-06-25 | 2004-05-20 | Digital high pass filter compensation module and wireless transmission/reception unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2010503881A (en) * | 2006-09-13 | 2010-02-04 | テレフオンアクチーボラゲット エル エム エリクソン（パブル） | Method and apparatus for voice / acoustic transmitter and receiver |
| CN101212436B (en) * | 2006-12-25 | 2010-11-03 | 联芯科技有限公司 | High pass filter frequency response characteristic compensator and method and zero intermediate frequency receiver |
| CN103905070B (en) * | 2012-12-28 | 2016-05-25 | 瑞昱半导体股份有限公司 | Device for signalling and method, balanced compensated signal receiving device and method |
| CN103944533B (en) * | 2014-04-04 | 2017-08-18 | 江苏卓胜微电子有限公司 | Fluting wave filter |
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2004
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| CN1813398A (en) | 2006-08-02 |
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