CN100505162C

CN100505162C - Method for manufacturing wire of semiconductor component

Info

Publication number: CN100505162C
Application number: CNB021060436A
Authority: CN
Inventors: 郭东政
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2002-04-09
Filing date: 2002-04-09
Publication date: 2009-06-24
Anticipated expiration: 2022-04-09
Also published as: CN1450596A

Abstract

This invention relates to a line process method for a semiconductor element providing a base with a deposition layer then forming a photoresist layer on it, and a blend is used for exerusing a microimage technology to patternize the photoresist layer in which, then etching is processed with the photoresist layer as the cover to form several lines. Considering the proximal effect and microloud effect brough with the etching technology line width difference between zones of high density pattern and zones of low density pattern should be reduced to the minimum.

Description

The manufacture method of the line of semiconductor element

Technical field

The invention relates to a kind of manufacture method of semiconductor element, and particularly relevant for a kind of manufacture method of line of semiconductor element.

Background technology

Under the more and more higher situation of the requirement of circuit integration, the design of entire circuit element size also is forced to advance toward the direction that size does not stop to dwindle.And the photoetching technique in the semiconductor technology (photolithography) influences the precision of component size especially greatly.Because be that etching, doping process all need to reach by photoetching process, and in the element integrated level of whole semi-conductor industry, whether can continue toward live width propelling littler below the 0.15 μ m, also be decided by the development of photoetching process technology.For in response to this demand, some methods that improve the mask resolution are constantly put forward, as the optical near-correction method (optical proximity correction, OPC).

Generally below 0.18 micron the time,, make the diffraction problems of light be tending towards serious because the size of the hole of pattern, lines is and then dwindled.So eliminate critical size (the critical dimension that is caused because of proximity effcet (Proximity Effect) by the optical near-correction method; CD) bias phenomenon.Wherein, proximity effcet is on wafer the time, to make light beam extended owing to light beam can produce scattering phenomenon by the graphic pattern projection on the mask on the one hand when light beam.On the other hand, the photoresist layer that light beam can be by wafer surface reflected via the semiconductor-based end of wafer again, produced the phenomenon of interfering, therefore can repeated exposure, and change exposure actual on photoresist layer.This kind phenomenon when the critical size of technology hour obvious more more, especially when its critical size approaches the wavelength of light source.

Yet, known technology utilizes optical near-correction method (OPC) to go to promote illumination resolution, photoresist size after so that develop can reach after the living size with default value, but often different via the prepared pattern of etch process again with predetermined size, and make component size produce deviation.This is because etch process (etchingprocess) regular meeting after the photoetching technique causes the generation of micro loading effect (microloading effect) as can be known after inquiring into, and so-called micro loading effect is made a general reference exactly in etch-rate (etching rate), pattern form (shape) or other etching characteristic (etching attribute) unexpected change is arranged.For example the shape of the zone (dense feature region) of high pattern density and the etched pattern (etched feature) in the zone (few and isolated feature region) of low pattern density or single pattern or etch-rate can produce and not want the variation that takes place in substrate.This is normally because the etch-rate of single pattern than the etch-rate height of high pattern density, so produced difference on critical size, and then causes the size of whole semiconductor element to produce deviation.

So mostly the method that solves the micro loading effect in the etch process at present is to change engraving method (etching recipe), for example gas used of etching, energy of etch process or the like.But list just changes engraving method, and the effect that reduces micro loading effect is still limited, but also can cause the rising of process complexity.

Summary of the invention

Purpose of the present invention just provides a kind of manufacture method of line of semiconductor element, to produce the line in the same live width of different pattern density area.

A further object of the present invention provides a kind of manufacture method of line of semiconductor element, can avoid the problem of known technology generation semiconductor element dimensional discrepancy.

Another object of the present invention provides a kind of manufacture method of line of semiconductor element, can simplify the technology of the line of making semiconductor element.

According to above-mentioned and other purpose, the present invention proposes a kind of manufacture method of line of semiconductor element, and comprising provides the substrate with a sedimentary deposit, forms a photoresist layer subsequently on sedimentary deposit.Then, use a mask to implement a photoetching process, with the patterning photoresist layer, wherein this mask considers that proximity effcet and etched micro loading effect design.Then, as etch mask, sedimentary deposit is carried out an etch process with the patterning photoresist layer, so as to forming several lines, and these lines have pattern density higher zone and the low pattern density or the zone of single pattern.At last, remove the patterning photoresist layer.

The present invention proposes a kind of manufacture method of pattern of semiconductor element in addition, comprise the substrate with a sedimentary deposit is provided, form a patterning photoresist layer subsequently on sedimentary deposit, wherein the pattern of this patterning photoresist layer considers that proximity effcet and etched micro loading effect make.Then, as etch mask, sedimentary deposit is carried out an etch process, so as to forming several patterns with the patterning photoresist layer.Also can comprise the step of removing the patterning photoresist layer at last.

Because the present invention is when the patterning photoresist layer, consider proximity effcet and the micro loading effect that etch process brought thereafter in the lump, so behind the process etch process, the live width difference in the zone that zone that can pattern density is higher and pattern density are lower contracts to minimum, even can be in the zone of different pattern density during pattern-making, obtain and the predetermined the most approaching pattern of pattern dimension that forms, and the technology of global patternization is also simple than known method.

Description of drawings

Figure 1A to Fig. 1 C is the manufacturing process profile according to the line of a kind of semiconductor element of the embodiment of the invention.

100: substrate

102: the zone of high pattern density

104: the zone of low pattern density or single pattern

106,106a, 106b: layer

108,108a, 108b: photoresist layer

110: mask

112,114a, 114b: the width of photoresist layer

116,118: the width of pattern

Embodiment

Please refer to Figure 1A, a substrate 100 at first is provided, this substrate 100 comprises zone (dense feature region) the 102 and one low pattern density of a high pattern density or the zone (few and isolated feature region) 104 of single pattern.Then, form one deck 106 in substrate 100, this layer 106 is a sedimentary deposit for example, and this sedimentary deposit can be a polysilicon layer.Then, on this layer 106, form a photoresist layer 108.

Then, please refer to Figure 1B, use a mask 110 to implement photoetching process, with patterning photoresist layer 108, wherein mask 110 is considered proximity effcet (Proximity Effect) design with etched micro loading effect (microloading effect), omit the detailed pattern of mask 110 among the Yu Bentu, mainly be because the pattern of mask 110 can change according to required, for example at the single area (ISO region) of mask 110 and the other different size pattern (sizing pattern) and the scattering strip (scattering bar) of adding of line of close quarters (DENSE region), make the difference of the photoresist width according pattern density that post-exposure goes out, produce the different variation of width, to cooperate the influence of micro loading effect.

Please continue with reference to Figure 1B, if preboarding is formed in the live width of intensive line and the line in the zone 104 of low pattern density or single pattern in the zone 102 of high pattern density when being identical, for proximity effcet and the micro loading effect of preventing, be wider than the live width of the predetermined intensive line that forms at the width 112 of the photoresist layer 108a pattern in the zone 102 of high pattern density; And the width 114b in the bottom of the photoresist layer 108b in the zone 104 of low pattern density or single pattern equals the live width of the predetermined line that forms; And the width 114a at the top of photoresist layer 108b is less than the width 114b of the bottom of photoresist layer 108b.

At last, please refer to Fig. 1 C, as etch mask, its lower floor 106 is carried out etch process with the photoresist layer 108a that is patterned and 108b (please refer to Figure 1B), so as to forming several lines 106a and 106b, wherein the line 106a of these formation and 106b are as grid for example.Because photoresist layer 108a and 108b consider proximity effcet and etched micro loading effect, after so etching is finished, the live width difference of line 106b that is positioned at the zone 104 of the line 106a in zone 102 of high pattern density and low pattern density or single pattern can contract to minimum, even can reach same size.Subsequently, can remove photoresist layer 108a and the 108b that is patterned.

By the invention described above preferred embodiment as can be known, apply the present invention to and have following advantage less:

1) since the present invention when the patterning photoresist layer, consider proximity effcet and the micro loading effect that etch process brought thereafter in the lump, so behind the process etch process, the live width difference in the zone that zone that can pattern density is higher and pattern density are lower contracts to minimum.

2) the present invention is when the patterning photoresist layer, consider proximity effcet and the micro loading effect that etch process brought thereafter in the lump, so no matter be, all can obtain and the predetermined the most approaching pattern of pattern dimension that forms in the higher zone of pattern density or in the lower zone of pattern density.

3) the present invention has considered proximity effcet and the micro loading effect that etch process brought thereafter in the lump when the patterning photoresist layer, so can simplify the technology of the line of making semiconductor element.

4) the present invention considers proximity effcet and micro loading effect in the lump when the patterning photoresist layer, so but the technology of simplified patternization causes the technology of global patternization simple than known method.

Claims

1, a kind of manufacture method of line of semiconductor subassembly is characterized in that, this method comprises:

Substrate with one deck is provided;

Go up formation one photoresist layer in this layer;

Use a mask to implement photoetching process, with this photoresist layer of patterning, form a plurality of intensive photoresist patterns and a plurality of single photoresist pattern, wherein this mask is considered proximity effcet and etched micro loading effect and is designed;

With this photoresist layer of being patterned as etching mask, this layer is carried out an etch process, so as to forming many lines, these lines are divided into many intensive lines that form with aforementioned intensive photoresist pattern and many single lines that form with aforementioned single photoresist pattern, wherein:

Each intensive photoresist pattern is wider than each intensive line;

The width of the bottom of the photoresist pattern that each is single equals each single line; And

The width at the top of the photoresist pattern that each is single is less than the width of the bottom of each single photoresist pattern; And

This photoresist layer that removal is patterned.

2, the manufacture method of the line of semiconductor subassembly as claimed in claim 1 is characterized in that, the live width of a plurality of lines is identical.

3, the manufacture method of the line of semiconductor subassembly as claimed in claim 1 is characterized in that, a plurality of lines comprise grid.

4, the manufacture method of the line of semiconductor subassembly as claimed in claim 1 is characterized in that, this layer comprises a sedimentary deposit.

5, the manufacture method of the line of semiconductor subassembly as claimed in claim 4 is characterized in that, this sedimentary deposit comprises polysilicon layer.

6, a kind of manufacture method of pattern of semiconductor subassembly, a plurality of single patterns that are suitable for forming a plurality of intensive pattern of high pattern density and low pattern density is characterized in that this method comprises in a substrate:

This substrate with one deck is provided;

Go up to form a patterning photoresist layer in this layer, the pattern of this patterning photoresist layer is to consider proximity effcet and etched micro loading effect and make, wherein

Each intensive photoresist pattern is wider than each intensive pattern;

The width of the bottom of the photoresist pattern that each is single equals each single pattern; And

Utilize this patterning photoresist layer as etching mask, this layer is carried out an etch process, in this substrate, to form a plurality of intensive patterns and a plurality of single pattern.

7, the manufacture method of the pattern of semiconductor subassembly as claimed in claim 6 is characterized in that, behind this etch process, more comprises and removes this patterning photoresist layer.

8, the manufacture method of the pattern of semiconductor subassembly as claimed in claim 6 is characterized in that, this layer comprises sedimentary deposit.

9, the manufacture method of the pattern of semiconductor subassembly as claimed in claim 8 is characterized in that, this sedimentary deposit comprises polysilicon layer.